1 files changed, 21 insertions, 12 deletions

diff --git a/drivers/edac/tile_edac.c b/drivers/edac/tile_edac.c
index e99d00976189..7bb4614730db 100644
--- a/drivers/edac/tile_edac.c
+++ b/drivers/edac/tile_edac.c
@@ -71,7 +71,10 @@ static void tile_edac_check(struct mem_ctl_info *mci)
         if (mem_error.sbe_count != priv->ce_count) {
                 dev_dbg(mci->dev, "ECC CE err on node %d\n", priv->node);
                 priv->ce_count = mem_error.sbe_count;
-                edac_mc_handle_ce(mci, 0, 0, 0, 0, 0, mci->ctl_name);
+                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+                                     0, 0, 0,
+                                     0, 0, -1,
+                                     mci->ctl_name, "", NULL);
         }
 }
 
@@ -84,6 +87,7 @@ static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
         struct csrow_info       *csrow = &mci->csrows[0];
         struct tile_edac_priv   *priv = mci->pvt_info;
         struct mshim_mem_info   mem_info;
+        struct dimm_info *dimm = csrow->channels[0].dimm;
 
         if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
                 sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
@@ -93,27 +97,25 @@ static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
         }
 
         if (mem_info.mem_ecc)
-                csrow->edac_mode = EDAC_SECDED;
+                dimm->edac_mode = EDAC_SECDED;
         else
-                csrow->edac_mode = EDAC_NONE;
+                dimm->edac_mode = EDAC_NONE;
         switch (mem_info.mem_type) {
         case DDR2:
-                csrow->mtype = MEM_DDR2;
+                dimm->mtype = MEM_DDR2;
                 break;
 
         case DDR3:
-                csrow->mtype = MEM_DDR3;
+                dimm->mtype = MEM_DDR3;
                 break;
 
         default:
                 return -1;
         }
 
-        csrow->first_page = 0;
-        csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
-        csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
-        csrow->grain = TILE_EDAC_ERROR_GRAIN;
-        csrow->dtype = DEV_UNKNOWN;
+        dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
+        dimm->grain = TILE_EDAC_ERROR_GRAIN;
+        dimm->dtype = DEV_UNKNOWN;
 
         return 0;
 }
@@ -123,6 +125,7 @@ static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
         char                    hv_file[32];
         int                     hv_devhdl;
         struct mem_ctl_info     *mci;
+        struct edac_mc_layer    layers[2];
         struct tile_edac_priv   *priv;
         int                     rc;
 
@@ -132,8 +135,14 @@ static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
                 return -EINVAL;
 
         /* A TILE MC has a single channel and one chip-select row. */
-        mci = edac_mc_alloc(sizeof(struct tile_edac_priv),
-                TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id);
+        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+        layers[0].size = TILE_EDAC_NR_CSROWS;
+        layers[0].is_virt_csrow = true;
+        layers[1].type = EDAC_MC_LAYER_CHANNEL;
+        layers[1].size = TILE_EDAC_NR_CHANS;
+        layers[1].is_virt_csrow = false;
+        mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
+                            sizeof(struct tile_edac_priv));
         if (mci == NULL)
                 return -ENOMEM;
         priv = mci->pvt_info;