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path: root/drivers/edac/r82600_edac.c
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Diffstat (limited to 'drivers/edac/r82600_edac.c')
-rw-r--r--drivers/edac/r82600_edac.c48
1 files changed, 23 insertions, 25 deletions
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index e1cacd164f31..f854debd5533 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -140,7 +140,7 @@ static void r82600_get_error_info(struct mem_ctl_info *mci,
140{ 140{
141 struct pci_dev *pdev; 141 struct pci_dev *pdev;
142 142
143 pdev = to_pci_dev(mci->dev); 143 pdev = to_pci_dev(mci->pdev);
144 pci_read_config_dword(pdev, R82600_EAP, &info->eapr); 144 pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
145 145
146 if (info->eapr & BIT(0)) 146 if (info->eapr & BIT(0))
@@ -179,11 +179,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
179 error_found = 1; 179 error_found = 1;
180 180
181 if (handle_errors) 181 if (handle_errors)
182 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 182 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
183 page, 0, syndrome, 183 page, 0, syndrome,
184 edac_mc_find_csrow_by_page(mci, page), 184 edac_mc_find_csrow_by_page(mci, page),
185 0, -1, 185 0, -1,
186 mci->ctl_name, "", NULL); 186 mci->ctl_name, "");
187 } 187 }
188 188
189 if (info->eapr & BIT(1)) { /* UE? */ 189 if (info->eapr & BIT(1)) { /* UE? */
@@ -191,11 +191,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
191 191
192 if (handle_errors) 192 if (handle_errors)
193 /* 82600 doesn't give enough info */ 193 /* 82600 doesn't give enough info */
194 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 194 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
195 page, 0, 0, 195 page, 0, 0,
196 edac_mc_find_csrow_by_page(mci, page), 196 edac_mc_find_csrow_by_page(mci, page),
197 0, -1, 197 0, -1,
198 mci->ctl_name, "", NULL); 198 mci->ctl_name, "");
199 } 199 }
200 200
201 return error_found; 201 return error_found;
@@ -205,7 +205,7 @@ static void r82600_check(struct mem_ctl_info *mci)
205{ 205{
206 struct r82600_error_info info; 206 struct r82600_error_info info;
207 207
208 debugf1("MC%d: %s()\n", mci->mc_idx, __func__); 208 edac_dbg(1, "MC%d\n", mci->mc_idx);
209 r82600_get_error_info(mci, &info); 209 r82600_get_error_info(mci, &info);
210 r82600_process_error_info(mci, &info, 1); 210 r82600_process_error_info(mci, &info, 1);
211} 211}
@@ -230,19 +230,19 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
230 row_high_limit_last = 0; 230 row_high_limit_last = 0;
231 231
232 for (index = 0; index < mci->nr_csrows; index++) { 232 for (index = 0; index < mci->nr_csrows; index++) {
233 csrow = &mci->csrows[index]; 233 csrow = mci->csrows[index];
234 dimm = csrow->channels[0].dimm; 234 dimm = csrow->channels[0]->dimm;
235 235
236 /* find the DRAM Chip Select Base address and mask */ 236 /* find the DRAM Chip Select Base address and mask */
237 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); 237 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
238 238
239 debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar); 239 edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
240 240
241 row_high_limit = ((u32) drbar << 24); 241 row_high_limit = ((u32) drbar << 24);
242/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ 242/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
243 243
244 debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n", 244 edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
245 __func__, index, row_high_limit, row_high_limit_last); 245 index, row_high_limit, row_high_limit_last);
246 246
247 /* Empty row [p.57] */ 247 /* Empty row [p.57] */
248 if (row_high_limit == row_high_limit_last) 248 if (row_high_limit == row_high_limit_last)
@@ -277,14 +277,13 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
277 u32 sdram_refresh_rate; 277 u32 sdram_refresh_rate;
278 struct r82600_error_info discard; 278 struct r82600_error_info discard;
279 279
280 debugf0("%s()\n", __func__); 280 edac_dbg(0, "\n");
281 pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); 281 pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
282 pci_read_config_dword(pdev, R82600_EAP, &eapr); 282 pci_read_config_dword(pdev, R82600_EAP, &eapr);
283 scrub_disabled = eapr & BIT(31); 283 scrub_disabled = eapr & BIT(31);
284 sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); 284 sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
285 debugf2("%s(): sdram refresh rate = %#0x\n", __func__, 285 edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
286 sdram_refresh_rate); 286 edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
287 debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
288 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
289 layers[0].size = R82600_NR_CSROWS; 288 layers[0].size = R82600_NR_CSROWS;
290 layers[0].is_virt_csrow = true; 289 layers[0].is_virt_csrow = true;
@@ -295,8 +294,8 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
295 if (mci == NULL) 294 if (mci == NULL)
296 return -ENOMEM; 295 return -ENOMEM;
297 296
298 debugf0("%s(): mci = %p\n", __func__, mci); 297 edac_dbg(0, "mci = %p\n", mci);
299 mci->dev = &pdev->dev; 298 mci->pdev = &pdev->dev;
300 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 299 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
301 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 300 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
302 /* FIXME try to work out if the chip leads have been used for COM2 301 /* FIXME try to work out if the chip leads have been used for COM2
@@ -311,8 +310,8 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
311 310
312 if (ecc_enabled(dramcr)) { 311 if (ecc_enabled(dramcr)) {
313 if (scrub_disabled) 312 if (scrub_disabled)
314 debugf3("%s(): mci = %p - Scrubbing disabled! EAP: " 313 edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
315 "%#0x\n", __func__, mci, eapr); 314 mci, eapr);
316 } else 315 } else
317 mci->edac_cap = EDAC_FLAG_NONE; 316 mci->edac_cap = EDAC_FLAG_NONE;
318 317
@@ -329,15 +328,14 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
329 * type of memory controller. The ID is therefore hardcoded to 0. 328 * type of memory controller. The ID is therefore hardcoded to 0.
330 */ 329 */
331 if (edac_mc_add_mc(mci)) { 330 if (edac_mc_add_mc(mci)) {
332 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 331 edac_dbg(3, "failed edac_mc_add_mc()\n");
333 goto fail; 332 goto fail;
334 } 333 }
335 334
336 /* get this far and it's successful */ 335 /* get this far and it's successful */
337 336
338 if (disable_hardware_scrub) { 337 if (disable_hardware_scrub) {
339 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n", 338 edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
340 __func__);
341 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); 339 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
342 } 340 }
343 341
@@ -352,7 +350,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
352 __func__); 350 __func__);
353 } 351 }
354 352
355 debugf3("%s(): success\n", __func__); 353 edac_dbg(3, "success\n");
356 return 0; 354 return 0;
357 355
358fail: 356fail:
@@ -364,7 +362,7 @@ fail:
364static int __devinit r82600_init_one(struct pci_dev *pdev, 362static int __devinit r82600_init_one(struct pci_dev *pdev,
365 const struct pci_device_id *ent) 363 const struct pci_device_id *ent)
366{ 364{
367 debugf0("%s()\n", __func__); 365 edac_dbg(0, "\n");
368 366
369 /* don't need to call pci_enable_device() */ 367 /* don't need to call pci_enable_device() */
370 return r82600_probe1(pdev, ent->driver_data); 368 return r82600_probe1(pdev, ent->driver_data);
@@ -374,7 +372,7 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
374{ 372{
375 struct mem_ctl_info *mci; 373 struct mem_ctl_info *mci;
376 374
377 debugf0("%s()\n", __func__); 375 edac_dbg(0, "\n");
378 376
379 if (r82600_pci) 377 if (r82600_pci)
380 edac_pci_release_generic_ctl(r82600_pci); 378 edac_pci_release_generic_ctl(r82600_pci);