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path: root/drivers/edac/mce_amd.c
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Diffstat (limited to 'drivers/edac/mce_amd.c')
-rw-r--r--drivers/edac/mce_amd.c47
1 files changed, 14 insertions, 33 deletions
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index f78c1c54dbd5..58586d59bf8e 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -138,6 +138,15 @@ static const char * const mc5_mce_desc[] = {
138 "Retire status queue" 138 "Retire status queue"
139}; 139};
140 140
141static const char * const mc6_mce_desc[] = {
142 "Hardware Assertion",
143 "Free List",
144 "Physical Register File",
145 "Retire Queue",
146 "Scheduler table",
147 "Status Register File",
148};
149
141static bool f12h_mc0_mce(u16 ec, u8 xec) 150static bool f12h_mc0_mce(u16 ec, u8 xec)
142{ 151{
143 bool ret = false; 152 bool ret = false;
@@ -432,8 +441,8 @@ static bool k8_mc2_mce(u16 ec, u8 xec)
432 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); 441 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
433 else if (xec == 0x0) { 442 else if (xec == 0x0) {
434 if (TLB_ERROR(ec)) 443 if (TLB_ERROR(ec))
435 pr_cont(": %s error in a Page Descriptor Cache or " 444 pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
436 "Guest TLB.\n", TT_MSG(ec)); 445 TT_MSG(ec));
437 else if (BUS_ERROR(ec)) 446 else if (BUS_ERROR(ec))
438 pr_cont(": %s/ECC error in data read from NB: %s.\n", 447 pr_cont(": %s/ECC error in data read from NB: %s.\n",
439 R4_MSG(ec), PP_MSG(ec)); 448 R4_MSG(ec), PP_MSG(ec));
@@ -672,38 +681,10 @@ static void decode_mc6_mce(struct mce *m)
672 681
673 pr_emerg(HW_ERR "MC6 Error: "); 682 pr_emerg(HW_ERR "MC6 Error: ");
674 683
675 switch (xec) { 684 if (xec > 0x5)
676 case 0x0:
677 pr_cont("Hardware Assertion");
678 break;
679
680 case 0x1:
681 pr_cont("Free List");
682 break;
683
684 case 0x2:
685 pr_cont("Physical Register File");
686 break;
687
688 case 0x3:
689 pr_cont("Retire Queue");
690 break;
691
692 case 0x4:
693 pr_cont("Scheduler table");
694 break;
695
696 case 0x5:
697 pr_cont("Status Register File");
698 break;
699
700 default:
701 goto wrong_mc6_mce; 685 goto wrong_mc6_mce;
702 break;
703 }
704
705 pr_cont(" parity error.\n");
706 686
687 pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
707 return; 688 return;
708 689
709 wrong_mc6_mce: 690 wrong_mc6_mce:
@@ -800,7 +781,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
800 pr_cont("]: 0x%016llx\n", m->status); 781 pr_cont("]: 0x%016llx\n", m->status);
801 782
802 if (m->status & MCI_STATUS_ADDRV) 783 if (m->status & MCI_STATUS_ADDRV)
803 pr_emerg(HW_ERR "MC%d_ADDR: 0x%016llx\n", m->bank, m->addr); 784 pr_emerg(HW_ERR "MC%d Error Address: 0x%016llx\n", m->bank, m->addr);
804 785
805 if (!fam_ops) 786 if (!fam_ops)
806 goto err_code; 787 goto err_code;