diff options
Diffstat (limited to 'drivers/edac/i82443bxgx_edac.c')
-rw-r--r-- | drivers/edac/i82443bxgx_edac.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index 0f2751bf3ffe..c43214fdf2d8 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c | |||
@@ -178,7 +178,7 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) | |||
178 | { | 178 | { |
179 | struct i82443bxgx_edacmc_error_info info; | 179 | struct i82443bxgx_edacmc_error_info info; |
180 | 180 | ||
181 | debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__); | 181 | debugf1("MC%d\n", mci->mc_idx); |
182 | i82443bxgx_edacmc_get_error_info(mci, &info); | 182 | i82443bxgx_edacmc_get_error_info(mci, &info); |
183 | i82443bxgx_edacmc_process_error_info(mci, &info, 1); | 183 | i82443bxgx_edacmc_process_error_info(mci, &info, 1); |
184 | } | 184 | } |
@@ -201,13 +201,13 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, | |||
201 | dimm = csrow->channels[0]->dimm; | 201 | dimm = csrow->channels[0]->dimm; |
202 | 202 | ||
203 | pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); | 203 | pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); |
204 | debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n", | 204 | debugf1("MC%d: Row=%d DRB = %#0x\n", |
205 | mci->mc_idx, __FILE__, __func__, index, drbar); | 205 | mci->mc_idx,index, drbar); |
206 | row_high_limit = ((u32) drbar << 23); | 206 | row_high_limit = ((u32) drbar << 23); |
207 | /* find the DRAM Chip Select Base address and mask */ | 207 | /* find the DRAM Chip Select Base address and mask */ |
208 | debugf1("MC%d: %s: %s() Row=%d, " | 208 | debugf1("MC%d: Row=%d, " |
209 | "Boundary Address=%#0x, Last = %#0x\n", | 209 | "Boundary Address=%#0x, Last = %#0x\n", |
210 | mci->mc_idx, __FILE__, __func__, index, row_high_limit, | 210 | mci->mc_idx, index, row_high_limit, |
211 | row_high_limit_last); | 211 | row_high_limit_last); |
212 | 212 | ||
213 | /* 440GX goes to 2GB, represented with a DRB of 0. */ | 213 | /* 440GX goes to 2GB, represented with a DRB of 0. */ |
@@ -241,7 +241,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
241 | enum mem_type mtype; | 241 | enum mem_type mtype; |
242 | enum edac_type edac_mode; | 242 | enum edac_type edac_mode; |
243 | 243 | ||
244 | debugf0("MC: %s: %s()\n", __FILE__, __func__); | 244 | debugf0("MC: %s()\n", __FILE__); |
245 | 245 | ||
246 | /* Something is really hosed if PCI config space reads from | 246 | /* Something is really hosed if PCI config space reads from |
247 | * the MC aren't working. | 247 | * the MC aren't working. |
@@ -259,7 +259,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
259 | if (mci == NULL) | 259 | if (mci == NULL) |
260 | return -ENOMEM; | 260 | return -ENOMEM; |
261 | 261 | ||
262 | debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci); | 262 | debugf0("MC: %s(): mci = %p\n", __FILE__, mci); |
263 | mci->pdev = &pdev->dev; | 263 | mci->pdev = &pdev->dev; |
264 | mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; | 264 | mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; |
265 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | 265 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
@@ -305,8 +305,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
305 | edac_mode = EDAC_SECDED; | 305 | edac_mode = EDAC_SECDED; |
306 | break; | 306 | break; |
307 | default: | 307 | default: |
308 | debugf0("%s(): Unknown/reserved ECC state " | 308 | debugf0("Unknown/reserved ECC state " |
309 | "in NBXCFG register!\n", __func__); | 309 | "in NBXCFG register!\n"); |
310 | edac_mode = EDAC_UNKNOWN; | 310 | edac_mode = EDAC_UNKNOWN; |
311 | break; | 311 | break; |
312 | } | 312 | } |
@@ -330,7 +330,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
330 | mci->ctl_page_to_phys = NULL; | 330 | mci->ctl_page_to_phys = NULL; |
331 | 331 | ||
332 | if (edac_mc_add_mc(mci)) { | 332 | if (edac_mc_add_mc(mci)) { |
333 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | 333 | debugf3("failed edac_mc_add_mc()\n"); |
334 | goto fail; | 334 | goto fail; |
335 | } | 335 | } |
336 | 336 | ||
@@ -345,7 +345,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
345 | __func__); | 345 | __func__); |
346 | } | 346 | } |
347 | 347 | ||
348 | debugf3("MC: %s: %s(): success\n", __FILE__, __func__); | 348 | debugf3("MC: %s(): success\n", __FILE__); |
349 | return 0; | 349 | return 0; |
350 | 350 | ||
351 | fail: | 351 | fail: |
@@ -361,7 +361,7 @@ static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, | |||
361 | { | 361 | { |
362 | int rc; | 362 | int rc; |
363 | 363 | ||
364 | debugf0("MC: %s: %s()\n", __FILE__, __func__); | 364 | debugf0("MC: %s()\n", __FILE__); |
365 | 365 | ||
366 | /* don't need to call pci_enable_device() */ | 366 | /* don't need to call pci_enable_device() */ |
367 | rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); | 367 | rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); |
@@ -376,7 +376,7 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) | |||
376 | { | 376 | { |
377 | struct mem_ctl_info *mci; | 377 | struct mem_ctl_info *mci; |
378 | 378 | ||
379 | debugf0("%s: %s()\n", __FILE__, __func__); | 379 | debugf0("%s()\n", __FILE__); |
380 | 380 | ||
381 | if (i82443bxgx_pci) | 381 | if (i82443bxgx_pci) |
382 | edac_pci_release_generic_ctl(i82443bxgx_pci); | 382 | edac_pci_release_generic_ctl(i82443bxgx_pci); |