diff options
Diffstat (limited to 'drivers/edac/i82443bxgx_edac.c')
-rw-r--r-- | drivers/edac/i82443bxgx_edac.c | 35 |
1 files changed, 16 insertions, 19 deletions
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index c43214fdf2d8..475bde1c4508 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c | |||
@@ -178,7 +178,7 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) | |||
178 | { | 178 | { |
179 | struct i82443bxgx_edacmc_error_info info; | 179 | struct i82443bxgx_edacmc_error_info info; |
180 | 180 | ||
181 | debugf1("MC%d\n", mci->mc_idx); | 181 | edac_dbg(1, "MC%d\n", mci->mc_idx); |
182 | i82443bxgx_edacmc_get_error_info(mci, &info); | 182 | i82443bxgx_edacmc_get_error_info(mci, &info); |
183 | i82443bxgx_edacmc_process_error_info(mci, &info, 1); | 183 | i82443bxgx_edacmc_process_error_info(mci, &info, 1); |
184 | } | 184 | } |
@@ -201,14 +201,13 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, | |||
201 | dimm = csrow->channels[0]->dimm; | 201 | dimm = csrow->channels[0]->dimm; |
202 | 202 | ||
203 | pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); | 203 | pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); |
204 | debugf1("MC%d: Row=%d DRB = %#0x\n", | 204 | edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n", |
205 | mci->mc_idx,index, drbar); | 205 | mci->mc_idx, index, drbar); |
206 | row_high_limit = ((u32) drbar << 23); | 206 | row_high_limit = ((u32) drbar << 23); |
207 | /* find the DRAM Chip Select Base address and mask */ | 207 | /* find the DRAM Chip Select Base address and mask */ |
208 | debugf1("MC%d: Row=%d, " | 208 | edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n", |
209 | "Boundary Address=%#0x, Last = %#0x\n", | 209 | mci->mc_idx, index, row_high_limit, |
210 | mci->mc_idx, index, row_high_limit, | 210 | row_high_limit_last); |
211 | row_high_limit_last); | ||
212 | 211 | ||
213 | /* 440GX goes to 2GB, represented with a DRB of 0. */ | 212 | /* 440GX goes to 2GB, represented with a DRB of 0. */ |
214 | if (row_high_limit_last && !row_high_limit) | 213 | if (row_high_limit_last && !row_high_limit) |
@@ -241,7 +240,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
241 | enum mem_type mtype; | 240 | enum mem_type mtype; |
242 | enum edac_type edac_mode; | 241 | enum edac_type edac_mode; |
243 | 242 | ||
244 | debugf0("MC: %s()\n", __FILE__); | 243 | edac_dbg(0, "MC:\n"); |
245 | 244 | ||
246 | /* Something is really hosed if PCI config space reads from | 245 | /* Something is really hosed if PCI config space reads from |
247 | * the MC aren't working. | 246 | * the MC aren't working. |
@@ -259,7 +258,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
259 | if (mci == NULL) | 258 | if (mci == NULL) |
260 | return -ENOMEM; | 259 | return -ENOMEM; |
261 | 260 | ||
262 | debugf0("MC: %s(): mci = %p\n", __FILE__, mci); | 261 | edac_dbg(0, "MC: mci = %p\n", mci); |
263 | mci->pdev = &pdev->dev; | 262 | mci->pdev = &pdev->dev; |
264 | mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; | 263 | mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; |
265 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | 264 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
@@ -275,8 +274,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
275 | mtype = MEM_RDR; | 274 | mtype = MEM_RDR; |
276 | break; | 275 | break; |
277 | default: | 276 | default: |
278 | debugf0("Unknown/reserved DRAM type value " | 277 | edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n"); |
279 | "in DRAMC register!\n"); | ||
280 | mtype = -MEM_UNKNOWN; | 278 | mtype = -MEM_UNKNOWN; |
281 | } | 279 | } |
282 | 280 | ||
@@ -305,8 +303,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
305 | edac_mode = EDAC_SECDED; | 303 | edac_mode = EDAC_SECDED; |
306 | break; | 304 | break; |
307 | default: | 305 | default: |
308 | debugf0("Unknown/reserved ECC state " | 306 | edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n"); |
309 | "in NBXCFG register!\n"); | ||
310 | edac_mode = EDAC_UNKNOWN; | 307 | edac_mode = EDAC_UNKNOWN; |
311 | break; | 308 | break; |
312 | } | 309 | } |
@@ -330,7 +327,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
330 | mci->ctl_page_to_phys = NULL; | 327 | mci->ctl_page_to_phys = NULL; |
331 | 328 | ||
332 | if (edac_mc_add_mc(mci)) { | 329 | if (edac_mc_add_mc(mci)) { |
333 | debugf3("failed edac_mc_add_mc()\n"); | 330 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
334 | goto fail; | 331 | goto fail; |
335 | } | 332 | } |
336 | 333 | ||
@@ -345,7 +342,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) | |||
345 | __func__); | 342 | __func__); |
346 | } | 343 | } |
347 | 344 | ||
348 | debugf3("MC: %s(): success\n", __FILE__); | 345 | edac_dbg(3, "MC: success\n"); |
349 | return 0; | 346 | return 0; |
350 | 347 | ||
351 | fail: | 348 | fail: |
@@ -361,7 +358,7 @@ static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, | |||
361 | { | 358 | { |
362 | int rc; | 359 | int rc; |
363 | 360 | ||
364 | debugf0("MC: %s()\n", __FILE__); | 361 | edac_dbg(0, "MC:\n"); |
365 | 362 | ||
366 | /* don't need to call pci_enable_device() */ | 363 | /* don't need to call pci_enable_device() */ |
367 | rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); | 364 | rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); |
@@ -376,7 +373,7 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) | |||
376 | { | 373 | { |
377 | struct mem_ctl_info *mci; | 374 | struct mem_ctl_info *mci; |
378 | 375 | ||
379 | debugf0("%s()\n", __FILE__); | 376 | edac_dbg(0, "\n"); |
380 | 377 | ||
381 | if (i82443bxgx_pci) | 378 | if (i82443bxgx_pci) |
382 | edac_pci_release_generic_ctl(i82443bxgx_pci); | 379 | edac_pci_release_generic_ctl(i82443bxgx_pci); |
@@ -428,7 +425,7 @@ static int __init i82443bxgx_edacmc_init(void) | |||
428 | id = &i82443bxgx_pci_tbl[i]; | 425 | id = &i82443bxgx_pci_tbl[i]; |
429 | } | 426 | } |
430 | if (!mci_pdev) { | 427 | if (!mci_pdev) { |
431 | debugf0("i82443bxgx pci_get_device fail\n"); | 428 | edac_dbg(0, "i82443bxgx pci_get_device fail\n"); |
432 | pci_rc = -ENODEV; | 429 | pci_rc = -ENODEV; |
433 | goto fail1; | 430 | goto fail1; |
434 | } | 431 | } |
@@ -436,7 +433,7 @@ static int __init i82443bxgx_edacmc_init(void) | |||
436 | pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); | 433 | pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); |
437 | 434 | ||
438 | if (pci_rc < 0) { | 435 | if (pci_rc < 0) { |
439 | debugf0("i82443bxgx init fail\n"); | 436 | edac_dbg(0, "i82443bxgx init fail\n"); |
440 | pci_rc = -ENODEV; | 437 | pci_rc = -ENODEV; |
441 | goto fail1; | 438 | goto fail1; |
442 | } | 439 | } |