diff options
Diffstat (limited to 'drivers/edac/amd76x_edac.c')
-rw-r--r-- | drivers/edac/amd76x_edac.c | 54 |
1 files changed, 25 insertions, 29 deletions
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c index 40c763231ecc..eaa225192098 100644 --- a/drivers/edac/amd76x_edac.c +++ b/drivers/edac/amd76x_edac.c | |||
@@ -86,11 +86,9 @@ struct amd76x_dev_info { | |||
86 | 86 | ||
87 | static const struct amd76x_dev_info amd76x_devs[] = { | 87 | static const struct amd76x_dev_info amd76x_devs[] = { |
88 | [AMD761] = { | 88 | [AMD761] = { |
89 | .ctl_name = "AMD761" | 89 | .ctl_name = "AMD761"}, |
90 | }, | ||
91 | [AMD762] = { | 90 | [AMD762] = { |
92 | .ctl_name = "AMD762" | 91 | .ctl_name = "AMD762"}, |
93 | }, | ||
94 | }; | 92 | }; |
95 | 93 | ||
96 | /** | 94 | /** |
@@ -102,21 +100,21 @@ static const struct amd76x_dev_info amd76x_devs[] = { | |||
102 | * on the chip so that further errors will be reported | 100 | * on the chip so that further errors will be reported |
103 | */ | 101 | */ |
104 | static void amd76x_get_error_info(struct mem_ctl_info *mci, | 102 | static void amd76x_get_error_info(struct mem_ctl_info *mci, |
105 | struct amd76x_error_info *info) | 103 | struct amd76x_error_info *info) |
106 | { | 104 | { |
107 | struct pci_dev *pdev; | 105 | struct pci_dev *pdev; |
108 | 106 | ||
109 | pdev = to_pci_dev(mci->dev); | 107 | pdev = to_pci_dev(mci->dev); |
110 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, | 108 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, |
111 | &info->ecc_mode_status); | 109 | &info->ecc_mode_status); |
112 | 110 | ||
113 | if (info->ecc_mode_status & BIT(8)) | 111 | if (info->ecc_mode_status & BIT(8)) |
114 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, | 112 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
115 | (u32) BIT(8), (u32) BIT(8)); | 113 | (u32) BIT(8), (u32) BIT(8)); |
116 | 114 | ||
117 | if (info->ecc_mode_status & BIT(9)) | 115 | if (info->ecc_mode_status & BIT(9)) |
118 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, | 116 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
119 | (u32) BIT(9), (u32) BIT(9)); | 117 | (u32) BIT(9), (u32) BIT(9)); |
120 | } | 118 | } |
121 | 119 | ||
122 | /** | 120 | /** |
@@ -130,7 +128,8 @@ static void amd76x_get_error_info(struct mem_ctl_info *mci, | |||
130 | * then attempt to handle and clean up after the error | 128 | * then attempt to handle and clean up after the error |
131 | */ | 129 | */ |
132 | static int amd76x_process_error_info(struct mem_ctl_info *mci, | 130 | static int amd76x_process_error_info(struct mem_ctl_info *mci, |
133 | struct amd76x_error_info *info, int handle_errors) | 131 | struct amd76x_error_info *info, |
132 | int handle_errors) | ||
134 | { | 133 | { |
135 | int error_found; | 134 | int error_found; |
136 | u32 row; | 135 | u32 row; |
@@ -138,7 +137,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci, | |||
138 | error_found = 0; | 137 | error_found = 0; |
139 | 138 | ||
140 | /* | 139 | /* |
141 | * Check for an uncorrectable error | 140 | * Check for an uncorrectable error |
142 | */ | 141 | */ |
143 | if (info->ecc_mode_status & BIT(8)) { | 142 | if (info->ecc_mode_status & BIT(8)) { |
144 | error_found = 1; | 143 | error_found = 1; |
@@ -146,12 +145,12 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci, | |||
146 | if (handle_errors) { | 145 | if (handle_errors) { |
147 | row = (info->ecc_mode_status >> 4) & 0xf; | 146 | row = (info->ecc_mode_status >> 4) & 0xf; |
148 | edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, | 147 | edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, |
149 | row, mci->ctl_name); | 148 | row, mci->ctl_name); |
150 | } | 149 | } |
151 | } | 150 | } |
152 | 151 | ||
153 | /* | 152 | /* |
154 | * Check for a correctable error | 153 | * Check for a correctable error |
155 | */ | 154 | */ |
156 | if (info->ecc_mode_status & BIT(9)) { | 155 | if (info->ecc_mode_status & BIT(9)) { |
157 | error_found = 1; | 156 | error_found = 1; |
@@ -159,7 +158,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci, | |||
159 | if (handle_errors) { | 158 | if (handle_errors) { |
160 | row = info->ecc_mode_status & 0xf; | 159 | row = info->ecc_mode_status & 0xf; |
161 | edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, | 160 | edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, |
162 | 0, row, 0, mci->ctl_name); | 161 | 0, row, 0, mci->ctl_name); |
163 | } | 162 | } |
164 | } | 163 | } |
165 | 164 | ||
@@ -182,7 +181,7 @@ static void amd76x_check(struct mem_ctl_info *mci) | |||
182 | } | 181 | } |
183 | 182 | ||
184 | static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | 183 | static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
185 | enum edac_type edac_mode) | 184 | enum edac_type edac_mode) |
186 | { | 185 | { |
187 | struct csrow_info *csrow; | 186 | struct csrow_info *csrow; |
188 | u32 mba, mba_base, mba_mask, dms; | 187 | u32 mba, mba_base, mba_mask, dms; |
@@ -193,8 +192,7 @@ static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |||
193 | 192 | ||
194 | /* find the DRAM Chip Select Base address and mask */ | 193 | /* find the DRAM Chip Select Base address and mask */ |
195 | pci_read_config_dword(pdev, | 194 | pci_read_config_dword(pdev, |
196 | AMD76X_MEM_BASE_ADDR + (index * 4), | 195 | AMD76X_MEM_BASE_ADDR + (index * 4), &mba); |
197 | &mba); | ||
198 | 196 | ||
199 | if (!(mba & BIT(0))) | 197 | if (!(mba & BIT(0))) |
200 | continue; | 198 | continue; |
@@ -249,7 +247,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
249 | mci->mtype_cap = MEM_FLAG_RDDR; | 247 | mci->mtype_cap = MEM_FLAG_RDDR; |
250 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | 248 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
251 | mci->edac_cap = ems_mode ? | 249 | mci->edac_cap = ems_mode ? |
252 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; | 250 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; |
253 | mci->mod_name = EDAC_MOD_STR; | 251 | mci->mod_name = EDAC_MOD_STR; |
254 | mci->mod_ver = AMD76X_REVISION; | 252 | mci->mod_ver = AMD76X_REVISION; |
255 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; | 253 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; |
@@ -258,12 +256,12 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
258 | mci->ctl_page_to_phys = NULL; | 256 | mci->ctl_page_to_phys = NULL; |
259 | 257 | ||
260 | amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]); | 258 | amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]); |
261 | amd76x_get_error_info(mci, &discard); /* clear counters */ | 259 | amd76x_get_error_info(mci, &discard); /* clear counters */ |
262 | 260 | ||
263 | /* Here we assume that we will never see multiple instances of this | 261 | /* Here we assume that we will never see multiple instances of this |
264 | * type of memory controller. The ID is therefore hardcoded to 0. | 262 | * type of memory controller. The ID is therefore hardcoded to 0. |
265 | */ | 263 | */ |
266 | if (edac_mc_add_mc(mci,0)) { | 264 | if (edac_mc_add_mc(mci, 0)) { |
267 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | 265 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
268 | goto fail; | 266 | goto fail; |
269 | } | 267 | } |
@@ -272,14 +270,14 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
272 | debugf3("%s(): success\n", __func__); | 270 | debugf3("%s(): success\n", __func__); |
273 | return 0; | 271 | return 0; |
274 | 272 | ||
275 | fail: | 273 | fail: |
276 | edac_mc_free(mci); | 274 | edac_mc_free(mci); |
277 | return -ENODEV; | 275 | return -ENODEV; |
278 | } | 276 | } |
279 | 277 | ||
280 | /* returns count (>= 0), or negative on error */ | 278 | /* returns count (>= 0), or negative on error */ |
281 | static int __devinit amd76x_init_one(struct pci_dev *pdev, | 279 | static int __devinit amd76x_init_one(struct pci_dev *pdev, |
282 | const struct pci_device_id *ent) | 280 | const struct pci_device_id *ent) |
283 | { | 281 | { |
284 | debugf0("%s()\n", __func__); | 282 | debugf0("%s()\n", __func__); |
285 | 283 | ||
@@ -309,16 +307,14 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev) | |||
309 | 307 | ||
310 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { | 308 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { |
311 | { | 309 | { |
312 | PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 310 | PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
313 | AMD762 | 311 | AMD762}, |
314 | }, | ||
315 | { | 312 | { |
316 | PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 313 | PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
317 | AMD761 | 314 | AMD761}, |
318 | }, | ||
319 | { | 315 | { |
320 | 0, | 316 | 0, |
321 | } /* 0 terminated list. */ | 317 | } /* 0 terminated list. */ |
322 | }; | 318 | }; |
323 | 319 | ||
324 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); | 320 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); |