1 files changed, 56 insertions, 4 deletions

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 2c6f113bae2b..d2443cfa0698 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -170,6 +170,8 @@
 /*
  * PCI-defined configuration space registers
  */
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
 #define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
 #define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
 #define PCI_DEVICE_ID_AMD_16H_NB_F1     0x1531
@@ -181,13 +183,22 @@
 #define DRAM_BASE_LO                    0x40
 #define DRAM_LIMIT_LO                   0x44
 
-#define dram_intlv_en(pvt, i)           ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
+/*
+ * F15 M30h D18F1x2[1C:00]
+ */
+#define DRAM_CONT_BASE                  0x200
+#define DRAM_CONT_LIMIT                 0x204
+
+/*
+ * F15 M30h D18F1x2[4C:40]
+ */
+#define DRAM_CONT_HIGH_OFF              0x240
+
 #define dram_rw(pvt, i)                 ((u8)(pvt->ranges[i].base.lo & 0x3))
 #define dram_intlv_sel(pvt, i)          ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
 #define dram_dst_node(pvt, i)           ((u8)(pvt->ranges[i].lim.lo & 0x7))
 
 #define DHAR                            0xf0
-#define dhar_valid(pvt)                 ((pvt)->dhar & BIT(0))
 #define dhar_mem_hoist_valid(pvt)       ((pvt)->dhar & BIT(1))
 #define dhar_base(pvt)                  ((pvt)->dhar & 0xff000000)
 #define k8_dhar_offset(pvt)             (((pvt)->dhar & 0x0000ff00) << 16)
@@ -234,8 +245,6 @@
 #define DDR3_MODE                       BIT(8)
 
 #define DCT_SEL_LO                      0x110
-#define dct_sel_baseaddr(pvt)           ((pvt)->dct_sel_lo & 0xFFFFF800)
-#define dct_sel_interleave_addr(pvt)    (((pvt)->dct_sel_lo >> 6) & 0x3)
 #define dct_high_range_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(0))
 #define dct_interleave_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(2))
 
@@ -297,6 +306,7 @@ enum amd_families {
         K8_CPUS = 0,
         F10_CPUS,
         F15_CPUS,
+        F15_M30H_CPUS,
         F16_CPUS,
         NUM_FAMILIES,
 };
@@ -337,6 +347,10 @@ struct amd64_pvt {
         struct pci_dev *F1, *F2, *F3;
 
         u16 mc_node_id;         /* MC index of this MC node */
+        u8 fam;                 /* CPU family */
+        u8 model;               /* ... model */
+        u8 stepping;            /* ... stepping */
+
         int ext_model;          /* extended model value of this node */
         int channel_count;
 
@@ -414,6 +428,14 @@ static inline u16 extract_syndrome(u64 status)
         return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
 }
 
+static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
+{
+        if (pvt->fam == 0x15 && pvt->model >= 0x30)
+                return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
+                        ((pvt->dct_sel_lo >> 6) & 0x3);
+
+        return  ((pvt)->dct_sel_lo >> 6) & 0x3;
+}
 /*
  * per-node ECC settings descriptor
  */
@@ -504,3 +526,33 @@ static inline void enable_caches(void *dummy)
 {
         write_cr0(read_cr0() & ~X86_CR0_CD);
 }
+
+static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
+{
+        if (pvt->fam == 0x15 && pvt->model >= 0x30) {
+                u32 tmp;
+                amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
+                return (u8) tmp & 0xF;
+        }
+        return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
+}
+
+static inline u8 dhar_valid(struct amd64_pvt *pvt)
+{
+        if (pvt->fam == 0x15 && pvt->model >= 0x30) {
+                u32 tmp;
+                amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
+                return (tmp >> 1) & BIT(0);
+        }
+        return (pvt)->dhar & BIT(0);
+}
+
+static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
+{
+        if (pvt->fam == 0x15 && pvt->model >= 0x30) {
+                u32 tmp;
+                amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
+                return (tmp >> 11) & 0x1FFF;
+        }
+        return (pvt)->dct_sel_lo & 0xFFFFF800;
+}