diff options
Diffstat (limited to 'drivers/edac/amd64_edac.h')
| -rw-r--r-- | drivers/edac/amd64_edac.h | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 8ea07e2715dc..c6f359a85207 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h | |||
| @@ -132,6 +132,8 @@ | |||
| 132 | #define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__ | 132 | #define EDAC_AMD64_VERSION " Ver: 3.2.0 " __DATE__ |
| 133 | #define EDAC_MOD_STR "amd64_edac" | 133 | #define EDAC_MOD_STR "amd64_edac" |
| 134 | 134 | ||
| 135 | #define EDAC_MAX_NUMNODES 8 | ||
| 136 | |||
| 135 | /* Extended Model from CPUID, for CPU Revision numbers */ | 137 | /* Extended Model from CPUID, for CPU Revision numbers */ |
| 136 | #define OPTERON_CPU_LE_REV_C 0 | 138 | #define OPTERON_CPU_LE_REV_C 0 |
| 137 | #define OPTERON_CPU_REV_D 1 | 139 | #define OPTERON_CPU_REV_D 1 |
| @@ -142,7 +144,7 @@ | |||
| 142 | #define OPTERON_CPU_REV_FA 5 | 144 | #define OPTERON_CPU_REV_FA 5 |
| 143 | 145 | ||
| 144 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | 146 | /* Hardware limit on ChipSelect rows per MC and processors per system */ |
| 145 | #define CHIPSELECT_COUNT 8 | 147 | #define MAX_CS_COUNT 8 |
| 146 | #define DRAM_REG_COUNT 8 | 148 | #define DRAM_REG_COUNT 8 |
| 147 | 149 | ||
| 148 | 150 | ||
| @@ -193,7 +195,6 @@ | |||
| 193 | */ | 195 | */ |
| 194 | #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL) | 196 | #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL) |
| 195 | #define REV_E_DCS_SHIFT 4 | 197 | #define REV_E_DCS_SHIFT 4 |
| 196 | #define REV_E_DCSM_COUNT 8 | ||
| 197 | 198 | ||
| 198 | #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL) | 199 | #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL) |
| 199 | #define REV_F_F1Xh_DCS_SHIFT 8 | 200 | #define REV_F_F1Xh_DCS_SHIFT 8 |
| @@ -204,9 +205,6 @@ | |||
| 204 | */ | 205 | */ |
| 205 | #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL) | 206 | #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL) |
| 206 | #define REV_F_DCS_SHIFT 8 | 207 | #define REV_F_DCS_SHIFT 8 |
| 207 | #define REV_F_DCSM_COUNT 4 | ||
| 208 | #define F10_DCSM_COUNT 4 | ||
| 209 | #define F11_DCSM_COUNT 2 | ||
| 210 | 208 | ||
| 211 | /* DRAM CS Mask Registers */ | 209 | /* DRAM CS Mask Registers */ |
| 212 | #define K8_DCSM0 0x60 | 210 | #define K8_DCSM0 0x60 |
| @@ -374,13 +372,11 @@ enum { | |||
| 374 | 372 | ||
| 375 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | 373 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ |
| 376 | (BIT(((word) & 0xF) + 20) | \ | 374 | (BIT(((word) & 0xF) + 20) | \ |
| 377 | BIT(17) | \ | 375 | BIT(17) | bits) |
| 378 | ((bits) & 0xF)) | ||
| 379 | 376 | ||
| 380 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | 377 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ |
| 381 | (BIT(((word) & 0xF) + 20) | \ | 378 | (BIT(((word) & 0xF) + 20) | \ |
| 382 | BIT(16) | \ | 379 | BIT(16) | bits) |
| 383 | ((bits) & 0xF)) | ||
| 384 | 380 | ||
| 385 | #define K8_NBCAP 0xE8 | 381 | #define K8_NBCAP 0xE8 |
| 386 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | 382 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) |
| @@ -445,12 +441,12 @@ struct amd64_pvt { | |||
| 445 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | 441 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ |
| 446 | 442 | ||
| 447 | /* DRAM CS Base Address Registers F2x[1,0][5C:40] */ | 443 | /* DRAM CS Base Address Registers F2x[1,0][5C:40] */ |
| 448 | u32 dcsb0[CHIPSELECT_COUNT]; | 444 | u32 dcsb0[MAX_CS_COUNT]; |
| 449 | u32 dcsb1[CHIPSELECT_COUNT]; | 445 | u32 dcsb1[MAX_CS_COUNT]; |
| 450 | 446 | ||
| 451 | /* DRAM CS Mask Registers F2x[1,0][6C:60] */ | 447 | /* DRAM CS Mask Registers F2x[1,0][6C:60] */ |
| 452 | u32 dcsm0[CHIPSELECT_COUNT]; | 448 | u32 dcsm0[MAX_CS_COUNT]; |
| 453 | u32 dcsm1[CHIPSELECT_COUNT]; | 449 | u32 dcsm1[MAX_CS_COUNT]; |
| 454 | 450 | ||
| 455 | /* | 451 | /* |
| 456 | * Decoded parts of DRAM BASE and LIMIT Registers | 452 | * Decoded parts of DRAM BASE and LIMIT Registers |
| @@ -470,6 +466,7 @@ struct amd64_pvt { | |||
| 470 | */ | 466 | */ |
| 471 | u32 dcsb_base; /* DCSB base bits */ | 467 | u32 dcsb_base; /* DCSB base bits */ |
| 472 | u32 dcsm_mask; /* DCSM mask bits */ | 468 | u32 dcsm_mask; /* DCSM mask bits */ |
| 469 | u32 cs_count; /* num chip selects (== num DCSB registers) */ | ||
| 473 | u32 num_dcsm; /* Number of DCSM registers */ | 470 | u32 num_dcsm; /* Number of DCSM registers */ |
| 474 | u32 dcs_mask_notused; /* DCSM notused mask bits */ | 471 | u32 dcs_mask_notused; /* DCSM notused mask bits */ |
| 475 | u32 dcs_shift; /* DCSB and DCSM shift value */ | 472 | u32 dcs_shift; /* DCSB and DCSM shift value */ |