aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/edac/amd64_edac.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 079f5b8dd5c2..495b4d506671 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1148,11 +1148,11 @@ static u64 f10_get_error_address(struct mem_ctl_info *mci,
1148static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) 1148static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
1149{ 1149{
1150 1150
1151 if (!amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_LOW, &pvt->dct_sel_low)) { 1151 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1152 debugf0("F2x110 (DCTL Sel. Low): 0x%08x, High range addrs at: 0x%x\n", 1152 debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
1153 pvt->dct_sel_low, dct_sel_baseaddr(pvt)); 1153 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1154 1154
1155 debugf0(" DCT mode: %s, All DCTs on: %s\n", 1155 debugf0(" mode: %s, All DCTs on: %s\n",
1156 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), 1156 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
1157 (dct_dram_enabled(pvt) ? "yes" : "no")); 1157 (dct_dram_enabled(pvt) ? "yes" : "no"));
1158 1158
@@ -1160,18 +1160,18 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
1160 debugf0(" Address range split per DCT: %s\n", 1160 debugf0(" Address range split per DCT: %s\n",
1161 (dct_high_range_enabled(pvt) ? "yes" : "no")); 1161 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1162 1162
1163 debugf0(" DCT data interleave for ECC: %s, " 1163 debugf0(" data interleave for ECC: %s, "
1164 "DRAM cleared since last warm reset: %s\n", 1164 "DRAM cleared since last warm reset: %s\n",
1165 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), 1165 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
1166 (dct_memory_cleared(pvt) ? "yes" : "no")); 1166 (dct_memory_cleared(pvt) ? "yes" : "no"));
1167 1167
1168 debugf0(" DCT channel interleave: %s, " 1168 debugf0(" channel interleave: %s, "
1169 "DCT interleave bits selector: 0x%x\n", 1169 "interleave bits selector: 0x%x\n",
1170 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), 1170 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
1171 dct_sel_interleave_addr(pvt)); 1171 dct_sel_interleave_addr(pvt));
1172 } 1172 }
1173 1173
1174 amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_HIGH, &pvt->dct_sel_hi); 1174 amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
1175} 1175}
1176 1176
1177/* 1177/*
@@ -1181,7 +1181,7 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
1181static u8 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, 1181static u8 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1182 bool hi_range_sel, u8 intlv_en) 1182 bool hi_range_sel, u8 intlv_en)
1183{ 1183{
1184 u32 dct_sel_high = (pvt->dct_sel_low >> 1) & 1; 1184 u32 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1185 1185
1186 if (dct_ganging_enabled(pvt)) 1186 if (dct_ganging_enabled(pvt))
1187 return 0; 1187 return 0;
@@ -1955,7 +1955,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
1955 amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0); 1955 amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
1956 amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0); 1956 amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
1957 1957
1958 if (!dct_ganging_enabled(pvt) && boot_cpu_data.x86 > 0xf) { 1958 if (!dct_ganging_enabled(pvt)) {
1959 amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1); 1959 amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
1960 amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1); 1960 amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
1961 } 1961 }