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path: root/drivers/dma/sh/shdmac.c
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Diffstat (limited to 'drivers/dma/sh/shdmac.c')
-rw-r--r--drivers/dma/sh/shdmac.c15
1 files changed, 7 insertions, 8 deletions
diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 146d5df926db..58eb85770eba 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -38,12 +38,12 @@
38#include "../dmaengine.h" 38#include "../dmaengine.h"
39#include "shdma.h" 39#include "shdma.h"
40 40
41/* DMA register */ 41/* DMA registers */
42#define SAR 0x00 42#define SAR 0x00 /* Source Address Register */
43#define DAR 0x04 43#define DAR 0x04 /* Destination Address Register */
44#define TCR 0x08 44#define TCR 0x08 /* Transfer Count Register */
45#define CHCR 0x0C 45#define CHCR 0x0C /* Channel Control Register */
46#define DMAOR 0x40 46#define DMAOR 0x40 /* DMA Operation Register */
47 47
48#define TEND 0x18 /* USB-DMAC */ 48#define TEND 0x18 /* USB-DMAC */
49 49
@@ -239,9 +239,8 @@ static void dmae_init(struct sh_dmae_chan *sh_chan)
239{ 239{
240 /* 240 /*
241 * Default configuration for dual address memory-memory transfer. 241 * Default configuration for dual address memory-memory transfer.
242 * 0x400 represents auto-request.
243 */ 242 */
244 u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, 243 u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
245 LOG2_DEFAULT_XFER_SIZE); 244 LOG2_DEFAULT_XFER_SIZE);
246 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); 245 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
247 chcr_write(sh_chan, chcr); 246 chcr_write(sh_chan, chcr);