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Diffstat (limited to 'drivers/dma/fsldma.c')
-rw-r--r--drivers/dma/fsldma.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 88f470f0d820..0e376eb37417 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1313,7 +1313,7 @@ static int __devinit fsldma_of_probe(struct of_device *op,
1313 INIT_LIST_HEAD(&fdev->common.channels); 1313 INIT_LIST_HEAD(&fdev->common.channels);
1314 1314
1315 /* ioremap the registers for use */ 1315 /* ioremap the registers for use */
1316 fdev->regs = of_iomap(op->node, 0); 1316 fdev->regs = of_iomap(op->dev.of_node, 0);
1317 if (!fdev->regs) { 1317 if (!fdev->regs) {
1318 dev_err(&op->dev, "unable to ioremap registers\n"); 1318 dev_err(&op->dev, "unable to ioremap registers\n");
1319 err = -ENOMEM; 1319 err = -ENOMEM;
@@ -1321,7 +1321,7 @@ static int __devinit fsldma_of_probe(struct of_device *op,
1321 } 1321 }
1322 1322
1323 /* map the channel IRQ if it exists, but don't hookup the handler yet */ 1323 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1324 fdev->irq = irq_of_parse_and_map(op->node, 0); 1324 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1325 1325
1326 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1326 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1327 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1327 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
@@ -1343,7 +1343,7 @@ static int __devinit fsldma_of_probe(struct of_device *op,
1343 * of_platform_bus_remove(). Instead, we manually instantiate every DMA 1343 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1344 * channel object. 1344 * channel object.
1345 */ 1345 */
1346 for_each_child_of_node(op->node, child) { 1346 for_each_child_of_node(op->dev.of_node, child) {
1347 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { 1347 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1348 fsl_dma_chan_probe(fdev, child, 1348 fsl_dma_chan_probe(fdev, child,
1349 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 1349 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,