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Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
-rw-r--r--drivers/dma/dw_dmac_regs.h18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index ff39fa6cd2bc..88965597b7d0 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -98,9 +98,17 @@ struct dw_dma_regs {
98 u32 DW_PARAMS; 98 u32 DW_PARAMS;
99}; 99};
100 100
101#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
102#define dma_readl_native ioread32be
103#define dma_writel_native iowrite32be
104#else
105#define dma_readl_native readl
106#define dma_writel_native writel
107#endif
108
101/* To access the registers in early stage of probe */ 109/* To access the registers in early stage of probe */
102#define dma_read_byaddr(addr, name) \ 110#define dma_read_byaddr(addr, name) \
103 readl((addr) + offsetof(struct dw_dma_regs, name)) 111 dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
104 112
105/* Bitfields in DW_PARAMS */ 113/* Bitfields in DW_PARAMS */
106#define DW_PARAMS_NR_CHAN 8 /* number of channels */ 114#define DW_PARAMS_NR_CHAN 8 /* number of channels */
@@ -216,9 +224,9 @@ __dwc_regs(struct dw_dma_chan *dwc)
216} 224}
217 225
218#define channel_readl(dwc, name) \ 226#define channel_readl(dwc, name) \
219 readl(&(__dwc_regs(dwc)->name)) 227 dma_readl_native(&(__dwc_regs(dwc)->name))
220#define channel_writel(dwc, name, val) \ 228#define channel_writel(dwc, name, val) \
221 writel((val), &(__dwc_regs(dwc)->name)) 229 dma_writel_native((val), &(__dwc_regs(dwc)->name))
222 230
223static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 231static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
224{ 232{
@@ -246,9 +254,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
246} 254}
247 255
248#define dma_readl(dw, name) \ 256#define dma_readl(dw, name) \
249 readl(&(__dw_regs(dw)->name)) 257 dma_readl_native(&(__dw_regs(dw)->name))
250#define dma_writel(dw, name, val) \ 258#define dma_writel(dw, name, val) \
251 writel((val), &(__dw_regs(dw)->name)) 259 dma_writel_native((val), &(__dw_regs(dw)->name))
252 260
253#define channel_set_bit(dw, reg, mask) \ 261#define channel_set_bit(dw, reg, mask) \
254 dma_writel(dw, reg, ((mask) << 8) | (mask)) 262 dma_writel(dw, reg, ((mask) << 8) | (mask))