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path: root/drivers/dma/dw_dmac_regs.h
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Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
-rw-r--r--drivers/dma/dw_dmac_regs.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index d9a939f67f46..720f821527f8 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -86,6 +86,7 @@ struct dw_dma_regs {
86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ 87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ 88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
89#define DWC_CTLL_FC(n) ((n) << 20)
89#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ 90#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
90#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 91#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
91#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 92#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
@@ -101,6 +102,8 @@ struct dw_dma_regs {
101#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff 102#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
102 103
103/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ 104/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
105#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
106#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
104#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ 107#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
105#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ 108#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
106#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ 109#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
@@ -134,6 +137,7 @@ struct dw_dma_chan {
134 struct dma_chan chan; 137 struct dma_chan chan;
135 void __iomem *ch_regs; 138 void __iomem *ch_regs;
136 u8 mask; 139 u8 mask;
140 u8 priority;
137 141
138 spinlock_t lock; 142 spinlock_t lock;
139 143
@@ -155,9 +159,9 @@ __dwc_regs(struct dw_dma_chan *dwc)
155} 159}
156 160
157#define channel_readl(dwc, name) \ 161#define channel_readl(dwc, name) \
158 __raw_readl(&(__dwc_regs(dwc)->name)) 162 readl(&(__dwc_regs(dwc)->name))
159#define channel_writel(dwc, name, val) \ 163#define channel_writel(dwc, name, val) \
160 __raw_writel((val), &(__dwc_regs(dwc)->name)) 164 writel((val), &(__dwc_regs(dwc)->name))
161 165
162static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 166static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
163{ 167{
@@ -181,9 +185,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
181} 185}
182 186
183#define dma_readl(dw, name) \ 187#define dma_readl(dw, name) \
184 __raw_readl(&(__dw_regs(dw)->name)) 188 readl(&(__dw_regs(dw)->name))
185#define dma_writel(dw, name, val) \ 189#define dma_writel(dw, name, val) \
186 __raw_writel((val), &(__dw_regs(dw)->name)) 190 writel((val), &(__dw_regs(dw)->name))
187 191
188#define channel_set_bit(dw, reg, mask) \ 192#define channel_set_bit(dw, reg, mask) \
189 dma_writel(dw, reg, ((mask) << 8) | (mask)) 193 dma_writel(dw, reg, ((mask) << 8) | (mask))