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path: root/drivers/dma/dw_dmac.c
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Diffstat (limited to 'drivers/dma/dw_dmac.c')
-rw-r--r--drivers/dma/dw_dmac.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 9bfd6d360718..decca1c3c83d 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -696,7 +696,7 @@ err_desc_get:
696 696
697static struct dma_async_tx_descriptor * 697static struct dma_async_tx_descriptor *
698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
699 unsigned int sg_len, enum dma_data_direction direction, 699 unsigned int sg_len, enum dma_transfer_direction direction,
700 unsigned long flags) 700 unsigned long flags)
701{ 701{
702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
@@ -720,7 +720,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
720 prev = first = NULL; 720 prev = first = NULL;
721 721
722 switch (direction) { 722 switch (direction) {
723 case DMA_TO_DEVICE: 723 case DMA_MEM_TO_DEV:
724 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 724 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
725 | DWC_CTLL_DST_WIDTH(reg_width) 725 | DWC_CTLL_DST_WIDTH(reg_width)
726 | DWC_CTLL_DST_FIX 726 | DWC_CTLL_DST_FIX
@@ -777,7 +777,7 @@ slave_sg_todev_fill_desc:
777 goto slave_sg_todev_fill_desc; 777 goto slave_sg_todev_fill_desc;
778 } 778 }
779 break; 779 break;
780 case DMA_FROM_DEVICE: 780 case DMA_DEV_TO_MEM:
781 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 781 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
782 | DWC_CTLL_SRC_WIDTH(reg_width) 782 | DWC_CTLL_SRC_WIDTH(reg_width)
783 | DWC_CTLL_DST_INC 783 | DWC_CTLL_DST_INC
@@ -1165,7 +1165,7 @@ EXPORT_SYMBOL(dw_dma_cyclic_stop);
1165 */ 1165 */
1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1168 enum dma_data_direction direction) 1168 enum dma_transfer_direction direction)
1169{ 1169{
1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1171 struct dw_cyclic_desc *cdesc; 1171 struct dw_cyclic_desc *cdesc;
@@ -1206,7 +1206,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1206 goto out_err; 1206 goto out_err;
1207 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1207 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1208 goto out_err; 1208 goto out_err;
1209 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 1209 if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1210 goto out_err; 1210 goto out_err;
1211 1211
1212 retval = ERR_PTR(-ENOMEM); 1212 retval = ERR_PTR(-ENOMEM);
@@ -1228,7 +1228,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1228 goto out_err_desc_get; 1228 goto out_err_desc_get;
1229 1229
1230 switch (direction) { 1230 switch (direction) {
1231 case DMA_TO_DEVICE: 1231 case DMA_MEM_TO_DEV:
1232 desc->lli.dar = dws->tx_reg; 1232 desc->lli.dar = dws->tx_reg;
1233 desc->lli.sar = buf_addr + (period_len * i); 1233 desc->lli.sar = buf_addr + (period_len * i);
1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
@@ -1239,7 +1239,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1239 | DWC_CTLL_FC(dws->fc) 1239 | DWC_CTLL_FC(dws->fc)
1240 | DWC_CTLL_INT_EN); 1240 | DWC_CTLL_INT_EN);
1241 break; 1241 break;
1242 case DMA_FROM_DEVICE: 1242 case DMA_DEV_TO_MEM:
1243 desc->lli.dar = buf_addr + (period_len * i); 1243 desc->lli.dar = buf_addr + (period_len * i);
1244 desc->lli.sar = dws->rx_reg; 1244 desc->lli.sar = dws->rx_reg;
1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)