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-rw-r--r--drivers/dma/at_hdmac.c1215
1 files changed, 1215 insertions, 0 deletions
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
new file mode 100644
index 000000000000..0aeb578a24e3
--- /dev/null
+++ b/drivers/dma/at_hdmac.c
@@ -0,0 +1,1215 @@
1/*
2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 *
12 * This supports the Atmel AHB DMA Controller,
13 *
14 * The driver has currently been tested with the Atmel AT91SAM9RL
15 * and AT91SAM9G45 series.
16 */
17
18#include <linux/clk.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/interrupt.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25
26#include "at_hdmac_regs.h"
27
28/*
29 * Glossary
30 * --------
31 *
32 * at_hdmac : Name of the ATmel AHB DMA Controller
33 * at_dma_ / atdma : ATmel DMA controller entity related
34 * atc_ / atchan : ATmel DMA Channel entity related
35 */
36
37#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
38#define ATC_DEFAULT_CTRLA (0)
39#define ATC_DEFAULT_CTRLB (ATC_SIF(0) \
40 |ATC_DIF(1))
41
42/*
43 * Initial number of descriptors to allocate for each channel. This could
44 * be increased during dma usage.
45 */
46static unsigned int init_nr_desc_per_channel = 64;
47module_param(init_nr_desc_per_channel, uint, 0644);
48MODULE_PARM_DESC(init_nr_desc_per_channel,
49 "initial descriptors per channel (default: 64)");
50
51
52/* prototypes */
53static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
54
55
56/*----------------------------------------------------------------------*/
57
58static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
59{
60 return list_first_entry(&atchan->active_list,
61 struct at_desc, desc_node);
62}
63
64static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
65{
66 return list_first_entry(&atchan->queue,
67 struct at_desc, desc_node);
68}
69
70/**
71 * atc_alloc_descriptor - allocate and return an initilized descriptor
72 * @chan: the channel to allocate descriptors for
73 * @gfp_flags: GFP allocation flags
74 *
75 * Note: The ack-bit is positioned in the descriptor flag at creation time
76 * to make initial allocation more convenient. This bit will be cleared
77 * and control will be given to client at usage time (during
78 * preparation functions).
79 */
80static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
81 gfp_t gfp_flags)
82{
83 struct at_desc *desc = NULL;
84 struct at_dma *atdma = to_at_dma(chan->device);
85 dma_addr_t phys;
86
87 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
88 if (desc) {
89 memset(desc, 0, sizeof(struct at_desc));
90 INIT_LIST_HEAD(&desc->tx_list);
91 dma_async_tx_descriptor_init(&desc->txd, chan);
92 /* txd.flags will be overwritten in prep functions */
93 desc->txd.flags = DMA_CTRL_ACK;
94 desc->txd.tx_submit = atc_tx_submit;
95 desc->txd.phys = phys;
96 }
97
98 return desc;
99}
100
101/**
102 * atc_desc_get - get a unsused descriptor from free_list
103 * @atchan: channel we want a new descriptor for
104 */
105static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
106{
107 struct at_desc *desc, *_desc;
108 struct at_desc *ret = NULL;
109 unsigned int i = 0;
110 LIST_HEAD(tmp_list);
111
112 spin_lock_bh(&atchan->lock);
113 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
114 i++;
115 if (async_tx_test_ack(&desc->txd)) {
116 list_del(&desc->desc_node);
117 ret = desc;
118 break;
119 }
120 dev_dbg(chan2dev(&atchan->chan_common),
121 "desc %p not ACKed\n", desc);
122 }
123 spin_unlock_bh(&atchan->lock);
124 dev_vdbg(chan2dev(&atchan->chan_common),
125 "scanned %u descriptors on freelist\n", i);
126
127 /* no more descriptor available in initial pool: create one more */
128 if (!ret) {
129 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
130 if (ret) {
131 spin_lock_bh(&atchan->lock);
132 atchan->descs_allocated++;
133 spin_unlock_bh(&atchan->lock);
134 } else {
135 dev_err(chan2dev(&atchan->chan_common),
136 "not enough descriptors available\n");
137 }
138 }
139
140 return ret;
141}
142
143/**
144 * atc_desc_put - move a descriptor, including any children, to the free list
145 * @atchan: channel we work on
146 * @desc: descriptor, at the head of a chain, to move to free list
147 */
148static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
149{
150 if (desc) {
151 struct at_desc *child;
152
153 spin_lock_bh(&atchan->lock);
154 list_for_each_entry(child, &desc->tx_list, desc_node)
155 dev_vdbg(chan2dev(&atchan->chan_common),
156 "moving child desc %p to freelist\n",
157 child);
158 list_splice_init(&desc->tx_list, &atchan->free_list);
159 dev_vdbg(chan2dev(&atchan->chan_common),
160 "moving desc %p to freelist\n", desc);
161 list_add(&desc->desc_node, &atchan->free_list);
162 spin_unlock_bh(&atchan->lock);
163 }
164}
165
166/**
167 * atc_assign_cookie - compute and assign new cookie
168 * @atchan: channel we work on
169 * @desc: descriptor to asign cookie for
170 *
171 * Called with atchan->lock held and bh disabled
172 */
173static dma_cookie_t
174atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc)
175{
176 dma_cookie_t cookie = atchan->chan_common.cookie;
177
178 if (++cookie < 0)
179 cookie = 1;
180
181 atchan->chan_common.cookie = cookie;
182 desc->txd.cookie = cookie;
183
184 return cookie;
185}
186
187/**
188 * atc_dostart - starts the DMA engine for real
189 * @atchan: the channel we want to start
190 * @first: first descriptor in the list we want to begin with
191 *
192 * Called with atchan->lock held and bh disabled
193 */
194static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
195{
196 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
197
198 /* ASSERT: channel is idle */
199 if (atc_chan_is_enabled(atchan)) {
200 dev_err(chan2dev(&atchan->chan_common),
201 "BUG: Attempted to start non-idle channel\n");
202 dev_err(chan2dev(&atchan->chan_common),
203 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
204 channel_readl(atchan, SADDR),
205 channel_readl(atchan, DADDR),
206 channel_readl(atchan, CTRLA),
207 channel_readl(atchan, CTRLB),
208 channel_readl(atchan, DSCR));
209
210 /* The tasklet will hopefully advance the queue... */
211 return;
212 }
213
214 vdbg_dump_regs(atchan);
215
216 /* clear any pending interrupt */
217 while (dma_readl(atdma, EBCISR))
218 cpu_relax();
219
220 channel_writel(atchan, SADDR, 0);
221 channel_writel(atchan, DADDR, 0);
222 channel_writel(atchan, CTRLA, 0);
223 channel_writel(atchan, CTRLB, 0);
224 channel_writel(atchan, DSCR, first->txd.phys);
225 dma_writel(atdma, CHER, atchan->mask);
226
227 vdbg_dump_regs(atchan);
228}
229
230/**
231 * atc_chain_complete - finish work for one transaction chain
232 * @atchan: channel we work on
233 * @desc: descriptor at the head of the chain we want do complete
234 *
235 * Called with atchan->lock held and bh disabled */
236static void
237atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
238{
239 dma_async_tx_callback callback;
240 void *param;
241 struct dma_async_tx_descriptor *txd = &desc->txd;
242
243 dev_vdbg(chan2dev(&atchan->chan_common),
244 "descriptor %u complete\n", txd->cookie);
245
246 atchan->completed_cookie = txd->cookie;
247 callback = txd->callback;
248 param = txd->callback_param;
249
250 /* move children to free_list */
251 list_splice_init(&desc->tx_list, &atchan->free_list);
252 /* move myself to free_list */
253 list_move(&desc->desc_node, &atchan->free_list);
254
255 /* unmap dma addresses */
256 if (!atchan->chan_common.private) {
257 struct device *parent = chan2parent(&atchan->chan_common);
258 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
259 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
260 dma_unmap_single(parent,
261 desc->lli.daddr,
262 desc->len, DMA_FROM_DEVICE);
263 else
264 dma_unmap_page(parent,
265 desc->lli.daddr,
266 desc->len, DMA_FROM_DEVICE);
267 }
268 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
269 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
270 dma_unmap_single(parent,
271 desc->lli.saddr,
272 desc->len, DMA_TO_DEVICE);
273 else
274 dma_unmap_page(parent,
275 desc->lli.saddr,
276 desc->len, DMA_TO_DEVICE);
277 }
278 }
279
280 /*
281 * The API requires that no submissions are done from a
282 * callback, so we don't need to drop the lock here
283 */
284 if (callback)
285 callback(param);
286
287 dma_run_dependencies(txd);
288}
289
290/**
291 * atc_complete_all - finish work for all transactions
292 * @atchan: channel to complete transactions for
293 *
294 * Eventually submit queued descriptors if any
295 *
296 * Assume channel is idle while calling this function
297 * Called with atchan->lock held and bh disabled
298 */
299static void atc_complete_all(struct at_dma_chan *atchan)
300{
301 struct at_desc *desc, *_desc;
302 LIST_HEAD(list);
303
304 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
305
306 BUG_ON(atc_chan_is_enabled(atchan));
307
308 /*
309 * Submit queued descriptors ASAP, i.e. before we go through
310 * the completed ones.
311 */
312 if (!list_empty(&atchan->queue))
313 atc_dostart(atchan, atc_first_queued(atchan));
314 /* empty active_list now it is completed */
315 list_splice_init(&atchan->active_list, &list);
316 /* empty queue list by moving descriptors (if any) to active_list */
317 list_splice_init(&atchan->queue, &atchan->active_list);
318
319 list_for_each_entry_safe(desc, _desc, &list, desc_node)
320 atc_chain_complete(atchan, desc);
321}
322
323/**
324 * atc_cleanup_descriptors - cleanup up finished descriptors in active_list
325 * @atchan: channel to be cleaned up
326 *
327 * Called with atchan->lock held and bh disabled
328 */
329static void atc_cleanup_descriptors(struct at_dma_chan *atchan)
330{
331 struct at_desc *desc, *_desc;
332 struct at_desc *child;
333
334 dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n");
335
336 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
337 if (!(desc->lli.ctrla & ATC_DONE))
338 /* This one is currently in progress */
339 return;
340
341 list_for_each_entry(child, &desc->tx_list, desc_node)
342 if (!(child->lli.ctrla & ATC_DONE))
343 /* Currently in progress */
344 return;
345
346 /*
347 * No descriptors so far seem to be in progress, i.e.
348 * this chain must be done.
349 */
350 atc_chain_complete(atchan, desc);
351 }
352}
353
354/**
355 * atc_advance_work - at the end of a transaction, move forward
356 * @atchan: channel where the transaction ended
357 *
358 * Called with atchan->lock held and bh disabled
359 */
360static void atc_advance_work(struct at_dma_chan *atchan)
361{
362 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
363
364 if (list_empty(&atchan->active_list) ||
365 list_is_singular(&atchan->active_list)) {
366 atc_complete_all(atchan);
367 } else {
368 atc_chain_complete(atchan, atc_first_active(atchan));
369 /* advance work */
370 atc_dostart(atchan, atc_first_active(atchan));
371 }
372}
373
374
375/**
376 * atc_handle_error - handle errors reported by DMA controller
377 * @atchan: channel where error occurs
378 *
379 * Called with atchan->lock held and bh disabled
380 */
381static void atc_handle_error(struct at_dma_chan *atchan)
382{
383 struct at_desc *bad_desc;
384 struct at_desc *child;
385
386 /*
387 * The descriptor currently at the head of the active list is
388 * broked. Since we don't have any way to report errors, we'll
389 * just have to scream loudly and try to carry on.
390 */
391 bad_desc = atc_first_active(atchan);
392 list_del_init(&bad_desc->desc_node);
393
394 /* As we are stopped, take advantage to push queued descriptors
395 * in active_list */
396 list_splice_init(&atchan->queue, atchan->active_list.prev);
397
398 /* Try to restart the controller */
399 if (!list_empty(&atchan->active_list))
400 atc_dostart(atchan, atc_first_active(atchan));
401
402 /*
403 * KERN_CRITICAL may seem harsh, but since this only happens
404 * when someone submits a bad physical address in a
405 * descriptor, we should consider ourselves lucky that the
406 * controller flagged an error instead of scribbling over
407 * random memory locations.
408 */
409 dev_crit(chan2dev(&atchan->chan_common),
410 "Bad descriptor submitted for DMA!\n");
411 dev_crit(chan2dev(&atchan->chan_common),
412 " cookie: %d\n", bad_desc->txd.cookie);
413 atc_dump_lli(atchan, &bad_desc->lli);
414 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
415 atc_dump_lli(atchan, &child->lli);
416
417 /* Pretend the descriptor completed successfully */
418 atc_chain_complete(atchan, bad_desc);
419}
420
421
422/*-- IRQ & Tasklet ---------------------------------------------------*/
423
424static void atc_tasklet(unsigned long data)
425{
426 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
427
428 /* Channel cannot be enabled here */
429 if (atc_chan_is_enabled(atchan)) {
430 dev_err(chan2dev(&atchan->chan_common),
431 "BUG: channel enabled in tasklet\n");
432 return;
433 }
434
435 spin_lock(&atchan->lock);
436 if (test_and_clear_bit(0, &atchan->error_status))
437 atc_handle_error(atchan);
438 else
439 atc_advance_work(atchan);
440
441 spin_unlock(&atchan->lock);
442}
443
444static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
445{
446 struct at_dma *atdma = (struct at_dma *)dev_id;
447 struct at_dma_chan *atchan;
448 int i;
449 u32 status, pending, imr;
450 int ret = IRQ_NONE;
451
452 do {
453 imr = dma_readl(atdma, EBCIMR);
454 status = dma_readl(atdma, EBCISR);
455 pending = status & imr;
456
457 if (!pending)
458 break;
459
460 dev_vdbg(atdma->dma_common.dev,
461 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
462 status, imr, pending);
463
464 for (i = 0; i < atdma->dma_common.chancnt; i++) {
465 atchan = &atdma->chan[i];
466 if (pending & (AT_DMA_CBTC(i) | AT_DMA_ERR(i))) {
467 if (pending & AT_DMA_ERR(i)) {
468 /* Disable channel on AHB error */
469 dma_writel(atdma, CHDR, atchan->mask);
470 /* Give information to tasklet */
471 set_bit(0, &atchan->error_status);
472 }
473 tasklet_schedule(&atchan->tasklet);
474 ret = IRQ_HANDLED;
475 }
476 }
477
478 } while (pending);
479
480 return ret;
481}
482
483
484/*-- DMA Engine API --------------------------------------------------*/
485
486/**
487 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
488 * @desc: descriptor at the head of the transaction chain
489 *
490 * Queue chain if DMA engine is working already
491 *
492 * Cookie increment and adding to active_list or queue must be atomic
493 */
494static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
495{
496 struct at_desc *desc = txd_to_at_desc(tx);
497 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
498 dma_cookie_t cookie;
499
500 spin_lock_bh(&atchan->lock);
501 cookie = atc_assign_cookie(atchan, desc);
502
503 if (list_empty(&atchan->active_list)) {
504 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
505 desc->txd.cookie);
506 atc_dostart(atchan, desc);
507 list_add_tail(&desc->desc_node, &atchan->active_list);
508 } else {
509 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
510 desc->txd.cookie);
511 list_add_tail(&desc->desc_node, &atchan->queue);
512 }
513
514 spin_unlock_bh(&atchan->lock);
515
516 return cookie;
517}
518
519/**
520 * atc_prep_dma_memcpy - prepare a memcpy operation
521 * @chan: the channel to prepare operation on
522 * @dest: operation virtual destination address
523 * @src: operation virtual source address
524 * @len: operation length
525 * @flags: tx descriptor status flags
526 */
527static struct dma_async_tx_descriptor *
528atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
529 size_t len, unsigned long flags)
530{
531 struct at_dma_chan *atchan = to_at_dma_chan(chan);
532 struct at_desc *desc = NULL;
533 struct at_desc *first = NULL;
534 struct at_desc *prev = NULL;
535 size_t xfer_count;
536 size_t offset;
537 unsigned int src_width;
538 unsigned int dst_width;
539 u32 ctrla;
540 u32 ctrlb;
541
542 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
543 dest, src, len, flags);
544
545 if (unlikely(!len)) {
546 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
547 return NULL;
548 }
549
550 ctrla = ATC_DEFAULT_CTRLA;
551 ctrlb = ATC_DEFAULT_CTRLB
552 | ATC_SRC_ADDR_MODE_INCR
553 | ATC_DST_ADDR_MODE_INCR
554 | ATC_FC_MEM2MEM;
555
556 /*
557 * We can be a lot more clever here, but this should take care
558 * of the most common optimization.
559 */
560 if (!((src | dest | len) & 3)) {
561 ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
562 src_width = dst_width = 2;
563 } else if (!((src | dest | len) & 1)) {
564 ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
565 src_width = dst_width = 1;
566 } else {
567 ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
568 src_width = dst_width = 0;
569 }
570
571 for (offset = 0; offset < len; offset += xfer_count << src_width) {
572 xfer_count = min_t(size_t, (len - offset) >> src_width,
573 ATC_BTSIZE_MAX);
574
575 desc = atc_desc_get(atchan);
576 if (!desc)
577 goto err_desc_get;
578
579 desc->lli.saddr = src + offset;
580 desc->lli.daddr = dest + offset;
581 desc->lli.ctrla = ctrla | xfer_count;
582 desc->lli.ctrlb = ctrlb;
583
584 desc->txd.cookie = 0;
585 async_tx_ack(&desc->txd);
586
587 if (!first) {
588 first = desc;
589 } else {
590 /* inform the HW lli about chaining */
591 prev->lli.dscr = desc->txd.phys;
592 /* insert the link descriptor to the LD ring */
593 list_add_tail(&desc->desc_node,
594 &first->tx_list);
595 }
596 prev = desc;
597 }
598
599 /* First descriptor of the chain embedds additional information */
600 first->txd.cookie = -EBUSY;
601 first->len = len;
602
603 /* set end-of-link to the last link descriptor of list*/
604 set_desc_eol(desc);
605
606 desc->txd.flags = flags; /* client is in control of this ack */
607
608 return &first->txd;
609
610err_desc_get:
611 atc_desc_put(atchan, first);
612 return NULL;
613}
614
615
616/**
617 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
618 * @chan: DMA channel
619 * @sgl: scatterlist to transfer to/from
620 * @sg_len: number of entries in @scatterlist
621 * @direction: DMA direction
622 * @flags: tx descriptor status flags
623 */
624static struct dma_async_tx_descriptor *
625atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
626 unsigned int sg_len, enum dma_data_direction direction,
627 unsigned long flags)
628{
629 struct at_dma_chan *atchan = to_at_dma_chan(chan);
630 struct at_dma_slave *atslave = chan->private;
631 struct at_desc *first = NULL;
632 struct at_desc *prev = NULL;
633 u32 ctrla;
634 u32 ctrlb;
635 dma_addr_t reg;
636 unsigned int reg_width;
637 unsigned int mem_width;
638 unsigned int i;
639 struct scatterlist *sg;
640 size_t total_len = 0;
641
642 dev_vdbg(chan2dev(chan), "prep_slave_sg: %s f0x%lx\n",
643 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
644 flags);
645
646 if (unlikely(!atslave || !sg_len)) {
647 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
648 return NULL;
649 }
650
651 reg_width = atslave->reg_width;
652
653 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
654 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN;
655
656 switch (direction) {
657 case DMA_TO_DEVICE:
658 ctrla |= ATC_DST_WIDTH(reg_width);
659 ctrlb |= ATC_DST_ADDR_MODE_FIXED
660 | ATC_SRC_ADDR_MODE_INCR
661 | ATC_FC_MEM2PER;
662 reg = atslave->tx_reg;
663 for_each_sg(sgl, sg, sg_len, i) {
664 struct at_desc *desc;
665 u32 len;
666 u32 mem;
667
668 desc = atc_desc_get(atchan);
669 if (!desc)
670 goto err_desc_get;
671
672 mem = sg_phys(sg);
673 len = sg_dma_len(sg);
674 mem_width = 2;
675 if (unlikely(mem & 3 || len & 3))
676 mem_width = 0;
677
678 desc->lli.saddr = mem;
679 desc->lli.daddr = reg;
680 desc->lli.ctrla = ctrla
681 | ATC_SRC_WIDTH(mem_width)
682 | len >> mem_width;
683 desc->lli.ctrlb = ctrlb;
684
685 if (!first) {
686 first = desc;
687 } else {
688 /* inform the HW lli about chaining */
689 prev->lli.dscr = desc->txd.phys;
690 /* insert the link descriptor to the LD ring */
691 list_add_tail(&desc->desc_node,
692 &first->tx_list);
693 }
694 prev = desc;
695 total_len += len;
696 }
697 break;
698 case DMA_FROM_DEVICE:
699 ctrla |= ATC_SRC_WIDTH(reg_width);
700 ctrlb |= ATC_DST_ADDR_MODE_INCR
701 | ATC_SRC_ADDR_MODE_FIXED
702 | ATC_FC_PER2MEM;
703
704 reg = atslave->rx_reg;
705 for_each_sg(sgl, sg, sg_len, i) {
706 struct at_desc *desc;
707 u32 len;
708 u32 mem;
709
710 desc = atc_desc_get(atchan);
711 if (!desc)
712 goto err_desc_get;
713
714 mem = sg_phys(sg);
715 len = sg_dma_len(sg);
716 mem_width = 2;
717 if (unlikely(mem & 3 || len & 3))
718 mem_width = 0;
719
720 desc->lli.saddr = reg;
721 desc->lli.daddr = mem;
722 desc->lli.ctrla = ctrla
723 | ATC_DST_WIDTH(mem_width)
724 | len >> mem_width;
725 desc->lli.ctrlb = ctrlb;
726
727 if (!first) {
728 first = desc;
729 } else {
730 /* inform the HW lli about chaining */
731 prev->lli.dscr = desc->txd.phys;
732 /* insert the link descriptor to the LD ring */
733 list_add_tail(&desc->desc_node,
734 &first->tx_list);
735 }
736 prev = desc;
737 total_len += len;
738 }
739 break;
740 default:
741 return NULL;
742 }
743
744 /* set end-of-link to the last link descriptor of list*/
745 set_desc_eol(prev);
746
747 /* First descriptor of the chain embedds additional information */
748 first->txd.cookie = -EBUSY;
749 first->len = total_len;
750
751 /* last link descriptor of list is responsible of flags */
752 prev->txd.flags = flags; /* client is in control of this ack */
753
754 return &first->txd;
755
756err_desc_get:
757 dev_err(chan2dev(chan), "not enough descriptors available\n");
758 atc_desc_put(atchan, first);
759 return NULL;
760}
761
762static void atc_terminate_all(struct dma_chan *chan)
763{
764 struct at_dma_chan *atchan = to_at_dma_chan(chan);
765 struct at_dma *atdma = to_at_dma(chan->device);
766 struct at_desc *desc, *_desc;
767 LIST_HEAD(list);
768
769 /*
770 * This is only called when something went wrong elsewhere, so
771 * we don't really care about the data. Just disable the
772 * channel. We still have to poll the channel enable bit due
773 * to AHB/HSB limitations.
774 */
775 spin_lock_bh(&atchan->lock);
776
777 dma_writel(atdma, CHDR, atchan->mask);
778
779 /* confirm that this channel is disabled */
780 while (dma_readl(atdma, CHSR) & atchan->mask)
781 cpu_relax();
782
783 /* active_list entries will end up before queued entries */
784 list_splice_init(&atchan->queue, &list);
785 list_splice_init(&atchan->active_list, &list);
786
787 spin_unlock_bh(&atchan->lock);
788
789 /* Flush all pending and queued descriptors */
790 list_for_each_entry_safe(desc, _desc, &list, desc_node)
791 atc_chain_complete(atchan, desc);
792}
793
794/**
795 * atc_is_tx_complete - poll for transaction completion
796 * @chan: DMA channel
797 * @cookie: transaction identifier to check status of
798 * @done: if not %NULL, updated with last completed transaction
799 * @used: if not %NULL, updated with last used transaction
800 *
801 * If @done and @used are passed in, upon return they reflect the driver
802 * internal state and can be used with dma_async_is_complete() to check
803 * the status of multiple cookies without re-checking hardware state.
804 */
805static enum dma_status
806atc_is_tx_complete(struct dma_chan *chan,
807 dma_cookie_t cookie,
808 dma_cookie_t *done, dma_cookie_t *used)
809{
810 struct at_dma_chan *atchan = to_at_dma_chan(chan);
811 dma_cookie_t last_used;
812 dma_cookie_t last_complete;
813 enum dma_status ret;
814
815 dev_vdbg(chan2dev(chan), "is_tx_complete: %d (d%d, u%d)\n",
816 cookie, done ? *done : 0, used ? *used : 0);
817
818 spin_lock_bh(atchan->lock);
819
820 last_complete = atchan->completed_cookie;
821 last_used = chan->cookie;
822
823 ret = dma_async_is_complete(cookie, last_complete, last_used);
824 if (ret != DMA_SUCCESS) {
825 atc_cleanup_descriptors(atchan);
826
827 last_complete = atchan->completed_cookie;
828 last_used = chan->cookie;
829
830 ret = dma_async_is_complete(cookie, last_complete, last_used);
831 }
832
833 spin_unlock_bh(atchan->lock);
834
835 if (done)
836 *done = last_complete;
837 if (used)
838 *used = last_used;
839
840 return ret;
841}
842
843/**
844 * atc_issue_pending - try to finish work
845 * @chan: target DMA channel
846 */
847static void atc_issue_pending(struct dma_chan *chan)
848{
849 struct at_dma_chan *atchan = to_at_dma_chan(chan);
850
851 dev_vdbg(chan2dev(chan), "issue_pending\n");
852
853 if (!atc_chan_is_enabled(atchan)) {
854 spin_lock_bh(&atchan->lock);
855 atc_advance_work(atchan);
856 spin_unlock_bh(&atchan->lock);
857 }
858}
859
860/**
861 * atc_alloc_chan_resources - allocate resources for DMA channel
862 * @chan: allocate descriptor resources for this channel
863 * @client: current client requesting the channel be ready for requests
864 *
865 * return - the number of allocated descriptors
866 */
867static int atc_alloc_chan_resources(struct dma_chan *chan)
868{
869 struct at_dma_chan *atchan = to_at_dma_chan(chan);
870 struct at_dma *atdma = to_at_dma(chan->device);
871 struct at_desc *desc;
872 struct at_dma_slave *atslave;
873 int i;
874 u32 cfg;
875 LIST_HEAD(tmp_list);
876
877 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
878
879 /* ASSERT: channel is idle */
880 if (atc_chan_is_enabled(atchan)) {
881 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
882 return -EIO;
883 }
884
885 cfg = ATC_DEFAULT_CFG;
886
887 atslave = chan->private;
888 if (atslave) {
889 /*
890 * We need controller-specific data to set up slave
891 * transfers.
892 */
893 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
894
895 /* if cfg configuration specified take it instad of default */
896 if (atslave->cfg)
897 cfg = atslave->cfg;
898 }
899
900 /* have we already been set up?
901 * reconfigure channel but no need to reallocate descriptors */
902 if (!list_empty(&atchan->free_list))
903 return atchan->descs_allocated;
904
905 /* Allocate initial pool of descriptors */
906 for (i = 0; i < init_nr_desc_per_channel; i++) {
907 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
908 if (!desc) {
909 dev_err(atdma->dma_common.dev,
910 "Only %d initial descriptors\n", i);
911 break;
912 }
913 list_add_tail(&desc->desc_node, &tmp_list);
914 }
915
916 spin_lock_bh(&atchan->lock);
917 atchan->descs_allocated = i;
918 list_splice(&tmp_list, &atchan->free_list);
919 atchan->completed_cookie = chan->cookie = 1;
920 spin_unlock_bh(&atchan->lock);
921
922 /* channel parameters */
923 channel_writel(atchan, CFG, cfg);
924
925 dev_dbg(chan2dev(chan),
926 "alloc_chan_resources: allocated %d descriptors\n",
927 atchan->descs_allocated);
928
929 return atchan->descs_allocated;
930}
931
932/**
933 * atc_free_chan_resources - free all channel resources
934 * @chan: DMA channel
935 */
936static void atc_free_chan_resources(struct dma_chan *chan)
937{
938 struct at_dma_chan *atchan = to_at_dma_chan(chan);
939 struct at_dma *atdma = to_at_dma(chan->device);
940 struct at_desc *desc, *_desc;
941 LIST_HEAD(list);
942
943 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
944 atchan->descs_allocated);
945
946 /* ASSERT: channel is idle */
947 BUG_ON(!list_empty(&atchan->active_list));
948 BUG_ON(!list_empty(&atchan->queue));
949 BUG_ON(atc_chan_is_enabled(atchan));
950
951 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
952 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
953 list_del(&desc->desc_node);
954 /* free link descriptor */
955 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
956 }
957 list_splice_init(&atchan->free_list, &list);
958 atchan->descs_allocated = 0;
959
960 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
961}
962
963
964/*-- Module Management -----------------------------------------------*/
965
966/**
967 * at_dma_off - disable DMA controller
968 * @atdma: the Atmel HDAMC device
969 */
970static void at_dma_off(struct at_dma *atdma)
971{
972 dma_writel(atdma, EN, 0);
973
974 /* disable all interrupts */
975 dma_writel(atdma, EBCIDR, -1L);
976
977 /* confirm that all channels are disabled */
978 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
979 cpu_relax();
980}
981
982static int __init at_dma_probe(struct platform_device *pdev)
983{
984 struct at_dma_platform_data *pdata;
985 struct resource *io;
986 struct at_dma *atdma;
987 size_t size;
988 int irq;
989 int err;
990 int i;
991
992 /* get DMA Controller parameters from platform */
993 pdata = pdev->dev.platform_data;
994 if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS)
995 return -EINVAL;
996
997 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
998 if (!io)
999 return -EINVAL;
1000
1001 irq = platform_get_irq(pdev, 0);
1002 if (irq < 0)
1003 return irq;
1004
1005 size = sizeof(struct at_dma);
1006 size += pdata->nr_channels * sizeof(struct at_dma_chan);
1007 atdma = kzalloc(size, GFP_KERNEL);
1008 if (!atdma)
1009 return -ENOMEM;
1010
1011 /* discover transaction capabilites from the platform data */
1012 atdma->dma_common.cap_mask = pdata->cap_mask;
1013 atdma->all_chan_mask = (1 << pdata->nr_channels) - 1;
1014
1015 size = io->end - io->start + 1;
1016 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1017 err = -EBUSY;
1018 goto err_kfree;
1019 }
1020
1021 atdma->regs = ioremap(io->start, size);
1022 if (!atdma->regs) {
1023 err = -ENOMEM;
1024 goto err_release_r;
1025 }
1026
1027 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1028 if (IS_ERR(atdma->clk)) {
1029 err = PTR_ERR(atdma->clk);
1030 goto err_clk;
1031 }
1032 clk_enable(atdma->clk);
1033
1034 /* force dma off, just in case */
1035 at_dma_off(atdma);
1036
1037 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1038 if (err)
1039 goto err_irq;
1040
1041 platform_set_drvdata(pdev, atdma);
1042
1043 /* create a pool of consistent memory blocks for hardware descriptors */
1044 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
1045 &pdev->dev, sizeof(struct at_desc),
1046 4 /* word alignment */, 0);
1047 if (!atdma->dma_desc_pool) {
1048 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1049 err = -ENOMEM;
1050 goto err_pool_create;
1051 }
1052
1053 /* clear any pending interrupt */
1054 while (dma_readl(atdma, EBCISR))
1055 cpu_relax();
1056
1057 /* initialize channels related values */
1058 INIT_LIST_HEAD(&atdma->dma_common.channels);
1059 for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) {
1060 struct at_dma_chan *atchan = &atdma->chan[i];
1061
1062 atchan->chan_common.device = &atdma->dma_common;
1063 atchan->chan_common.cookie = atchan->completed_cookie = 1;
1064 atchan->chan_common.chan_id = i;
1065 list_add_tail(&atchan->chan_common.device_node,
1066 &atdma->dma_common.channels);
1067
1068 atchan->ch_regs = atdma->regs + ch_regs(i);
1069 spin_lock_init(&atchan->lock);
1070 atchan->mask = 1 << i;
1071
1072 INIT_LIST_HEAD(&atchan->active_list);
1073 INIT_LIST_HEAD(&atchan->queue);
1074 INIT_LIST_HEAD(&atchan->free_list);
1075
1076 tasklet_init(&atchan->tasklet, atc_tasklet,
1077 (unsigned long)atchan);
1078 atc_enable_irq(atchan);
1079 }
1080
1081 /* set base routines */
1082 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
1083 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
1084 atdma->dma_common.device_is_tx_complete = atc_is_tx_complete;
1085 atdma->dma_common.device_issue_pending = atc_issue_pending;
1086 atdma->dma_common.dev = &pdev->dev;
1087
1088 /* set prep routines based on capability */
1089 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
1090 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
1091
1092 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
1093 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
1094 atdma->dma_common.device_terminate_all = atc_terminate_all;
1095 }
1096
1097 dma_writel(atdma, EN, AT_DMA_ENABLE);
1098
1099 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1100 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1101 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1102 atdma->dma_common.chancnt);
1103
1104 dma_async_device_register(&atdma->dma_common);
1105
1106 return 0;
1107
1108err_pool_create:
1109 platform_set_drvdata(pdev, NULL);
1110 free_irq(platform_get_irq(pdev, 0), atdma);
1111err_irq:
1112 clk_disable(atdma->clk);
1113 clk_put(atdma->clk);
1114err_clk:
1115 iounmap(atdma->regs);
1116 atdma->regs = NULL;
1117err_release_r:
1118 release_mem_region(io->start, size);
1119err_kfree:
1120 kfree(atdma);
1121 return err;
1122}
1123
1124static int __exit at_dma_remove(struct platform_device *pdev)
1125{
1126 struct at_dma *atdma = platform_get_drvdata(pdev);
1127 struct dma_chan *chan, *_chan;
1128 struct resource *io;
1129
1130 at_dma_off(atdma);
1131 dma_async_device_unregister(&atdma->dma_common);
1132
1133 dma_pool_destroy(atdma->dma_desc_pool);
1134 platform_set_drvdata(pdev, NULL);
1135 free_irq(platform_get_irq(pdev, 0), atdma);
1136
1137 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1138 device_node) {
1139 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1140
1141 /* Disable interrupts */
1142 atc_disable_irq(atchan);
1143 tasklet_disable(&atchan->tasklet);
1144
1145 tasklet_kill(&atchan->tasklet);
1146 list_del(&chan->device_node);
1147 }
1148
1149 clk_disable(atdma->clk);
1150 clk_put(atdma->clk);
1151
1152 iounmap(atdma->regs);
1153 atdma->regs = NULL;
1154
1155 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1156 release_mem_region(io->start, io->end - io->start + 1);
1157
1158 kfree(atdma);
1159
1160 return 0;
1161}
1162
1163static void at_dma_shutdown(struct platform_device *pdev)
1164{
1165 struct at_dma *atdma = platform_get_drvdata(pdev);
1166
1167 at_dma_off(platform_get_drvdata(pdev));
1168 clk_disable(atdma->clk);
1169}
1170
1171static int at_dma_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1172{
1173 struct at_dma *atdma = platform_get_drvdata(pdev);
1174
1175 at_dma_off(platform_get_drvdata(pdev));
1176 clk_disable(atdma->clk);
1177 return 0;
1178}
1179
1180static int at_dma_resume_early(struct platform_device *pdev)
1181{
1182 struct at_dma *atdma = platform_get_drvdata(pdev);
1183
1184 clk_enable(atdma->clk);
1185 dma_writel(atdma, EN, AT_DMA_ENABLE);
1186 return 0;
1187
1188}
1189
1190static struct platform_driver at_dma_driver = {
1191 .remove = __exit_p(at_dma_remove),
1192 .shutdown = at_dma_shutdown,
1193 .suspend_late = at_dma_suspend_late,
1194 .resume_early = at_dma_resume_early,
1195 .driver = {
1196 .name = "at_hdmac",
1197 },
1198};
1199
1200static int __init at_dma_init(void)
1201{
1202 return platform_driver_probe(&at_dma_driver, at_dma_probe);
1203}
1204module_init(at_dma_init);
1205
1206static void __exit at_dma_exit(void)
1207{
1208 platform_driver_unregister(&at_dma_driver);
1209}
1210module_exit(at_dma_exit);
1211
1212MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1213MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1214MODULE_LICENSE("GPL");
1215MODULE_ALIAS("platform:at_hdmac");
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-01 21:04:28 -0400