diff options
Diffstat (limited to 'drivers/crypto/talitos.h')
| -rw-r--r-- | drivers/crypto/talitos.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h index e6b87770df03..125560a1d5f7 100644 --- a/drivers/crypto/talitos.h +++ b/drivers/crypto/talitos.h | |||
| @@ -56,6 +56,7 @@ | |||
| 56 | #define TALITOS_CCCR_CONT 0x2 /* channel continue */ | 56 | #define TALITOS_CCCR_CONT 0x2 /* channel continue */ |
| 57 | #define TALITOS_CCCR_RESET 0x1 /* channel reset */ | 57 | #define TALITOS_CCCR_RESET 0x1 /* channel reset */ |
| 58 | #define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c) | 58 | #define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c) |
| 59 | #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */ | ||
| 59 | #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */ | 60 | #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */ |
| 60 | #define TALITOS_CCCR_LO_NT 0x4 /* notification type */ | 61 | #define TALITOS_CCCR_LO_NT 0x4 /* notification type */ |
| 61 | #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */ | 62 | #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */ |
| @@ -103,6 +104,9 @@ | |||
| 103 | #define TALITOS_AESUISR_LO 0x4034 | 104 | #define TALITOS_AESUISR_LO 0x4034 |
| 104 | #define TALITOS_MDEUISR 0x6030 /* message digest unit */ | 105 | #define TALITOS_MDEUISR 0x6030 /* message digest unit */ |
| 105 | #define TALITOS_MDEUISR_LO 0x6034 | 106 | #define TALITOS_MDEUISR_LO 0x6034 |
| 107 | #define TALITOS_MDEUICR 0x6038 /* interrupt control */ | ||
| 108 | #define TALITOS_MDEUICR_LO 0x603c | ||
| 109 | #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */ | ||
| 106 | #define TALITOS_AFEUISR 0x8030 /* arc4 unit */ | 110 | #define TALITOS_AFEUISR 0x8030 /* arc4 unit */ |
| 107 | #define TALITOS_AFEUISR_LO 0x8034 | 111 | #define TALITOS_AFEUISR_LO 0x8034 |
| 108 | #define TALITOS_RNGUISR 0xa030 /* random number unit */ | 112 | #define TALITOS_RNGUISR 0xa030 /* random number unit */ |
| @@ -131,6 +135,9 @@ | |||
| 131 | 135 | ||
| 132 | /* written back when done */ | 136 | /* written back when done */ |
| 133 | #define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000) | 137 | #define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000) |
| 138 | #define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000) | ||
| 139 | #define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000) | ||
| 140 | #define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000) | ||
| 134 | 141 | ||
| 135 | /* primary execution unit select */ | 142 | /* primary execution unit select */ |
| 136 | #define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000) | 143 | #define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000) |
| @@ -169,6 +176,7 @@ | |||
| 169 | #define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000) | 176 | #define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000) |
| 170 | 177 | ||
| 171 | /* secondary execution unit mode (MODE1) and derivatives */ | 178 | /* secondary execution unit mode (MODE1) and derivatives */ |
| 179 | #define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000) | ||
| 172 | #define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000) | 180 | #define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000) |
| 173 | #define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800) | 181 | #define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800) |
| 174 | #define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400) | 182 | #define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400) |