diff options
Diffstat (limited to 'drivers/crypto/talitos.h')
-rw-r--r-- | drivers/crypto/talitos.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h index 05c57b730e99..0b746aca4587 100644 --- a/drivers/crypto/talitos.h +++ b/drivers/crypto/talitos.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Freescale SEC (talitos) device register and descriptor header defines | 2 | * Freescale SEC (talitos) device register and descriptor header defines |
3 | * | 3 | * |
4 | * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. | 4 | * Copyright (c) 2006-2010 Freescale Semiconductor, Inc. |
5 | * | 5 | * |
6 | * Redistribution and use in source and binary forms, with or without | 6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions | 7 | * modification, are permitted provided that the following conditions |
@@ -164,6 +164,7 @@ | |||
164 | #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000) | 164 | #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000) |
165 | #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000) | 165 | #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000) |
166 | #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000) | 166 | #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000) |
167 | #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000) | ||
167 | #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000) | 168 | #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000) |
168 | #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000) | 169 | #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000) |
169 | #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000) | 170 | #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000) |
@@ -187,6 +188,7 @@ | |||
187 | #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000) | 188 | #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000) |
188 | #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800) | 189 | #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800) |
189 | #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400) | 190 | #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400) |
191 | #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300) | ||
190 | #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200) | 192 | #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200) |
191 | #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100) | 193 | #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100) |
192 | #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000) | 194 | #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000) |