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path: root/drivers/cpufreq/exynos4x12-cpufreq.c
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Diffstat (limited to 'drivers/cpufreq/exynos4x12-cpufreq.c')
-rw-r--r--drivers/cpufreq/exynos4x12-cpufreq.c388
1 files changed, 59 insertions, 329 deletions
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8c5a7afa5b0b..0661039e5d4a 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -20,26 +20,18 @@
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h> 21#include <mach/cpufreq.h>
22 22
23#define CPUFREQ_LEVEL_END (L13 + 1)
24
25static int max_support_idx;
26static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
27
28static struct clk *cpu_clk; 23static struct clk *cpu_clk;
29static struct clk *moutcore; 24static struct clk *moutcore;
30static struct clk *mout_mpll; 25static struct clk *mout_mpll;
31static struct clk *mout_apll; 26static struct clk *mout_apll;
32 27
33struct cpufreq_clkdiv { 28static unsigned int exynos4x12_volt_table[] = {
34 unsigned int index; 29 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
35 unsigned int clkdiv; 30 1000000, 987500, 975000, 950000, 925000, 900000, 900000
36 unsigned int clkdiv1;
37}; 31};
38 32
39static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
40
41static struct cpufreq_frequency_table exynos4x12_freq_table[] = { 33static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
42 {L0, 1500 * 1000}, 34 {L0, CPUFREQ_ENTRY_INVALID},
43 {L1, 1400 * 1000}, 35 {L1, 1400 * 1000},
44 {L2, 1300 * 1000}, 36 {L2, 1300 * 1000},
45 {L3, 1200 * 1000}, 37 {L3, 1200 * 1000},
@@ -56,247 +48,54 @@ static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
56 {0, CPUFREQ_TABLE_END}, 48 {0, CPUFREQ_TABLE_END},
57}; 49};
58 50
59static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END]; 51static struct apll_freq *apll_freq_4x12;
60 52
61static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = { 53static struct apll_freq apll_freq_4212[] = {
62 /* 54 /*
63 * Clock divider value for following 55 * values:
64 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 56 * freq
65 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 57 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
58 * clock divider for COPY, HPM, RESERVED
59 * PLL M, P, S
66 */ 60 */
67 /* ARM L0: 1500 MHz */ 61 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
68 { 0, 3, 7, 0, 6, 1, 2, 0 }, 62 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
69 63 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
70 /* ARM L1: 1400 MHz */ 64 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
71 { 0, 3, 7, 0, 6, 1, 2, 0 }, 65 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
72 66 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
73 /* ARM L2: 1300 MHz */ 67 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
74 { 0, 3, 7, 0, 5, 1, 2, 0 }, 68 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
75 69 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
76 /* ARM L3: 1200 MHz */ 70 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
77 { 0, 3, 7, 0, 5, 1, 2, 0 }, 71 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
78 72 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
79 /* ARM L4: 1100 MHz */ 73 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
80 { 0, 3, 6, 0, 4, 1, 2, 0 }, 74 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
81
82 /* ARM L5: 1000 MHz */
83 { 0, 2, 5, 0, 4, 1, 1, 0 },
84
85 /* ARM L6: 900 MHz */
86 { 0, 2, 5, 0, 3, 1, 1, 0 },
87
88 /* ARM L7: 800 MHz */
89 { 0, 2, 5, 0, 3, 1, 1, 0 },
90
91 /* ARM L8: 700 MHz */
92 { 0, 2, 4, 0, 3, 1, 1, 0 },
93
94 /* ARM L9: 600 MHz */
95 { 0, 2, 4, 0, 3, 1, 1, 0 },
96
97 /* ARM L10: 500 MHz */
98 { 0, 2, 4, 0, 3, 1, 1, 0 },
99
100 /* ARM L11: 400 MHz */
101 { 0, 2, 4, 0, 3, 1, 1, 0 },
102
103 /* ARM L12: 300 MHz */
104 { 0, 2, 4, 0, 2, 1, 1, 0 },
105
106 /* ARM L13: 200 MHz */
107 { 0, 1, 3, 0, 1, 1, 1, 0 },
108}; 75};
109 76
110static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = { 77static struct apll_freq apll_freq_4412[] = {
111 /* 78 /*
112 * Clock divider value for following 79 * values:
113 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 80 * freq
114 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 81 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
115 */ 82 * clock divider for COPY, HPM, CORES
116 /* ARM L0: 1500 MHz */ 83 * PLL M, P, S
117 { 0, 3, 7, 0, 6, 1, 2, 0 },
118
119 /* ARM L1: 1400 MHz */
120 { 0, 3, 7, 0, 6, 1, 2, 0 },
121
122 /* ARM L2: 1300 MHz */
123 { 0, 3, 7, 0, 5, 1, 2, 0 },
124
125 /* ARM L3: 1200 MHz */
126 { 0, 3, 7, 0, 5, 1, 2, 0 },
127
128 /* ARM L4: 1100 MHz */
129 { 0, 3, 6, 0, 4, 1, 2, 0 },
130
131 /* ARM L5: 1000 MHz */
132 { 0, 2, 5, 0, 4, 1, 1, 0 },
133
134 /* ARM L6: 900 MHz */
135 { 0, 2, 5, 0, 3, 1, 1, 0 },
136
137 /* ARM L7: 800 MHz */
138 { 0, 2, 5, 0, 3, 1, 1, 0 },
139
140 /* ARM L8: 700 MHz */
141 { 0, 2, 4, 0, 3, 1, 1, 0 },
142
143 /* ARM L9: 600 MHz */
144 { 0, 2, 4, 0, 3, 1, 1, 0 },
145
146 /* ARM L10: 500 MHz */
147 { 0, 2, 4, 0, 3, 1, 1, 0 },
148
149 /* ARM L11: 400 MHz */
150 { 0, 2, 4, 0, 3, 1, 1, 0 },
151
152 /* ARM L12: 300 MHz */
153 { 0, 2, 4, 0, 2, 1, 1, 0 },
154
155 /* ARM L13: 200 MHz */
156 { 0, 1, 3, 0, 1, 1, 1, 0 },
157};
158
159static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
160 /* Clock divider value for following
161 * { DIVCOPY, DIVHPM }
162 */
163 /* ARM L0: 1500 MHz */
164 { 6, 0 },
165
166 /* ARM L1: 1400 MHz */
167 { 6, 0 },
168
169 /* ARM L2: 1300 MHz */
170 { 5, 0 },
171
172 /* ARM L3: 1200 MHz */
173 { 5, 0 },
174
175 /* ARM L4: 1100 MHz */
176 { 4, 0 },
177
178 /* ARM L5: 1000 MHz */
179 { 4, 0 },
180
181 /* ARM L6: 900 MHz */
182 { 3, 0 },
183
184 /* ARM L7: 800 MHz */
185 { 3, 0 },
186
187 /* ARM L8: 700 MHz */
188 { 3, 0 },
189
190 /* ARM L9: 600 MHz */
191 { 3, 0 },
192
193 /* ARM L10: 500 MHz */
194 { 3, 0 },
195
196 /* ARM L11: 400 MHz */
197 { 3, 0 },
198
199 /* ARM L12: 300 MHz */
200 { 3, 0 },
201
202 /* ARM L13: 200 MHz */
203 { 3, 0 },
204};
205
206static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
207 /* Clock divider value for following
208 * { DIVCOPY, DIVHPM, DIVCORES }
209 */ 84 */
210 /* ARM L0: 1500 MHz */ 85 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
211 { 6, 0, 7 }, 86 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
212 87 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
213 /* ARM L1: 1400 MHz */ 88 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
214 { 6, 0, 6 }, 89 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
215 90 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
216 /* ARM L2: 1300 MHz */ 91 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
217 { 5, 0, 6 }, 92 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
218 93 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
219 /* ARM L3: 1200 MHz */ 94 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
220 { 5, 0, 5 }, 95 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
221 96 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
222 /* ARM L4: 1100 MHz */ 97 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
223 { 4, 0, 5 }, 98 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
224
225 /* ARM L5: 1000 MHz */
226 { 4, 0, 4 },
227
228 /* ARM L6: 900 MHz */
229 { 3, 0, 4 },
230
231 /* ARM L7: 800 MHz */
232 { 3, 0, 3 },
233
234 /* ARM L8: 700 MHz */
235 { 3, 0, 3 },
236
237 /* ARM L9: 600 MHz */
238 { 3, 0, 2 },
239
240 /* ARM L10: 500 MHz */
241 { 3, 0, 2 },
242
243 /* ARM L11: 400 MHz */
244 { 3, 0, 1 },
245
246 /* ARM L12: 300 MHz */
247 { 3, 0, 1 },
248
249 /* ARM L13: 200 MHz */
250 { 3, 0, 0 },
251};
252
253static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
254 /* APLL FOUT L0: 1500 MHz */
255 ((250 << 16) | (4 << 8) | (0x0)),
256
257 /* APLL FOUT L1: 1400 MHz */
258 ((175 << 16) | (3 << 8) | (0x0)),
259
260 /* APLL FOUT L2: 1300 MHz */
261 ((325 << 16) | (6 << 8) | (0x0)),
262
263 /* APLL FOUT L3: 1200 MHz */
264 ((200 << 16) | (4 << 8) | (0x0)),
265
266 /* APLL FOUT L4: 1100 MHz */
267 ((275 << 16) | (6 << 8) | (0x0)),
268
269 /* APLL FOUT L5: 1000 MHz */
270 ((125 << 16) | (3 << 8) | (0x0)),
271
272 /* APLL FOUT L6: 900 MHz */
273 ((150 << 16) | (4 << 8) | (0x0)),
274
275 /* APLL FOUT L7: 800 MHz */
276 ((100 << 16) | (3 << 8) | (0x0)),
277
278 /* APLL FOUT L8: 700 MHz */
279 ((175 << 16) | (3 << 8) | (0x1)),
280
281 /* APLL FOUT L9: 600 MHz */
282 ((200 << 16) | (4 << 8) | (0x1)),
283
284 /* APLL FOUT L10: 500 MHz */
285 ((125 << 16) | (3 << 8) | (0x1)),
286
287 /* APLL FOUT L11 400 MHz */
288 ((100 << 16) | (3 << 8) | (0x1)),
289
290 /* APLL FOUT L12: 300 MHz */
291 ((200 << 16) | (4 << 8) | (0x2)),
292
293 /* APLL FOUT L13: 200 MHz */
294 ((100 << 16) | (3 << 8) | (0x2)),
295};
296
297static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
298 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
299 1000000, 987500, 975000, 950000, 925000, 900000, 900000
300}; 99};
301 100
302static void exynos4x12_set_clkdiv(unsigned int div_index) 101static void exynos4x12_set_clkdiv(unsigned int div_index)
@@ -306,7 +105,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
306 105
307 /* Change Divider - CPU0 */ 106 /* Change Divider - CPU0 */
308 107
309 tmp = exynos4x12_clkdiv_table[div_index].clkdiv; 108 tmp = apll_freq_4x12[div_index].clk_div_cpu0;
310 109
311 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); 110 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
312 111
@@ -314,7 +113,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
314 cpu_relax(); 113 cpu_relax();
315 114
316 /* Change Divider - CPU1 */ 115 /* Change Divider - CPU1 */
317 tmp = exynos4x12_clkdiv_table[div_index].clkdiv1; 116 tmp = apll_freq_4x12[div_index].clk_div_cpu1;
318 117
319 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); 118 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
320 if (soc_is_exynos4212()) 119 if (soc_is_exynos4212())
@@ -341,14 +140,14 @@ static void exynos4x12_set_apll(unsigned int index)
341 } while (tmp != 0x2); 140 } while (tmp != 0x2);
342 141
343 /* 2. Set APLL Lock time */ 142 /* 2. Set APLL Lock time */
344 pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f); 143 pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
345 144
346 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK); 145 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
347 146
348 /* 3. Change PLL PMS values */ 147 /* 3. Change PLL PMS values */
349 tmp = __raw_readl(EXYNOS4_APLL_CON0); 148 tmp = __raw_readl(EXYNOS4_APLL_CON0);
350 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 149 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
351 tmp |= exynos4x12_apll_pms_table[index]; 150 tmp |= apll_freq_4x12[index].mps;
352 __raw_writel(tmp, EXYNOS4_APLL_CON0); 151 __raw_writel(tmp, EXYNOS4_APLL_CON0);
353 152
354 /* 4. wait_lock_time */ 153 /* 4. wait_lock_time */
@@ -367,10 +166,10 @@ static void exynos4x12_set_apll(unsigned int index)
367 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); 166 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
368} 167}
369 168
370bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index) 169static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
371{ 170{
372 unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8; 171 unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
373 unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8; 172 unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
374 173
375 return (old_pm == new_pm) ? 0 : 1; 174 return (old_pm == new_pm) ? 0 : 1;
376} 175}
@@ -387,7 +186,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
387 /* 2. Change just s value in apll m,p,s value */ 186 /* 2. Change just s value in apll m,p,s value */
388 tmp = __raw_readl(EXYNOS4_APLL_CON0); 187 tmp = __raw_readl(EXYNOS4_APLL_CON0);
389 tmp &= ~(0x7 << 0); 188 tmp &= ~(0x7 << 0);
390 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 189 tmp |= apll_freq_4x12[new_index].mps & 0x7;
391 __raw_writel(tmp, EXYNOS4_APLL_CON0); 190 __raw_writel(tmp, EXYNOS4_APLL_CON0);
392 191
393 } else { 192 } else {
@@ -402,7 +201,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
402 /* 1. Change just s value in apll m,p,s value */ 201 /* 1. Change just s value in apll m,p,s value */
403 tmp = __raw_readl(EXYNOS4_APLL_CON0); 202 tmp = __raw_readl(EXYNOS4_APLL_CON0);
404 tmp &= ~(0x7 << 0); 203 tmp &= ~(0x7 << 0);
405 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 204 tmp |= apll_freq_4x12[new_index].mps & 0x7;
406 __raw_writel(tmp, EXYNOS4_APLL_CON0); 205 __raw_writel(tmp, EXYNOS4_APLL_CON0);
407 /* 2. Change the system clock divider values */ 206 /* 2. Change the system clock divider values */
408 exynos4x12_set_clkdiv(new_index); 207 exynos4x12_set_clkdiv(new_index);
@@ -416,27 +215,10 @@ static void exynos4x12_set_frequency(unsigned int old_index,
416 } 215 }
417} 216}
418 217
419static void __init set_volt_table(void)
420{
421 unsigned int i;
422
423 max_support_idx = L1;
424
425 /* Not supported */
426 exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
427
428 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
429 exynos4x12_volt_table[i] = asv_voltage_4x12[i];
430}
431
432int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) 218int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
433{ 219{
434 int i;
435 unsigned int tmp;
436 unsigned long rate; 220 unsigned long rate;
437 221
438 set_volt_table();
439
440 cpu_clk = clk_get(NULL, "armclk"); 222 cpu_clk = clk_get(NULL, "armclk");
441 if (IS_ERR(cpu_clk)) 223 if (IS_ERR(cpu_clk))
442 return PTR_ERR(cpu_clk); 224 return PTR_ERR(cpu_clk);
@@ -455,66 +237,14 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
455 if (IS_ERR(mout_apll)) 237 if (IS_ERR(mout_apll))
456 goto err_mout_apll; 238 goto err_mout_apll;
457 239
458 for (i = L0; i < CPUFREQ_LEVEL_END; i++) { 240 if (soc_is_exynos4212())
459 241 apll_freq_4x12 = apll_freq_4212;
460 exynos4x12_clkdiv_table[i].index = i; 242 else
461 243 apll_freq_4x12 = apll_freq_4412;
462 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
463
464 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
465 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
466 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
467 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
468 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
469 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
470 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
471
472 if (soc_is_exynos4212()) {
473 tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
474 (clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
475 (clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
476 (clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
477 (clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
478 (clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
479 (clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
480 } else {
481 tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
482
483 tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
484 (clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
485 (clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
486 (clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
487 (clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
488 (clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
489 (clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
490 (clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
491 }
492
493 exynos4x12_clkdiv_table[i].clkdiv = tmp;
494
495 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
496
497 if (soc_is_exynos4212()) {
498 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
499 EXYNOS4_CLKDIV_CPU1_HPM_MASK);
500 tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
501 (clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
502 } else {
503 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
504 EXYNOS4_CLKDIV_CPU1_HPM_MASK |
505 EXYNOS4_CLKDIV_CPU1_CORES_MASK);
506 tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
507 (clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
508 (clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
509 }
510 exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
511 }
512 244
513 info->mpll_freq_khz = rate; 245 info->mpll_freq_khz = rate;
514 info->pm_lock_idx = L5; 246 /* 800Mhz */
515 info->pll_safe_idx = L7; 247 info->pll_safe_idx = L7;
516 info->max_support_idx = max_support_idx;
517 info->min_support_idx = min_support_idx;
518 info->cpu_clk = cpu_clk; 248 info->cpu_clk = cpu_clk;
519 info->volt_table = exynos4x12_volt_table; 249 info->volt_table = exynos4x12_volt_table;
520 info->freq_table = exynos4x12_freq_table; 250 info->freq_table = exynos4x12_freq_table;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 13:34:29 -0400