4 files changed, 400 insertions, 0 deletions

diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
new file mode 100644
index 000000000000..a52225470225
--- /dev/null
+++ b/drivers/clocksource/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
+obj-$(CONFIG_X86_PM_TIMER)      += acpi_pm.o
+obj-$(CONFIG_SCx200HR_TIMER)    += scx200_hrt.o
diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
new file mode 100644
index 000000000000..7ad3be8c0f49
--- /dev/null
+++ b/drivers/clocksource/acpi_pm.c
@@ -0,0 +1,177 @@
+/*
+ * linux/drivers/clocksource/acpi_pm.c
+ *
+ * This file contains the ACPI PM based clocksource.
+ *
+ * This code was largely moved from the i386 timer_pm.c file
+ * which was (C) Dominik Brodowski <linux@brodo.de> 2003
+ * and contained the following comments:
+ *
+ * Driver to use the Power Management Timer (PMTMR) available in some
+ * southbridges as primary timing source for the Linux kernel.
+ *
+ * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
+ * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
+ *
+ * This file is licensed under the GPL v2.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+/* Number of PMTMR ticks expected during calibration run */
+#define PMTMR_TICKS_PER_SEC 3579545
+
+/*
+ * The I/O port the PMTMR resides at.
+ * The location is detected during setup_arch(),
+ * in arch/i386/acpi/boot.c
+ */
+u32 pmtmr_ioport __read_mostly;
+
+#define ACPI_PM_MASK CLOCKSOURCE_MASK(24) /* limit it to 24 bits */
+
+static inline u32 read_pmtmr(void)
+{
+        /* mask the output to 24 bits */
+        return inl(pmtmr_ioport) & ACPI_PM_MASK;
+}
+
+static cycle_t acpi_pm_read_verified(void)
+{
+        u32 v1 = 0, v2 = 0, v3 = 0;
+
+        /*
+         * It has been reported that because of various broken
+         * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
+         * source is not latched, you must read it multiple
+         * times to ensure a safe value is read:
+         */
+        do {
+                v1 = read_pmtmr();
+                v2 = read_pmtmr();
+                v3 = read_pmtmr();
+        } while ((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
+                        || (v3 > v1 && v3 < v2));
+
+        return (cycle_t)v2;
+}
+
+static cycle_t acpi_pm_read(void)
+{
+        return (cycle_t)read_pmtmr();
+}
+
+static struct clocksource clocksource_acpi_pm = {
+        .name           = "acpi_pm",
+        .rating         = 200,
+        .read           = acpi_pm_read,
+        .mask           = (cycle_t)ACPI_PM_MASK,
+        .mult           = 0, /*to be caluclated*/
+        .shift          = 22,
+        .is_continuous  = 1,
+};
+
+
+#ifdef CONFIG_PCI
+static int acpi_pm_good;
+static int __init acpi_pm_good_setup(char *__str)
+{
+       acpi_pm_good = 1;
+       return 1;
+}
+__setup("acpi_pm_good", acpi_pm_good_setup);
+
+static inline void acpi_pm_need_workaround(void)
+{
+        clocksource_acpi_pm.read = acpi_pm_read_verified;
+        clocksource_acpi_pm.rating = 110;
+}
+
+/*
+ * PIIX4 Errata:
+ *
+ * The power management timer may return improper results when read.
+ * Although the timer value settles properly after incrementing,
+ * while incrementing there is a 3 ns window every 69.8 ns where the
+ * timer value is indeterminate (a 4.2% chance that the data will be
+ * incorrect when read). As a result, the ACPI free running count up
+ * timer specification is violated due to erroneous reads.
+ */
+static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
+{
+        u8 rev;
+
+        if (acpi_pm_good)
+                return;
+
+        pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
+        /* the bug has been fixed in PIIX4M */
+        if (rev < 3) {
+                printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
+                       " Due to workarounds for a bug,\n"
+                       "* this clock source is slow. Consider trying"
+                       " other clock sources\n");
+
+                acpi_pm_need_workaround();
+        }
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
+                        acpi_pm_check_blacklist);
+
+static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
+{
+        if (acpi_pm_good)
+                return;
+
+        printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
+               " workarounds for a bug,\n"
+               "* this clock source is slow. If you are sure your timer"
+               " does not have\n"
+               "* this bug, please use \"acpi_pm_good\" to disable the"
+               " workaround\n");
+
+        acpi_pm_need_workaround();
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
+                        acpi_pm_check_graylist);
+#endif
+
+
+static int __init init_acpi_pm_clocksource(void)
+{
+        u32 value1, value2;
+        unsigned int i;
+
+        if (!pmtmr_ioport)
+                return -ENODEV;
+
+        clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
+                                                clocksource_acpi_pm.shift);
+
+        /* "verify" this timing source: */
+        value1 = read_pmtmr();
+        for (i = 0; i < 10000; i++) {
+                value2 = read_pmtmr();
+                if (value2 == value1)
+                        continue;
+                if (value2 > value1)
+                        goto pm_good;
+                if ((value2 < value1) && ((value2) < 0xFFF))
+                        goto pm_good;
+                printk(KERN_INFO "PM-Timer had inconsistent results:"
+                        " 0x%#x, 0x%#x - aborting.\n", value1, value2);
+                return -EINVAL;
+        }
+        printk(KERN_INFO "PM-Timer had no reasonable result:"
+                        " 0x%#x - aborting.\n", value1);
+        return -ENODEV;
+
+pm_good:
+        return clocksource_register(&clocksource_acpi_pm);
+}
+
+module_init(init_acpi_pm_clocksource);
diff --git a/drivers/clocksource/cyclone.c b/drivers/clocksource/cyclone.c
new file mode 100644
index 000000000000..bf4d3d50d1c4
--- /dev/null
+++ b/drivers/clocksource/cyclone.c
@@ -0,0 +1,119 @@
+#include <linux/clocksource.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/timex.h>
+#include <linux/init.h>
+
+#include <asm/pgtable.h>
+#include <asm/io.h>
+
+#include "mach_timer.h"
+
+#define CYCLONE_CBAR_ADDR       0xFEB00CD0      /* base address ptr */
+#define CYCLONE_PMCC_OFFSET     0x51A0          /* offset to control register */
+#define CYCLONE_MPCS_OFFSET     0x51A8          /* offset to select register */
+#define CYCLONE_MPMC_OFFSET     0x51D0          /* offset to count register */
+#define CYCLONE_TIMER_FREQ      99780000        /* 100Mhz, but not really */
+#define CYCLONE_TIMER_MASK      CLOCKSOURCE_MASK(32) /* 32 bit mask */
+
+int use_cyclone = 0;
+static void __iomem *cyclone_ptr;
+
+static cycle_t read_cyclone(void)
+{
+        return (cycle_t)readl(cyclone_ptr);
+}
+
+static struct clocksource clocksource_cyclone = {
+        .name           = "cyclone",
+        .rating         = 250,
+        .read           = read_cyclone,
+        .mask           = CYCLONE_TIMER_MASK,
+        .mult           = 10,
+        .shift          = 0,
+        .is_continuous  = 1,
+};
+
+static int __init init_cyclone_clocksource(void)
+{
+        unsigned long base;     /* saved value from CBAR */
+        unsigned long offset;
+        u32 __iomem* volatile cyclone_timer;    /* Cyclone MPMC0 register */
+        u32 __iomem* reg;
+        int i;
+
+        /* make sure we're on a summit box: */
+        if (!use_cyclone)
+                return -ENODEV;
+
+        printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
+
+        /* find base address: */
+        offset = CYCLONE_CBAR_ADDR;
+        reg = ioremap_nocache(offset, sizeof(reg));
+        if (!reg) {
+                printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
+                return -ENODEV;
+        }
+        /* even on 64bit systems, this is only 32bits: */
+        base = readl(reg);
+        if (!base) {
+                printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
+                return -ENODEV;
+        }
+        iounmap(reg);
+
+        /* setup PMCC: */
+        offset = base + CYCLONE_PMCC_OFFSET;
+        reg = ioremap_nocache(offset, sizeof(reg));
+        if (!reg) {
+                printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
+                return -ENODEV;
+        }
+        writel(0x00000001,reg);
+        iounmap(reg);
+
+        /* setup MPCS: */
+        offset = base + CYCLONE_MPCS_OFFSET;
+        reg = ioremap_nocache(offset, sizeof(reg));
+        if (!reg) {
+                printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
+                return -ENODEV;
+        }
+        writel(0x00000001,reg);
+        iounmap(reg);
+
+        /* map in cyclone_timer: */
+        offset = base + CYCLONE_MPMC_OFFSET;
+        cyclone_timer = ioremap_nocache(offset, sizeof(u64));
+        if (!cyclone_timer) {
+                printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
+                return -ENODEV;
+        }
+
+        /* quick test to make sure its ticking: */
+        for (i = 0; i < 3; i++){
+                u32 old = readl(cyclone_timer);
+                int stall = 100;
+
+                while (stall--)
+                        barrier();
+
+                if (readl(cyclone_timer) == old) {
+                        printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
+                        iounmap(cyclone_timer);
+                        cyclone_timer = NULL;
+                        return -ENODEV;
+                }
+        }
+        cyclone_ptr = cyclone_timer;
+
+        /* sort out mult/shift values: */
+        clocksource_cyclone.shift = 22;
+        clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
+                                                clocksource_cyclone.shift);
+
+        return clocksource_register(&clocksource_cyclone);
+}
+
+module_init(init_cyclone_clocksource);
diff --git a/drivers/clocksource/scx200_hrt.c b/drivers/clocksource/scx200_hrt.c
new file mode 100644
index 000000000000..d418b8297211
--- /dev/null
+++ b/drivers/clocksource/scx200_hrt.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2006 Jim Cromie
+ *
+ * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
+ * high-resolution timer.  The Geode SC-1100 (at least) has a buggy
+ * time stamp counter (TSC), which loses time unless 'idle=poll' is
+ * given as a boot-arg. In its absence, the Generic Timekeeping code
+ * will detect and de-rate the bad TSC, allowing this timer to take
+ * over timekeeping duties.
+ *
+ * Based on work by John Stultz, and Ted Phelps (in a 2.6.12-rc6 patch)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/scx200.h>
+
+#define NAME "scx200_hrt"
+
+static int mhz27;
+module_param(mhz27, int, 0);    /* load time only */
+MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
+
+static int ppm;
+module_param(ppm, int, 0);      /* load time only */
+MODULE_PARM_DESC(ppm, "+-adjust to actual XO freq (ppm)");
+
+/* HiRes Timer configuration register address */
+#define SCx200_TMCNFG_OFFSET (SCx200_TIMER_OFFSET + 5)
+
+/* and config settings */
+#define HR_TMEN (1 << 0)        /* timer interrupt enable */
+#define HR_TMCLKSEL (1 << 1)    /* 1|0 counts at 27|1 MHz */
+#define HR_TM27MPD (1 << 2)     /* 1 turns off input clock (power-down) */
+
+/* The base timer frequency, * 27 if selected */
+#define HRT_FREQ   1000000
+
+static cycle_t read_hrt(void)
+{
+        /* Read the timer value */
+        return (cycle_t) inl(scx200_cb_base + SCx200_TIMER_OFFSET);
+}
+
+#define HRT_SHIFT_1     22
+#define HRT_SHIFT_27    26
+
+static struct clocksource cs_hrt = {
+        .name           = "scx200_hrt",
+        .rating         = 250,
+        .read           = read_hrt,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .is_continuous  = 1,
+        /* mult, shift are set based on mhz27 flag */
+};
+
+static int __init init_hrt_clocksource(void)
+{
+        /* Make sure scx200 has initializedd the configuration block */
+        if (!scx200_cb_present())
+                return -ENODEV;
+
+        /* Reserve the timer's ISA io-region for ourselves */
+        if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
+                            SCx200_TIMER_SIZE,
+                            "NatSemi SCx200 High-Resolution Timer")) {
+                printk(KERN_WARNING NAME ": unable to lock timer region\n");
+                return -ENODEV;
+        }
+
+        /* write timer config */
+        outb(HR_TMEN | (mhz27) ? HR_TMCLKSEL : 0,
+             scx200_cb_base + SCx200_TMCNFG_OFFSET);
+
+        if (mhz27) {
+                cs_hrt.shift = HRT_SHIFT_27;
+                cs_hrt.mult = clocksource_hz2mult((HRT_FREQ + ppm) * 27,
+                                                  cs_hrt.shift);
+        } else {
+                cs_hrt.shift = HRT_SHIFT_1;
+                cs_hrt.mult = clocksource_hz2mult(HRT_FREQ + ppm,
+                                                  cs_hrt.shift);
+        }
+        printk(KERN_INFO "enabling scx200 high-res timer (%s MHz +%d ppm)\n",
+                mhz27 ? "27":"1", ppm);
+
+        return clocksource_register(&cs_hrt);
+}
+
+module_init(init_hrt_clocksource);
+
+MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
+MODULE_DESCRIPTION("clocksource on SCx200 HiRes Timer");
+MODULE_LICENSE("GPL");