4 files changed, 917 insertions, 19 deletions

diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1efb2879a94f..eef216f7f61d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_X86_CYCLONE_TIMER)	+= cyclone.o
 obj-$(CONFIG_X86_PM_TIMER)      += acpi_pm.o
 obj-$(CONFIG_SCx200HR_TIMER)    += scx200_hrt.o
 obj-$(CONFIG_SH_TIMER_CMT)      += sh_cmt.o
+obj-$(CONFIG_SH_TIMER_MTU2)     += sh_mtu2.o
+obj-$(CONFIG_SH_TIMER_TMU)      += sh_tmu.o
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 1c92c39a53aa..cf56a2af5fe1 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -18,7 +18,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/bootmem.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
@@ -29,7 +28,7 @@
 #include <linux/err.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
-#include <linux/sh_cmt.h>
+#include <linux/sh_timer.h>
 
 struct sh_cmt_priv {
         void __iomem *mapbase;
@@ -47,6 +46,7 @@ struct sh_cmt_priv {
         unsigned long rate;
         spinlock_t lock;
         struct clock_event_device ced;
+        struct clocksource cs;
         unsigned long total_cycles;
 };
 
@@ -59,7 +59,7 @@ static DEFINE_SPINLOCK(sh_cmt_lock);
 
 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
 {
-        struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
         void __iomem *base = p->mapbase;
         unsigned long offs;
 
@@ -83,7 +83,7 @@ static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
                                 unsigned long value)
 {
-        struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
         void __iomem *base = p->mapbase;
         unsigned long offs;
 
@@ -110,23 +110,28 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
                                         int *has_wrapped)
 {
         unsigned long v1, v2, v3;
+        int o1, o2;
+
+        o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
 
         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
         do {
+                o2 = o1;
                 v1 = sh_cmt_read(p, CMCNT);
                 v2 = sh_cmt_read(p, CMCNT);
                 v3 = sh_cmt_read(p, CMCNT);
-        } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
-                          || (v3 > v1 && v3 < v2)));
+                o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
+        } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
+                          || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 
-        *has_wrapped = sh_cmt_read(p, CMCSR) & p->overflow_bit;
+        *has_wrapped = o1;
         return v2;
 }
 
 
 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
 {
-        struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
         unsigned long flags, value;
 
         /* start stop register shared by multiple timer channels */
@@ -144,7 +149,7 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
 
 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
 {
-        struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
         int ret;
 
         /* enable clock */
@@ -153,16 +158,18 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
                 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
                 return ret;
         }
-        *rate = clk_get_rate(p->clk) / 8;
 
         /* make sure channel is disabled */
         sh_cmt_start_stop_ch(p, 0);
 
         /* configure channel, periodic mode and maximum timeout */
-        if (p->width == 16)
-                sh_cmt_write(p, CMCSR, 0);
-        else
+        if (p->width == 16) {
+                *rate = clk_get_rate(p->clk) / 512;
+                sh_cmt_write(p, CMCSR, 0x43);
+        } else {
+                *rate = clk_get_rate(p->clk) / 8;
                 sh_cmt_write(p, CMCSR, 0x01a4);
+        }
 
         sh_cmt_write(p, CMCOR, 0xffffffff);
         sh_cmt_write(p, CMCNT, 0);
@@ -376,6 +383,68 @@ static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
         spin_unlock_irqrestore(&p->lock, flags);
 }
 
+static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
+{
+        return container_of(cs, struct sh_cmt_priv, cs);
+}
+
+static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
+{
+        struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
+        unsigned long flags, raw;
+        unsigned long value;
+        int has_wrapped;
+
+        spin_lock_irqsave(&p->lock, flags);
+        value = p->total_cycles;
+        raw = sh_cmt_get_counter(p, &has_wrapped);
+
+        if (unlikely(has_wrapped))
+                raw += p->match_value;
+        spin_unlock_irqrestore(&p->lock, flags);
+
+        return value + raw;
+}
+
+static int sh_cmt_clocksource_enable(struct clocksource *cs)
+{
+        struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
+        int ret;
+
+        p->total_cycles = 0;
+
+        ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
+        if (ret)
+                return ret;
+
+        /* TODO: calculate good shift from rate and counter bit width */
+        cs->shift = 0;
+        cs->mult = clocksource_hz2mult(p->rate, cs->shift);
+        return 0;
+}
+
+static void sh_cmt_clocksource_disable(struct clocksource *cs)
+{
+        sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
+}
+
+static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
+                                       char *name, unsigned long rating)
+{
+        struct clocksource *cs = &p->cs;
+
+        cs->name = name;
+        cs->rating = rating;
+        cs->read = sh_cmt_clocksource_read;
+        cs->enable = sh_cmt_clocksource_enable;
+        cs->disable = sh_cmt_clocksource_disable;
+        cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
+        cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
+        pr_info("sh_cmt: %s used as clock source\n", cs->name);
+        clocksource_register(cs);
+        return 0;
+}
+
 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
 {
         return container_of(ced, struct sh_cmt_priv, ced);
@@ -468,9 +537,9 @@ static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
         clockevents_register_device(ced);
 }
 
-int sh_cmt_register(struct sh_cmt_priv *p, char *name,
-                    unsigned long clockevent_rating,
-                    unsigned long clocksource_rating)
+static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
+                           unsigned long clockevent_rating,
+                           unsigned long clocksource_rating)
 {
         if (p->width == (sizeof(p->max_match_value) * 8))
                 p->max_match_value = ~0;
@@ -483,12 +552,15 @@ int sh_cmt_register(struct sh_cmt_priv *p, char *name,
         if (clockevent_rating)
                 sh_cmt_register_clockevent(p, name, clockevent_rating);
 
+        if (clocksource_rating)
+                sh_cmt_register_clocksource(p, name, clocksource_rating);
+
         return 0;
 }
 
 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 {
-        struct sh_cmt_config *cfg = pdev->dev.platform_data;
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
         struct resource *res;
         int irq, ret;
         ret = -ENXIO;
@@ -545,7 +617,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
         if (resource_size(res) == 6) {
                 p->width = 16;
                 p->overflow_bit = 0x80;
-                p->clear_bits = ~0xc0;
+                p->clear_bits = ~0x80;
         } else {
                 p->width = 32;
                 p->overflow_bit = 0x8000;
@@ -566,8 +638,14 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
 static int __devinit sh_cmt_probe(struct platform_device *pdev)
 {
         struct sh_cmt_priv *p = platform_get_drvdata(pdev);
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
         int ret;
 
+        if (p) {
+                pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
+                return 0;
+        }
+
         p = kmalloc(sizeof(*p), GFP_KERNEL);
         if (p == NULL) {
                 dev_err(&pdev->dev, "failed to allocate driver data\n");
@@ -577,7 +655,6 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
         ret = sh_cmt_setup(p, pdev);
         if (ret) {
                 kfree(p);
-
                 platform_set_drvdata(pdev, NULL);
         }
         return ret;
@@ -606,6 +683,7 @@ static void __exit sh_cmt_exit(void)
         platform_driver_unregister(&sh_cmt_device_driver);
 }
 
+early_platform_init("earlytimer", &sh_cmt_device_driver);
 module_init(sh_cmt_init);
 module_exit(sh_cmt_exit);
 
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
new file mode 100644
index 000000000000..d1ae75454d10
--- /dev/null
+++ b/drivers/clocksource/sh_mtu2.c
@@ -0,0 +1,357 @@
+/*
+ * SuperH Timer Support - MTU2
+ *
+ *  Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clockchips.h>
+#include <linux/sh_timer.h>
+
+struct sh_mtu2_priv {
+        void __iomem *mapbase;
+        struct clk *clk;
+        struct irqaction irqaction;
+        struct platform_device *pdev;
+        unsigned long rate;
+        unsigned long periodic;
+        struct clock_event_device ced;
+};
+
+static DEFINE_SPINLOCK(sh_mtu2_lock);
+
+#define TSTR -1 /* shared register */
+#define TCR  0 /* channel register */
+#define TMDR 1 /* channel register */
+#define TIOR 2 /* channel register */
+#define TIER 3 /* channel register */
+#define TSR  4 /* channel register */
+#define TCNT 5 /* channel register */
+#define TGR  6 /* channel register */
+
+static unsigned long mtu2_reg_offs[] = {
+        [TCR] = 0,
+        [TMDR] = 1,
+        [TIOR] = 2,
+        [TIER] = 4,
+        [TSR] = 5,
+        [TCNT] = 6,
+        [TGR] = 8,
+};
+
+static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        void __iomem *base = p->mapbase;
+        unsigned long offs;
+
+        if (reg_nr == TSTR)
+                return ioread8(base + cfg->channel_offset);
+
+        offs = mtu2_reg_offs[reg_nr];
+
+        if ((reg_nr == TCNT) || (reg_nr == TGR))
+                return ioread16(base + offs);
+        else
+                return ioread8(base + offs);
+}
+
+static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
+                                unsigned long value)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        void __iomem *base = p->mapbase;
+        unsigned long offs;
+
+        if (reg_nr == TSTR) {
+                iowrite8(value, base + cfg->channel_offset);
+                return;
+        }
+
+        offs = mtu2_reg_offs[reg_nr];
+
+        if ((reg_nr == TCNT) || (reg_nr == TGR))
+                iowrite16(value, base + offs);
+        else
+                iowrite8(value, base + offs);
+}
+
+static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        unsigned long flags, value;
+
+        /* start stop register shared by multiple timer channels */
+        spin_lock_irqsave(&sh_mtu2_lock, flags);
+        value = sh_mtu2_read(p, TSTR);
+
+        if (start)
+                value |= 1 << cfg->timer_bit;
+        else
+                value &= ~(1 << cfg->timer_bit);
+
+        sh_mtu2_write(p, TSTR, value);
+        spin_unlock_irqrestore(&sh_mtu2_lock, flags);
+}
+
+static int sh_mtu2_enable(struct sh_mtu2_priv *p)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        int ret;
+
+        /* enable clock */
+        ret = clk_enable(p->clk);
+        if (ret) {
+                pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk);
+                return ret;
+        }
+
+        /* make sure channel is disabled */
+        sh_mtu2_start_stop_ch(p, 0);
+
+        p->rate = clk_get_rate(p->clk) / 64;
+        p->periodic = (p->rate + HZ/2) / HZ;
+
+        /* "Periodic Counter Operation" */
+        sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
+        sh_mtu2_write(p, TIOR, 0);
+        sh_mtu2_write(p, TGR, p->periodic);
+        sh_mtu2_write(p, TCNT, 0);
+        sh_mtu2_write(p, TMDR, 0);
+        sh_mtu2_write(p, TIER, 0x01);
+
+        /* enable channel */
+        sh_mtu2_start_stop_ch(p, 1);
+
+        return 0;
+}
+
+static void sh_mtu2_disable(struct sh_mtu2_priv *p)
+{
+        /* disable channel */
+        sh_mtu2_start_stop_ch(p, 0);
+
+        /* stop clock */
+        clk_disable(p->clk);
+}
+
+static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
+{
+        struct sh_mtu2_priv *p = dev_id;
+
+        /* acknowledge interrupt */
+        sh_mtu2_read(p, TSR);
+        sh_mtu2_write(p, TSR, 0xfe);
+
+        /* notify clockevent layer */
+        p->ced.event_handler(&p->ced);
+        return IRQ_HANDLED;
+}
+
+static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
+{
+        return container_of(ced, struct sh_mtu2_priv, ced);
+}
+
+static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *ced)
+{
+        struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
+        int disabled = 0;
+
+        /* deal with old setting first */
+        switch (ced->mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                sh_mtu2_disable(p);
+                disabled = 1;
+                break;
+        default:
+                break;
+        }
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                pr_info("sh_mtu2: %s used for periodic clock events\n",
+                        ced->name);
+                sh_mtu2_enable(p);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+                if (!disabled)
+                        sh_mtu2_disable(p);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                break;
+        }
+}
+
+static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
+                                       char *name, unsigned long rating)
+{
+        struct clock_event_device *ced = &p->ced;
+        int ret;
+
+        memset(ced, 0, sizeof(*ced));
+
+        ced->name = name;
+        ced->features = CLOCK_EVT_FEAT_PERIODIC;
+        ced->rating = rating;
+        ced->cpumask = cpumask_of(0);
+        ced->set_mode = sh_mtu2_clock_event_mode;
+
+        ret = setup_irq(p->irqaction.irq, &p->irqaction);
+        if (ret) {
+                pr_err("sh_mtu2: failed to request irq %d\n",
+                       p->irqaction.irq);
+                return;
+        }
+
+        pr_info("sh_mtu2: %s used for clock events\n", ced->name);
+        clockevents_register_device(ced);
+}
+
+static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
+                            unsigned long clockevent_rating)
+{
+        if (clockevent_rating)
+                sh_mtu2_register_clockevent(p, name, clockevent_rating);
+
+        return 0;
+}
+
+static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
+{
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
+        struct resource *res;
+        int irq, ret;
+        ret = -ENXIO;
+
+        memset(p, 0, sizeof(*p));
+        p->pdev = pdev;
+
+        if (!cfg) {
+                dev_err(&p->pdev->dev, "missing platform data\n");
+                goto err0;
+        }
+
+        platform_set_drvdata(pdev, p);
+
+        res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&p->pdev->dev, "failed to get I/O memory\n");
+                goto err0;
+        }
+
+        irq = platform_get_irq(p->pdev, 0);
+        if (irq < 0) {
+                dev_err(&p->pdev->dev, "failed to get irq\n");
+                goto err0;
+        }
+
+        /* map memory, let mapbase point to our channel */
+        p->mapbase = ioremap_nocache(res->start, resource_size(res));
+        if (p->mapbase == NULL) {
+                pr_err("sh_mtu2: failed to remap I/O memory\n");
+                goto err0;
+        }
+
+        /* setup data for setup_irq() (too early for request_irq()) */
+        p->irqaction.name = cfg->name;
+        p->irqaction.handler = sh_mtu2_interrupt;
+        p->irqaction.dev_id = p;
+        p->irqaction.irq = irq;
+        p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
+        p->irqaction.mask = CPU_MASK_NONE;
+
+        /* get hold of clock */
+        p->clk = clk_get(&p->pdev->dev, cfg->clk);
+        if (IS_ERR(p->clk)) {
+                pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk);
+                ret = PTR_ERR(p->clk);
+                goto err1;
+        }
+
+        return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating);
+ err1:
+        iounmap(p->mapbase);
+ err0:
+        return ret;
+}
+
+static int __devinit sh_mtu2_probe(struct platform_device *pdev)
+{
+        struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
+        int ret;
+
+        if (p) {
+                pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name);
+                return 0;
+        }
+
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (p == NULL) {
+                dev_err(&pdev->dev, "failed to allocate driver data\n");
+                return -ENOMEM;
+        }
+
+        ret = sh_mtu2_setup(p, pdev);
+        if (ret) {
+                kfree(p);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return ret;
+}
+
+static int __devexit sh_mtu2_remove(struct platform_device *pdev)
+{
+        return -EBUSY; /* cannot unregister clockevent */
+}
+
+static struct platform_driver sh_mtu2_device_driver = {
+        .probe          = sh_mtu2_probe,
+        .remove         = __devexit_p(sh_mtu2_remove),
+        .driver         = {
+                .name   = "sh_mtu2",
+        }
+};
+
+static int __init sh_mtu2_init(void)
+{
+        return platform_driver_register(&sh_mtu2_device_driver);
+}
+
+static void __exit sh_mtu2_exit(void)
+{
+        platform_driver_unregister(&sh_mtu2_device_driver);
+}
+
+early_platform_init("earlytimer", &sh_mtu2_device_driver);
+module_init(sh_mtu2_init);
+module_exit(sh_mtu2_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
new file mode 100644
index 000000000000..d6ea4398bf62
--- /dev/null
+++ b/drivers/clocksource/sh_tmu.c
@@ -0,0 +1,461 @@
+/*
+ * SuperH Timer Support - TMU
+ *
+ *  Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/sh_timer.h>
+
+struct sh_tmu_priv {
+        void __iomem *mapbase;
+        struct clk *clk;
+        struct irqaction irqaction;
+        struct platform_device *pdev;
+        unsigned long rate;
+        unsigned long periodic;
+        struct clock_event_device ced;
+        struct clocksource cs;
+};
+
+static DEFINE_SPINLOCK(sh_tmu_lock);
+
+#define TSTR -1 /* shared register */
+#define TCOR  0 /* channel register */
+#define TCNT 1 /* channel register */
+#define TCR 2 /* channel register */
+
+static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        void __iomem *base = p->mapbase;
+        unsigned long offs;
+
+        if (reg_nr == TSTR)
+                return ioread8(base - cfg->channel_offset);
+
+        offs = reg_nr << 2;
+
+        if (reg_nr == TCR)
+                return ioread16(base + offs);
+        else
+                return ioread32(base + offs);
+}
+
+static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
+                                unsigned long value)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        void __iomem *base = p->mapbase;
+        unsigned long offs;
+
+        if (reg_nr == TSTR) {
+                iowrite8(value, base - cfg->channel_offset);
+                return;
+        }
+
+        offs = reg_nr << 2;
+
+        if (reg_nr == TCR)
+                iowrite16(value, base + offs);
+        else
+                iowrite32(value, base + offs);
+}
+
+static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        unsigned long flags, value;
+
+        /* start stop register shared by multiple timer channels */
+        spin_lock_irqsave(&sh_tmu_lock, flags);
+        value = sh_tmu_read(p, TSTR);
+
+        if (start)
+                value |= 1 << cfg->timer_bit;
+        else
+                value &= ~(1 << cfg->timer_bit);
+
+        sh_tmu_write(p, TSTR, value);
+        spin_unlock_irqrestore(&sh_tmu_lock, flags);
+}
+
+static int sh_tmu_enable(struct sh_tmu_priv *p)
+{
+        struct sh_timer_config *cfg = p->pdev->dev.platform_data;
+        int ret;
+
+        /* enable clock */
+        ret = clk_enable(p->clk);
+        if (ret) {
+                pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
+                return ret;
+        }
+
+        /* make sure channel is disabled */
+        sh_tmu_start_stop_ch(p, 0);
+
+        /* maximum timeout */
+        sh_tmu_write(p, TCOR, 0xffffffff);
+        sh_tmu_write(p, TCNT, 0xffffffff);
+
+        /* configure channel to parent clock / 4, irq off */
+        p->rate = clk_get_rate(p->clk) / 4;
+        sh_tmu_write(p, TCR, 0x0000);
+
+        /* enable channel */
+        sh_tmu_start_stop_ch(p, 1);
+
+        return 0;
+}
+
+static void sh_tmu_disable(struct sh_tmu_priv *p)
+{
+        /* disable channel */
+        sh_tmu_start_stop_ch(p, 0);
+
+        /* stop clock */
+        clk_disable(p->clk);
+}
+
+static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
+                            int periodic)
+{
+        /* stop timer */
+        sh_tmu_start_stop_ch(p, 0);
+
+        /* acknowledge interrupt */
+        sh_tmu_read(p, TCR);
+
+        /* enable interrupt */
+        sh_tmu_write(p, TCR, 0x0020);
+
+        /* reload delta value in case of periodic timer */
+        if (periodic)
+                sh_tmu_write(p, TCOR, delta);
+        else
+                sh_tmu_write(p, TCOR, 0);
+
+        sh_tmu_write(p, TCNT, delta);
+
+        /* start timer */
+        sh_tmu_start_stop_ch(p, 1);
+}
+
+static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
+{
+        struct sh_tmu_priv *p = dev_id;
+
+        /* disable or acknowledge interrupt */
+        if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
+                sh_tmu_write(p, TCR, 0x0000);
+        else
+                sh_tmu_write(p, TCR, 0x0020);
+
+        /* notify clockevent layer */
+        p->ced.event_handler(&p->ced);
+        return IRQ_HANDLED;
+}
+
+static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
+{
+        return container_of(cs, struct sh_tmu_priv, cs);
+}
+
+static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
+{
+        struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
+
+        return sh_tmu_read(p, TCNT) ^ 0xffffffff;
+}
+
+static int sh_tmu_clocksource_enable(struct clocksource *cs)
+{
+        struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
+        int ret;
+
+        ret = sh_tmu_enable(p);
+        if (ret)
+                return ret;
+
+        /* TODO: calculate good shift from rate and counter bit width */
+        cs->shift = 10;
+        cs->mult = clocksource_hz2mult(p->rate, cs->shift);
+        return 0;
+}
+
+static void sh_tmu_clocksource_disable(struct clocksource *cs)
+{
+        sh_tmu_disable(cs_to_sh_tmu(cs));
+}
+
+static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
+                                       char *name, unsigned long rating)
+{
+        struct clocksource *cs = &p->cs;
+
+        cs->name = name;
+        cs->rating = rating;
+        cs->read = sh_tmu_clocksource_read;
+        cs->enable = sh_tmu_clocksource_enable;
+        cs->disable = sh_tmu_clocksource_disable;
+        cs->mask = CLOCKSOURCE_MASK(32);
+        cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
+        pr_info("sh_tmu: %s used as clock source\n", cs->name);
+        clocksource_register(cs);
+        return 0;
+}
+
+static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
+{
+        return container_of(ced, struct sh_tmu_priv, ced);
+}
+
+static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
+{
+        struct clock_event_device *ced = &p->ced;
+
+        sh_tmu_enable(p);
+
+        /* TODO: calculate good shift from rate and counter bit width */
+
+        ced->shift = 32;
+        ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
+        ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
+        ced->min_delta_ns = 5000;
+
+        if (periodic) {
+                p->periodic = (p->rate + HZ/2) / HZ;
+                sh_tmu_set_next(p, p->periodic, 1);
+        }
+}
+
+static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *ced)
+{
+        struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
+        int disabled = 0;
+
+        /* deal with old setting first */
+        switch (ced->mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+        case CLOCK_EVT_MODE_ONESHOT:
+                sh_tmu_disable(p);
+                disabled = 1;
+                break;
+        default:
+                break;
+        }
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                pr_info("sh_tmu: %s used for periodic clock events\n",
+                        ced->name);
+                sh_tmu_clock_event_start(p, 1);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                pr_info("sh_tmu: %s used for oneshot clock events\n",
+                        ced->name);
+                sh_tmu_clock_event_start(p, 0);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+                if (!disabled)
+                        sh_tmu_disable(p);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                break;
+        }
+}
+
+static int sh_tmu_clock_event_next(unsigned long delta,
+                                   struct clock_event_device *ced)
+{
+        struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
+
+        BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
+
+        /* program new delta value */
+        sh_tmu_set_next(p, delta, 0);
+        return 0;
+}
+
+static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
+                                       char *name, unsigned long rating)
+{
+        struct clock_event_device *ced = &p->ced;
+        int ret;
+
+        memset(ced, 0, sizeof(*ced));
+
+        ced->name = name;
+        ced->features = CLOCK_EVT_FEAT_PERIODIC;
+        ced->features |= CLOCK_EVT_FEAT_ONESHOT;
+        ced->rating = rating;
+        ced->cpumask = cpumask_of(0);
+        ced->set_next_event = sh_tmu_clock_event_next;
+        ced->set_mode = sh_tmu_clock_event_mode;
+
+        ret = setup_irq(p->irqaction.irq, &p->irqaction);
+        if (ret) {
+                pr_err("sh_tmu: failed to request irq %d\n",
+                       p->irqaction.irq);
+                return;
+        }
+
+        pr_info("sh_tmu: %s used for clock events\n", ced->name);
+        clockevents_register_device(ced);
+}
+
+static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
+                    unsigned long clockevent_rating,
+                    unsigned long clocksource_rating)
+{
+        if (clockevent_rating)
+                sh_tmu_register_clockevent(p, name, clockevent_rating);
+        else if (clocksource_rating)
+                sh_tmu_register_clocksource(p, name, clocksource_rating);
+
+        return 0;
+}
+
+static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
+{
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
+        struct resource *res;
+        int irq, ret;
+        ret = -ENXIO;
+
+        memset(p, 0, sizeof(*p));
+        p->pdev = pdev;
+
+        if (!cfg) {
+                dev_err(&p->pdev->dev, "missing platform data\n");
+                goto err0;
+        }
+
+        platform_set_drvdata(pdev, p);
+
+        res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&p->pdev->dev, "failed to get I/O memory\n");
+                goto err0;
+        }
+
+        irq = platform_get_irq(p->pdev, 0);
+        if (irq < 0) {
+                dev_err(&p->pdev->dev, "failed to get irq\n");
+                goto err0;
+        }
+
+        /* map memory, let mapbase point to our channel */
+        p->mapbase = ioremap_nocache(res->start, resource_size(res));
+        if (p->mapbase == NULL) {
+                pr_err("sh_tmu: failed to remap I/O memory\n");
+                goto err0;
+        }
+
+        /* setup data for setup_irq() (too early for request_irq()) */
+        p->irqaction.name = cfg->name;
+        p->irqaction.handler = sh_tmu_interrupt;
+        p->irqaction.dev_id = p;
+        p->irqaction.irq = irq;
+        p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
+        p->irqaction.mask = CPU_MASK_NONE;
+
+        /* get hold of clock */
+        p->clk = clk_get(&p->pdev->dev, cfg->clk);
+        if (IS_ERR(p->clk)) {
+                pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
+                ret = PTR_ERR(p->clk);
+                goto err1;
+        }
+
+        return sh_tmu_register(p, cfg->name,
+                               cfg->clockevent_rating,
+                               cfg->clocksource_rating);
+ err1:
+        iounmap(p->mapbase);
+ err0:
+        return ret;
+}
+
+static int __devinit sh_tmu_probe(struct platform_device *pdev)
+{
+        struct sh_tmu_priv *p = platform_get_drvdata(pdev);
+        struct sh_timer_config *cfg = pdev->dev.platform_data;
+        int ret;
+
+        if (p) {
+                pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
+                return 0;
+        }
+
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (p == NULL) {
+                dev_err(&pdev->dev, "failed to allocate driver data\n");
+                return -ENOMEM;
+        }
+
+        ret = sh_tmu_setup(p, pdev);
+        if (ret) {
+                kfree(p);
+                platform_set_drvdata(pdev, NULL);
+        }
+        return ret;
+}
+
+static int __devexit sh_tmu_remove(struct platform_device *pdev)
+{
+        return -EBUSY; /* cannot unregister clockevent and clocksource */
+}
+
+static struct platform_driver sh_tmu_device_driver = {
+        .probe          = sh_tmu_probe,
+        .remove         = __devexit_p(sh_tmu_remove),
+        .driver         = {
+                .name   = "sh_tmu",
+        }
+};
+
+static int __init sh_tmu_init(void)
+{
+        return platform_driver_register(&sh_tmu_device_driver);
+}
+
+static void __exit sh_tmu_exit(void)
+{
+        platform_driver_unregister(&sh_tmu_device_driver);
+}
+
+early_platform_init("earlytimer", &sh_tmu_device_driver);
+module_init(sh_tmu_init);
+module_exit(sh_tmu_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("SuperH TMU Timer Driver");
+MODULE_LICENSE("GPL v2");