7 files changed, 288 insertions, 47 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 90420600e1eb..f657a48d20eb 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -32,6 +32,7 @@ config ARMADA_370_XP_TIMER
 
 config MESON6_TIMER
         bool
+        select CLKSRC_MMIO
 
 config ORION_TIMER
         select CLKSRC_OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 756f6f10efa0..fae0435cc23d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
 obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST)   += dummy_timer.o
 obj-$(CONFIG_ARCH_KEYSTONE)             += timer-keystone.o
+obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += timer-integrator-ap.o
 obj-$(CONFIG_CLKSRC_VERSATILE)          += versatile.o
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 43005d4d3348..6a79fc4f900c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -462,7 +462,10 @@ static void __init arch_counter_register(unsigned type)
 
         /* Register the CP15 based counter if we have one */
         if (type & ARCH_CP15_TIMER) {
-                arch_timer_read_counter = arch_counter_get_cntvct;
+                if (arch_timer_use_virtual)
+                        arch_timer_read_counter = arch_counter_get_cntvct;
+                else
+                        arch_timer_read_counter = arch_counter_get_cntpct;
         } else {
                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
 
@@ -702,6 +705,14 @@ static void __init arch_timer_init(struct device_node *np)
         arch_timer_detect_rate(NULL, np);
 
         /*
+         * If we cannot rely on firmware initializing the timer registers then
+         * we should use the physical timers instead.
+         */
+        if (IS_ENABLED(CONFIG_ARM) &&
+            of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
+                        arch_timer_use_virtual = false;
+
+        /*
          * If HYP mode is available, we know that the physical timer
          * has been configured to be accessible from PL1. Use it, so
          * that a guest can use the virtual timer instead.
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 0451e62fac7a..0c8c5e337540 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -43,6 +43,7 @@
 #include <linux/module.h>
 #include <linux/sched_clock.h>
 #include <linux/percpu.h>
+#include <linux/syscore_ops.h>
 
 /*
  * Timer block registers.
@@ -223,6 +224,28 @@ static struct notifier_block armada_370_xp_timer_cpu_nb = {
         .notifier_call = armada_370_xp_timer_cpu_notify,
 };
 
+static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
+
+static int armada_370_xp_timer_suspend(void)
+{
+        timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
+        timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
+        return 0;
+}
+
+static void armada_370_xp_timer_resume(void)
+{
+        writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+        writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+        writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
+        writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
+}
+
+struct syscore_ops armada_370_xp_timer_syscore_ops = {
+        .suspend        = armada_370_xp_timer_suspend,
+        .resume         = armada_370_xp_timer_resume,
+};
+
 static void __init armada_370_xp_timer_common_init(struct device_node *np)
 {
         u32 clr = 0, set = 0;
@@ -285,6 +308,8 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
         /* Immediately configure the timer on the boot CPU */
         if (!res)
                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
+
+        register_syscore_ops(&armada_370_xp_timer_syscore_ops);
 }
 
 static void __init armada_xp_timer_init(struct device_node *np)
@@ -293,6 +318,7 @@ static void __init armada_xp_timer_init(struct device_node *np)
 
         /* The 25Mhz fixed clock is mandatory, and must always be available */
         BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
         timer_clk = clk_get_rate(clk);
 
         armada_370_xp_timer_common_init(np);
@@ -300,11 +326,40 @@ static void __init armada_xp_timer_init(struct device_node *np)
 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
                        armada_xp_timer_init);
 
+static void __init armada_375_timer_init(struct device_node *np)
+{
+        struct clk *clk;
+
+        clk = of_clk_get_by_name(np, "fixed");
+        if (!IS_ERR(clk)) {
+                clk_prepare_enable(clk);
+                timer_clk = clk_get_rate(clk);
+        } else {
+
+                /*
+                 * This fallback is required in order to retain proper
+                 * devicetree backwards compatibility.
+                 */
+                clk = of_clk_get(np, 0);
+
+                /* Must have at least a clock */
+                BUG_ON(IS_ERR(clk));
+                clk_prepare_enable(clk);
+                timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
+                timer25Mhz = false;
+        }
+
+        armada_370_xp_timer_common_init(np);
+}
+CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
+                       armada_375_timer_init);
+
 static void __init armada_370_timer_init(struct device_node *np)
 {
         struct clk *clk = of_clk_get(np, 0);
 
         BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
         timer25Mhz = false;
 
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index d5289098b3df..b5b4d4585c9a 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -262,35 +262,3 @@ static void __init at91sam926x_pit_dt_init(struct device_node *node)
 }
 CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
                        at91sam926x_pit_dt_init);
-
-static void __iomem *pit_base_addr;
-
-void __init at91sam926x_pit_init(int irq)
-{
-        struct pit_data *data;
-
-        data = kzalloc(sizeof(*data), GFP_KERNEL);
-        if (!data)
-                panic(pr_fmt("Unable to allocate memory\n"));
-
-        data->base = pit_base_addr;
-
-        data->mck = clk_get(NULL, "mck");
-        if (IS_ERR(data->mck))
-                panic(pr_fmt("Unable to get mck clk\n"));
-
-        data->irq = irq;
-
-        at91sam926x_pit_common_init(data);
-}
-
-void __init at91sam926x_ioremap_pit(u32 addr)
-{
-        if (of_have_populated_dt())
-                return;
-
-        pit_base_addr = ioremap(addr, 16);
-
-        if (!pit_base_addr)
-                panic(pr_fmt("Impossible to ioremap PIT\n"));
-}
diff --git a/drivers/clocksource/timer-integrator-ap.c b/drivers/clocksource/timer-integrator-ap.c
new file mode 100644
index 000000000000..b9efd30513d5
--- /dev/null
+++ b/drivers/clocksource/timer-integrator-ap.c
@@ -0,0 +1,210 @@
+/*
+ * Integrator/AP timer driver
+ * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
+ * Copyright (c) 2014, Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/sched_clock.h>
+#include <asm/hardware/arm_timer.h>
+
+static void __iomem * sched_clk_base;
+
+static u64 notrace integrator_read_sched_clock(void)
+{
+        return -readl(sched_clk_base + TIMER_VALUE);
+}
+
+static void integrator_clocksource_init(unsigned long inrate,
+                                        void __iomem *base)
+{
+        u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
+        unsigned long rate = inrate;
+
+        if (rate >= 1500000) {
+                rate /= 16;
+                ctrl |= TIMER_CTRL_DIV16;
+        }
+
+        writel(0xffff, base + TIMER_LOAD);
+        writel(ctrl, base + TIMER_CTRL);
+
+        clocksource_mmio_init(base + TIMER_VALUE, "timer2",
+                        rate, 200, 16, clocksource_mmio_readl_down);
+
+        sched_clk_base = base;
+        sched_clock_register(integrator_read_sched_clock, 16, rate);
+}
+
+static unsigned long timer_reload;
+static void __iomem * clkevt_base;
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        /* clear the interrupt */
+        writel(1, clkevt_base + TIMER_INTCLR);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
+{
+        u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
+
+        /* Disable timer */
+        writel(ctrl, clkevt_base + TIMER_CTRL);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* Enable the timer and start the periodic tick */
+                writel(timer_reload, clkevt_base + TIMER_LOAD);
+                ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
+                writel(ctrl, clkevt_base + TIMER_CTRL);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Leave the timer disabled, .set_next_event will enable it */
+                ctrl &= ~TIMER_CTRL_PERIODIC;
+                writel(ctrl, clkevt_base + TIMER_CTRL);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+        default:
+                /* Just leave in disabled state */
+                break;
+        }
+
+}
+
+static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
+{
+        unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
+
+        writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
+        writel(next, clkevt_base + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
+
+        return 0;
+}
+
+static struct clock_event_device integrator_clockevent = {
+        .name           = "timer1",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = clkevt_set_mode,
+        .set_next_event = clkevt_set_next_event,
+        .rating         = 300,
+};
+
+static struct irqaction integrator_timer_irq = {
+        .name           = "timer",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = integrator_timer_interrupt,
+        .dev_id         = &integrator_clockevent,
+};
+
+static void integrator_clockevent_init(unsigned long inrate,
+                                void __iomem *base, int irq)
+{
+        unsigned long rate = inrate;
+        unsigned int ctrl = 0;
+
+        clkevt_base = base;
+        /* Calculate and program a divisor */
+        if (rate > 0x100000 * HZ) {
+                rate /= 256;
+                ctrl |= TIMER_CTRL_DIV256;
+        } else if (rate > 0x10000 * HZ) {
+                rate /= 16;
+                ctrl |= TIMER_CTRL_DIV16;
+        }
+        timer_reload = rate / HZ;
+        writel(ctrl, clkevt_base + TIMER_CTRL);
+
+        setup_irq(irq, &integrator_timer_irq);
+        clockevents_config_and_register(&integrator_clockevent,
+                                        rate,
+                                        1,
+                                        0xffffU);
+}
+
+static void __init integrator_ap_timer_init_of(struct device_node *node)
+{
+        const char *path;
+        void __iomem *base;
+        int err;
+        int irq;
+        struct clk *clk;
+        unsigned long rate;
+        struct device_node *pri_node;
+        struct device_node *sec_node;
+
+        base = of_io_request_and_map(node, 0, "integrator-timer");
+        if (!base)
+                return;
+
+        clk = of_clk_get(node, 0);
+        if (IS_ERR(clk)) {
+                pr_err("No clock for %s\n", node->name);
+                return;
+        }
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+        writel(0, base + TIMER_CTRL);
+
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-primary", &path);
+        if (WARN_ON(err))
+                return;
+        pri_node = of_find_node_by_path(path);
+        err = of_property_read_string(of_aliases,
+                                "arm,timer-secondary", &path);
+        if (WARN_ON(err))
+                return;
+        sec_node = of_find_node_by_path(path);
+
+        if (node == pri_node) {
+                /* The primary timer lacks IRQ, use as clocksource */
+                integrator_clocksource_init(rate, base);
+                return;
+        }
+
+        if (node == sec_node) {
+                /* The secondary timer will drive the clock event */
+                irq = irq_of_parse_and_map(node, 0);
+                integrator_clockevent_init(rate, base, irq);
+                return;
+        }
+
+        pr_info("Timer @%p unused\n", base);
+        clk_disable_unprepare(clk);
+}
+
+CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
+                       integrator_ap_timer_init_of);
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index caf7a2030461..361a789d4bee 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -20,8 +20,6 @@
 #include <linux/of_address.h>
 #include <linux/sched_clock.h>
 
-#define MARCO_CLOCK_FREQ 1000000
-
 #define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
 #define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
 #define SIRFSOC_TIMER_MATCH_0                           0x0018
@@ -40,6 +38,8 @@
 
 #define SIRFSOC_TIMER_REG_CNT 6
 
+static unsigned long marco_timer_rate;
+
 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
         SIRFSOC_TIMER_WATCHDOG_EN,
         SIRFSOC_TIMER_32COUNTER_0_CTRL,
@@ -195,7 +195,7 @@ static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
         ce->rating = 200;
         ce->set_mode = sirfsoc_timer_set_mode;
         ce->set_next_event = sirfsoc_timer_set_next_event;
-        clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60);
+        clockevents_calc_mult_shift(ce, marco_timer_rate, 60);
         ce->max_delta_ns = clockevent_delta2ns(-2, ce);
         ce->min_delta_ns = clockevent_delta2ns(2, ce);
         ce->cpumask = cpumask_of(cpu);
@@ -257,7 +257,6 @@ static void __init sirfsoc_clockevent_init(void)
 /* initialize the kernel jiffy timer source */
 static void __init sirfsoc_marco_timer_init(struct device_node *np)
 {
-        unsigned long rate;
         u32 timer_div;
         struct clk *clk;
 
@@ -266,16 +265,12 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
 
         BUG_ON(clk_prepare_enable(clk));
 
-        rate = clk_get_rate(clk);
-
-        BUG_ON(rate < MARCO_CLOCK_FREQ);
-        BUG_ON(rate % MARCO_CLOCK_FREQ);
+        marco_timer_rate = clk_get_rate(clk);
 
-        /* Initialize the timer dividers */
-        timer_div = rate / MARCO_CLOCK_FREQ - 1;
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
+        /* timer dividers: 0, not divided */
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
 
         /* Initialize timer counters to 0 */
         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
@@ -288,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
         /* Clear all interrupts */
         writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
 
-        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ));
+        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, marco_timer_rate));
 
         sirfsoc_clockevent_init();
 }