5 files changed, 27 insertions, 31 deletions

diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
index 6b5cf02c35c8..82e882028fcf 100644
--- a/drivers/clocksource/acpi_pm.c
+++ b/drivers/clocksource/acpi_pm.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/delay.h>
+#include <linux/async.h>
 #include <asm/io.h>
 
 /*
@@ -179,17 +180,15 @@ static int verify_pmtmr_rate(void)
 /* Number of reads we try to get two different values */
 #define ACPI_PM_READ_CHECKS 10000
 
-static int __init init_acpi_pm_clocksource(void)
+static void __init acpi_pm_clocksource_async(void *unused, async_cookie_t cookie)
 {
         cycle_t value1, value2;
         unsigned int i, j = 0;
 
-        if (!pmtmr_ioport)
-                return -ENODEV;
 
         /* "verify" this timing source: */
         for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
-                udelay(100 * j);
+                usleep_range(100 * j, 100 * j + 100);
                 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
                 for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
                         value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
@@ -203,25 +202,34 @@ static int __init init_acpi_pm_clocksource(void)
                                " 0x%#llx, 0x%#llx - aborting.\n",
                                value1, value2);
                         pmtmr_ioport = 0;
-                        return -EINVAL;
+                        return;
                 }
                 if (i == ACPI_PM_READ_CHECKS) {
                         printk(KERN_INFO "PM-Timer failed consistency check "
                                " (0x%#llx) - aborting.\n", value1);
                         pmtmr_ioport = 0;
-                        return -ENODEV;
+                        return;
                 }
         }
 
         if (verify_pmtmr_rate() != 0){
                 pmtmr_ioport = 0;
-                return -ENODEV;
+                return;
         }
 
-        return clocksource_register_hz(&clocksource_acpi_pm,
+        clocksource_register_hz(&clocksource_acpi_pm,
                                                 PMTMR_TICKS_PER_SEC);
 }
 
+static int __init init_acpi_pm_clocksource(void)
+{
+        if (!pmtmr_ioport)
+                return -ENODEV;
+
+        async_schedule(acpi_pm_clocksource_async, NULL);
+        return 0;
+}
+
 /* We use fs_initcall because we want the PCI fixups to have run
  * but we still need to load before device_initcall
  */
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
index fb6b6d28b60e..c26c369eb9e6 100644
--- a/drivers/clocksource/clksrc-dbx500-prcmu.c
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -52,7 +52,6 @@ static struct clocksource clocksource_dbx500_prcmu = {
         .name           = "dbx500-prcmu-timer",
         .rating         = 300,
         .read           = clksrc_dbx500_prcmu_read,
-        .shift          = 10,
         .mask           = CLOCKSOURCE_MASK(32),
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
@@ -90,7 +89,5 @@ void __init clksrc_dbx500_prcmu_init(void __iomem *base)
         setup_sched_clock(dbx500_prcmu_sched_clock_read,
                          32, RATE_32K);
 #endif
-        clocksource_calc_mult_shift(&clocksource_dbx500_prcmu,
-                                    RATE_32K, SCHED_CLOCK_MIN_WRAP);
-        clocksource_register(&clocksource_dbx500_prcmu);
+        clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
 }
diff --git a/drivers/clocksource/cs5535-clockevt.c b/drivers/clocksource/cs5535-clockevt.c
index b7dab32ce63c..540795cd0760 100644
--- a/drivers/clocksource/cs5535-clockevt.c
+++ b/drivers/clocksource/cs5535-clockevt.c
@@ -100,7 +100,6 @@ static struct clock_event_device cs5535_clockevent = {
         .set_mode = mfgpt_set_mode,
         .set_next_event = mfgpt_next_event,
         .rating = 250,
-        .cpumask = cpu_all_mask,
         .shift = 32
 };
 
@@ -133,7 +132,7 @@ static irqreturn_t mfgpt_tick(int irq, void *dev_id)
 
 static struct irqaction mfgptirq  = {
         .handler = mfgpt_tick,
-        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
+        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
         .name = DRV_NAME,
 };
 
diff --git a/drivers/clocksource/cyclone.c b/drivers/clocksource/cyclone.c
index 72f811f73e9c..9e0998f22885 100644
--- a/drivers/clocksource/cyclone.c
+++ b/drivers/clocksource/cyclone.c
@@ -55,11 +55,11 @@ static int __init init_cyclone_clocksource(void)
         }
         /* even on 64bit systems, this is only 32bits: */
         base = readl(reg);
+        iounmap(reg);
         if (!base) {
                 printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
                 return -ENODEV;
         }
-        iounmap(reg);
 
         /* setup PMCC: */
         offset = base + CYCLONE_PMCC_OFFSET;
diff --git a/drivers/clocksource/scx200_hrt.c b/drivers/clocksource/scx200_hrt.c
index 27f4d9637b62..64f9e8294434 100644
--- a/drivers/clocksource/scx200_hrt.c
+++ b/drivers/clocksource/scx200_hrt.c
@@ -49,9 +49,6 @@ static cycle_t read_hrt(struct clocksource *cs)
         return (cycle_t) inl(scx200_cb_base + SCx200_TIMER_OFFSET);
 }
 
-#define HRT_SHIFT_1     22
-#define HRT_SHIFT_27    26
-
 static struct clocksource cs_hrt = {
         .name           = "scx200_hrt",
         .rating         = 250,
@@ -63,6 +60,7 @@ static struct clocksource cs_hrt = {
 
 static int __init init_hrt_clocksource(void)
 {
+        u32 freq;
         /* Make sure scx200 has initialized the configuration block */
         if (!scx200_cb_present())
                 return -ENODEV;
@@ -71,7 +69,7 @@ static int __init init_hrt_clocksource(void)
         if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
                             SCx200_TIMER_SIZE,
                             "NatSemi SCx200 High-Resolution Timer")) {
-                printk(KERN_WARNING NAME ": unable to lock timer region\n");
+                pr_warn("unable to lock timer region\n");
                 return -ENODEV;
         }
 
@@ -79,19 +77,13 @@ static int __init init_hrt_clocksource(void)
         outb(HR_TMEN | (mhz27 ? HR_TMCLKSEL : 0),
              scx200_cb_base + SCx200_TMCNFG_OFFSET);
 
-        if (mhz27) {
-                cs_hrt.shift = HRT_SHIFT_27;
-                cs_hrt.mult = clocksource_hz2mult((HRT_FREQ + ppm) * 27,
-                                                  cs_hrt.shift);
-        } else {
-                cs_hrt.shift = HRT_SHIFT_1;
-                cs_hrt.mult = clocksource_hz2mult(HRT_FREQ + ppm,
-                                                  cs_hrt.shift);
-        }
-        printk(KERN_INFO "enabling scx200 high-res timer (%s MHz +%d ppm)\n",
-                mhz27 ? "27":"1", ppm);
+        freq = (HRT_FREQ + ppm);
+        if (mhz27)
+                freq *= 27;
+
+        pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
 
-        return clocksource_register(&cs_hrt);
+        return clocksource_register_hz(&cs_hrt, freq);
 }
 
 module_init(init_hrt_clocksource);