diff options
Diffstat (limited to 'drivers/clocksource/exynos_mct.c')
-rw-r--r-- | drivers/clocksource/exynos_mct.c | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 8d6420013a04..ab51bf20a3ed 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c | |||
@@ -153,19 +153,16 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset) | |||
153 | } | 153 | } |
154 | 154 | ||
155 | /* Clocksource handling */ | 155 | /* Clocksource handling */ |
156 | static void exynos4_mct_frc_start(u32 hi, u32 lo) | 156 | static void exynos4_mct_frc_start(void) |
157 | { | 157 | { |
158 | u32 reg; | 158 | u32 reg; |
159 | 159 | ||
160 | exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); | ||
161 | exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); | ||
162 | |||
163 | reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); | 160 | reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
164 | reg |= MCT_G_TCON_START; | 161 | reg |= MCT_G_TCON_START; |
165 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | 162 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); |
166 | } | 163 | } |
167 | 164 | ||
168 | static cycle_t exynos4_frc_read(struct clocksource *cs) | 165 | static cycle_t notrace _exynos4_frc_read(void) |
169 | { | 166 | { |
170 | unsigned int lo, hi; | 167 | unsigned int lo, hi; |
171 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); | 168 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); |
@@ -179,9 +176,14 @@ static cycle_t exynos4_frc_read(struct clocksource *cs) | |||
179 | return ((cycle_t)hi << 32) | lo; | 176 | return ((cycle_t)hi << 32) | lo; |
180 | } | 177 | } |
181 | 178 | ||
179 | static cycle_t exynos4_frc_read(struct clocksource *cs) | ||
180 | { | ||
181 | return _exynos4_frc_read(); | ||
182 | } | ||
183 | |||
182 | static void exynos4_frc_resume(struct clocksource *cs) | 184 | static void exynos4_frc_resume(struct clocksource *cs) |
183 | { | 185 | { |
184 | exynos4_mct_frc_start(0, 0); | 186 | exynos4_mct_frc_start(); |
185 | } | 187 | } |
186 | 188 | ||
187 | struct clocksource mct_frc = { | 189 | struct clocksource mct_frc = { |
@@ -195,12 +197,23 @@ struct clocksource mct_frc = { | |||
195 | 197 | ||
196 | static u64 notrace exynos4_read_sched_clock(void) | 198 | static u64 notrace exynos4_read_sched_clock(void) |
197 | { | 199 | { |
198 | return exynos4_frc_read(&mct_frc); | 200 | return _exynos4_frc_read(); |
201 | } | ||
202 | |||
203 | static struct delay_timer exynos4_delay_timer; | ||
204 | |||
205 | static cycles_t exynos4_read_current_timer(void) | ||
206 | { | ||
207 | return _exynos4_frc_read(); | ||
199 | } | 208 | } |
200 | 209 | ||
201 | static void __init exynos4_clocksource_init(void) | 210 | static void __init exynos4_clocksource_init(void) |
202 | { | 211 | { |
203 | exynos4_mct_frc_start(0, 0); | 212 | exynos4_mct_frc_start(); |
213 | |||
214 | exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; | ||
215 | exynos4_delay_timer.freq = clk_rate; | ||
216 | register_current_timer_delay(&exynos4_delay_timer); | ||
204 | 217 | ||
205 | if (clocksource_register_hz(&mct_frc, clk_rate)) | 218 | if (clocksource_register_hz(&mct_frc, clk_rate)) |
206 | panic("%s: can't register clocksource\n", mct_frc.name); | 219 | panic("%s: can't register clocksource\n", mct_frc.name); |