2 files changed, 10 insertions, 3 deletions

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index bc772f8585d6..848d602efc06 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -660,7 +660,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP4, 16, 1),
         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
-        MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+        MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+                        SRC_TOP4, 28, 1),
 
         MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
                         SRC_TOP5, 0, 1),
@@ -713,7 +714,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP11, 12, 1),
         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
-        MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+        MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+                        SRC_TOP11, 28, 1),
 
         MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
                         SRC_TOP12, 4, 1),
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 09dbe38e183d..62ac8f6e480c 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -16,7 +16,7 @@
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
 
-#define DRA7_DPLL_ABE_DEFFREQ                           361267200
+#define DRA7_DPLL_ABE_DEFFREQ                           180633600
 #define DRA7_DPLL_GMAC_DEFFREQ                          1000000000
 #define DRA7_DPLL_USB_DEFFREQ                           960000000
 
@@ -323,6 +323,11 @@ int __init dra7xx_dt_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+        dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
+        rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
+        if (rc)
+                pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
+
         dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
         rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
         if (rc)