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-rw-r--r--drivers/clk/clk-zynq.c14
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
index 37a30514fd66..b14a25f39255 100644
--- a/drivers/clk/clk-zynq.c
+++ b/drivers/clk/clk-zynq.c
@@ -81,6 +81,7 @@ static void __init zynq_pll_clk_setup(struct device_node *np)
81 if (WARN_ON(ret)) 81 if (WARN_ON(ret))
82 return; 82 return;
83} 83}
84CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
84 85
85struct zynq_periph_clk { 86struct zynq_periph_clk {
86 struct clk_hw hw; 87 struct clk_hw hw;
@@ -187,6 +188,7 @@ static void __init zynq_periph_clk_setup(struct device_node *np)
187 if (WARN_ON(err)) 188 if (WARN_ON(err))
188 return; 189 return;
189} 190}
191CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
190 192
191/* CPU Clock domain is modelled as a mux with 4 children subclks, whose 193/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
192 * derivative rates depend on CLK_621_TRUE 194 * derivative rates depend on CLK_621_TRUE
@@ -366,18 +368,10 @@ static void __init zynq_cpu_clk_setup(struct device_node *np)
366 if (WARN_ON(err)) 368 if (WARN_ON(err))
367 return; 369 return;
368} 370}
369 371CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
370static const __initconst struct of_device_id zynq_clk_match[] = {
371 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
372 { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, },
373 { .compatible = "xlnx,zynq-periph-clock",
374 .data = zynq_periph_clk_setup, },
375 { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, },
376 {}
377};
378 372
379void __init xilinx_zynq_clocks_init(void __iomem *slcr) 373void __init xilinx_zynq_clocks_init(void __iomem *slcr)
380{ 374{
381 slcr_base = slcr; 375 slcr_base = slcr;
382 of_clk_init(zynq_clk_match); 376 of_clk_init(NULL);
383} 377}