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-rw-r--r--drivers/clk/clk-si5351.c12
-rw-r--r--drivers/clk/clk-vt8500.c2
-rw-r--r--drivers/clk/clk.c1
-rw-r--r--drivers/clk/mxs/clk-imx28.c1
-rw-r--r--drivers/clk/samsung/clk-exynos4.c6
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c10
-rw-r--r--drivers/clk/samsung/clk-pll.c5
-rw-r--r--drivers/clk/spear/spear3xx_clock.c2
-rw-r--r--drivers/clk/tegra/clk-tegra20.c11
-rw-r--r--drivers/clk/tegra/clk-tegra30.c11
-rw-r--r--drivers/clk/ux500/clk-sysctrl.c8
-rw-r--r--drivers/clk/ux500/u8500_clk.c2
-rw-r--r--drivers/clk/x86/clk-lpt.c15
13 files changed, 60 insertions, 26 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 892728412e9d..24f553673b72 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
932 unsigned char reg; 932 unsigned char reg;
933 unsigned char rdiv; 933 unsigned char rdiv;
934 934
935 if (hwdata->num > 5) 935 if (hwdata->num <= 5)
936 reg = si5351_msynth_params_address(hwdata->num) + 2; 936 reg = si5351_msynth_params_address(hwdata->num) + 2;
937 else 937 else
938 reg = SI5351_CLK6_7_OUTPUT_DIVIDER; 938 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
1477 return -EINVAL; 1477 return -EINVAL;
1478 } 1478 }
1479 drvdata->onecell.clks[n] = clk; 1479 drvdata->onecell.clks[n] = clk;
1480
1481 /* set initial clkout rate */
1482 if (pdata->clkout[n].rate != 0) {
1483 int ret;
1484 ret = clk_set_rate(clk, pdata->clkout[n].rate);
1485 if (ret != 0) {
1486 dev_err(&client->dev, "Cannot set rate : %d\n",
1487 ret);
1488 }
1489 }
1480 } 1490 }
1481 1491
1482 ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get, 1492 ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688afa8e..553ac35bcc91 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
183 writel(divisor, cdev->div_reg); 183 writel(divisor, cdev->div_reg);
184 vt8500_pmc_wait_busy(); 184 vt8500_pmc_wait_busy();
185 185
186 spin_lock_irqsave(cdev->lock, flags); 186 spin_unlock_irqrestore(cdev->lock, flags);
187 187
188 return 0; 188 return 0;
189} 189}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 934cfd18f72d..1144e8c7579d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1955,6 +1955,7 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
1955 /* XXX the notifier code should handle this better */ 1955 /* XXX the notifier code should handle this better */
1956 if (!cn->notifier_head.head) { 1956 if (!cn->notifier_head.head) {
1957 srcu_cleanup_notifier_head(&cn->notifier_head); 1957 srcu_cleanup_notifier_head(&cn->notifier_head);
1958 list_del(&cn->node);
1958 kfree(cn); 1959 kfree(cn);
1959 } 1960 }
1960 1961
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index d0e5eed146de..4faf0afc44cd 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/clk/mxs.h>
13#include <linux/clkdev.h> 14#include <linux/clkdev.h>
14#include <linux/err.h> 15#include <linux/err.h>
15#include <linux/init.h> 16#include <linux/init.h>
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e69d034..3c1f88868f29 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
791 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 791 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
792 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 792 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
793 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 793 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
794 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 794 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
795 CLK_IGNORE_UNUSED, 0),
795 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
796 GATE(smmu_rotator, "smmu_rotator", "aclk200", 797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
797 E4210_GATE_IP_IMAGE, 4, 0, 0), 798 E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
819 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
820 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
821 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
822 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0), 823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
824 CLK_IGNORE_UNUSED, 0),
823 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 825 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
824 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 826 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
825 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 827 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75924a8..22d7699e7ced 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -155,7 +155,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
155 155
156/* list of all parent clock list */ 156/* list of all parent clock list */
157PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 157PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
158PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; 158PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
159PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 159PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
160PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 160PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
161PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 161PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
@@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
208}; 208};
209 209
210struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 210struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
211 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 211 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
212 MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 212 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
213 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 213 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
214 MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), 214 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
215 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 215 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
216 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 216 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
217 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 217 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
@@ -378,7 +378,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
378 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0), 378 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
379 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0), 379 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
380 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0), 380 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
381 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0), 381 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
382 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0), 382 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
383 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0), 383 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
384 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0), 384 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6be116..362f12dcd944 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -111,7 +111,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate) 111 unsigned long parent_rate)
112{ 112{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw); 113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
114 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 114 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
115 s16 kdiv;
115 u64 fvco = parent_rate; 116 u64 fvco = parent_rate;
116 117
117 pll_con0 = __raw_readl(pll->con_reg); 118 pll_con0 = __raw_readl(pll->con_reg);
@@ -119,7 +120,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
119 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 120 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
120 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 121 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
121 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 122 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
122 kdiv = pll_con1 & PLL36XX_KDIV_MASK; 123 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
123 124
124 fvco *= (mdiv << 16) + kdiv; 125 fvco *= (mdiv << 16) + kdiv;
125 do_div(fvco, (pdiv << sdiv)); 126 do_div(fvco, (pdiv << sdiv));
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index f9ec43fd1320..080c3c5e33f6 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -369,7 +369,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
369 clk_register_clkdev(clk, NULL, "60100000.serial"); 369 clk_register_clkdev(clk, NULL, "60100000.serial");
370} 370}
371#else 371#else
372static inline void spear320_clk_init(void) { } 372static inline void spear320_clk_init(void __iomem *soc_config_base) { }
373#endif 373#endif
374 374
375void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) 375void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 8292a00c3de9..075db0c99edb 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void)
872 struct clk *clk; 872 struct clk *clk;
873 int i; 873 int i;
874 874
875 /* ac97 */
876 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
877 TEGRA_PERIPH_ON_APB,
878 clk_base, 0, 3, &periph_l_regs,
879 periph_clk_enb_refcnt);
880 clk_register_clkdev(clk, NULL, "tegra20-ac97");
881 clks[ac97] = clk;
882
875 /* apbdma */ 883 /* apbdma */
876 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 884 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
877 0, 34, &periph_h_regs, 885 0, 34, &periph_h_regs,
@@ -1234,9 +1242,6 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1234 {uartc, pll_p, 0, 0}, 1242 {uartc, pll_p, 0, 0},
1235 {uartd, pll_p, 0, 0}, 1243 {uartd, pll_p, 0, 0},
1236 {uarte, pll_p, 0, 0}, 1244 {uarte, pll_p, 0, 0},
1237 {usbd, clk_max, 12000000, 0},
1238 {usb2, clk_max, 12000000, 0},
1239 {usb3, clk_max, 12000000, 0},
1240 {pll_a, clk_max, 56448000, 1}, 1245 {pll_a, clk_max, 56448000, 1},
1241 {pll_a_out0, clk_max, 11289600, 1}, 1246 {pll_a_out0, clk_max, 11289600, 1},
1242 {cdev1, clk_max, 0, 1}, 1247 {cdev1, clk_max, 0, 1},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c6921f538e28..ba99e3844106 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1598,6 +1598,12 @@ static void __init tegra30_periph_clk_init(void)
1598 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1598 clk_register_clkdev(clk, "afi", "tegra-pcie");
1599 clks[afi] = clk; 1599 clks[afi] = clk;
1600 1600
1601 /* pciex */
1602 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1603 74, &periph_u_regs, periph_clk_enb_refcnt);
1604 clk_register_clkdev(clk, "pciex", "tegra-pcie");
1605 clks[pciex] = clk;
1606
1601 /* kfuse */ 1607 /* kfuse */
1602 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1608 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1603 TEGRA_PERIPH_ON_APB, 1609 TEGRA_PERIPH_ON_APB,
@@ -1716,11 +1722,6 @@ static void __init tegra30_fixed_clk_init(void)
1716 1, 0, &cml_lock); 1722 1, 0, &cml_lock);
1717 clk_register_clkdev(clk, "cml1", NULL); 1723 clk_register_clkdev(clk, "cml1", NULL);
1718 clks[cml1] = clk; 1724 clks[cml1] = clk;
1719
1720 /* pciex */
1721 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1722 clk_register_clkdev(clk, "pciex", NULL);
1723 clks[pciex] = clk;
1724} 1725}
1725 1726
1726static void __init tegra30_osc_clk_init(void) 1727static void __init tegra30_osc_clk_init(void)
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index bc7e9bde792b..e364c9d4aa60 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
145 return ERR_PTR(-ENOMEM); 145 return ERR_PTR(-ENOMEM);
146 } 146 }
147 147
148 for (i = 0; i < num_parents; i++) { 148 /* set main clock registers */
149 clk->reg_sel[0] = reg_sel[0];
150 clk->reg_bits[0] = reg_bits[0];
151 clk->reg_mask[0] = reg_mask[0];
152
153 /* handle clocks with more than one parent */
154 for (i = 1; i < num_parents; i++) {
149 clk->reg_sel[i] = reg_sel[i]; 155 clk->reg_sel[i] = reg_sel[i];
150 clk->reg_bits[i] = reg_bits[i]; 156 clk->reg_bits[i] = reg_bits[i];
151 clk->reg_mask[i] = reg_mask[i]; 157 clk->reg_mask[i] = reg_mask[i];
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0b4f35a5ffc2..80069c370a47 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, 325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
326 BIT(0), 0); 326 BIT(0), 0);
327 clk_register_clkdev(clk, "fsmc", NULL); 327 clk_register_clkdev(clk, "fsmc", NULL);
328 clk_register_clkdev(clk, NULL, "smsc911x"); 328 clk_register_clkdev(clk, NULL, "smsc911x.0");
329 329
330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, 330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
331 BIT(1), 0); 331 BIT(1), 0);
diff --git a/drivers/clk/x86/clk-lpt.c b/drivers/clk/x86/clk-lpt.c
index 5cf4f4686406..4f45eee9e33b 100644
--- a/drivers/clk/x86/clk-lpt.c
+++ b/drivers/clk/x86/clk-lpt.c
@@ -15,22 +15,29 @@
15#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/platform_data/clk-lpss.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19 20
20#define PRV_CLOCK_PARAMS 0x800 21#define PRV_CLOCK_PARAMS 0x800
21 22
22static int lpt_clk_probe(struct platform_device *pdev) 23static int lpt_clk_probe(struct platform_device *pdev)
23{ 24{
25 struct lpss_clk_data *drvdata;
24 struct clk *clk; 26 struct clk *clk;
25 27
28 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
29 if (!drvdata)
30 return -ENOMEM;
31
26 /* LPSS free running clock */ 32 /* LPSS free running clock */
27 clk = clk_register_fixed_rate(&pdev->dev, "lpss_clk", NULL, CLK_IS_ROOT, 33 drvdata->name = "lpss_clk";
28 100000000); 34 clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL,
35 CLK_IS_ROOT, 100000000);
29 if (IS_ERR(clk)) 36 if (IS_ERR(clk))
30 return PTR_ERR(clk); 37 return PTR_ERR(clk);
31 38
32 /* Shared DMA clock */ 39 drvdata->clk = clk;
33 clk_register_clkdev(clk, "hclk", "INTL9C60.0.auto"); 40 platform_set_drvdata(pdev, drvdata);
34 return 0; 41 return 0;
35} 42}
36 43