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-rw-r--r--drivers/clk/Kconfig12
-rw-r--r--drivers/clk/Makefile5
-rw-r--r--drivers/clk/clk-divider.c68
-rw-r--r--drivers/clk/clk-fixed-factor.c95
-rw-r--r--drivers/clk/clk-fixed-rate.c49
-rw-r--r--drivers/clk/clk-gate.c104
-rw-r--r--drivers/clk/clk-mux.c27
-rw-r--r--drivers/clk/clk.c270
-rw-r--r--drivers/clk/clkdev.c142
-rw-r--r--drivers/clk/spear/Makefile10
-rw-r--r--drivers/clk/spear/clk-aux-synth.c198
-rw-r--r--drivers/clk/spear/clk-frac-synth.c165
-rw-r--r--drivers/clk/spear/clk-gpt-synth.c154
-rw-r--r--drivers/clk/spear/clk-vco-pll.c363
-rw-r--r--drivers/clk/spear/clk.c36
-rw-r--r--drivers/clk/spear/clk.h134
-rw-r--r--drivers/clk/spear/spear1310_clock.c1106
-rw-r--r--drivers/clk/spear/spear1340_clock.c964
-rw-r--r--drivers/clk/spear/spear3xx_clock.c612
-rw-r--r--drivers/clk/spear/spear6xx_clock.c342
20 files changed, 4618 insertions, 238 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 165e1febae53..4864407e3fc4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV
12config COMMON_CLK 12config COMMON_CLK
13 bool 13 bool
14 select HAVE_CLK_PREPARE 14 select HAVE_CLK_PREPARE
15 select CLKDEV_LOOKUP
15 ---help--- 16 ---help---
16 The common clock framework is a single definition of struct 17 The common clock framework is a single definition of struct
17 clk, useful across many platforms, as well as an 18 clk, useful across many platforms, as well as an
@@ -22,17 +23,6 @@ config COMMON_CLK
22menu "Common Clock Framework" 23menu "Common Clock Framework"
23 depends on COMMON_CLK 24 depends on COMMON_CLK
24 25
25config COMMON_CLK_DISABLE_UNUSED
26 bool "Disabled unused clocks at boot"
27 depends on COMMON_CLK
28 ---help---
29 Traverses the entire clock tree and disables any clocks that are
30 enabled in hardware but have not been enabled by any device drivers.
31 This saves power and keeps the software model of the clock in line
32 with reality.
33
34 If in doubt, say "N".
35
36config COMMON_CLK_DEBUG 26config COMMON_CLK_DEBUG
37 bool "DebugFS representation of clock tree" 27 bool "DebugFS representation of clock tree"
38 depends on COMMON_CLK 28 depends on COMMON_CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc11c4b..0f5e03d1ef5c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,7 @@
1 1
2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o 2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ 3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
4 clk-mux.o clk-divider.o 4 clk-mux.o clk-divider.o clk-fixed-factor.o
5
6# SoCs specific
7obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a75ea57..8ea11b444528 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -45,7 +45,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
45 45
46 return parent_rate / div; 46 return parent_rate / div;
47} 47}
48EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
49 48
50/* 49/*
51 * The reverse of DIV_ROUND_UP: The maximum number which 50 * The reverse of DIV_ROUND_UP: The maximum number which
@@ -68,8 +67,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
68 if (divider->flags & CLK_DIVIDER_ONE_BASED) 67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
69 maxdiv--; 68 maxdiv--;
70 69
71 if (!best_parent_rate) { 70 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
72 parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); 71 parent_rate = *best_parent_rate;
73 bestdiv = DIV_ROUND_UP(parent_rate, rate); 72 bestdiv = DIV_ROUND_UP(parent_rate, rate);
74 bestdiv = bestdiv == 0 ? 1 : bestdiv; 73 bestdiv = bestdiv == 0 ? 1 : bestdiv;
75 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 74 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
@@ -109,24 +108,18 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
109 int div; 108 int div;
110 div = clk_divider_bestdiv(hw, rate, prate); 109 div = clk_divider_bestdiv(hw, rate, prate);
111 110
112 if (prate) 111 return *prate / div;
113 return *prate / div;
114 else {
115 unsigned long r;
116 r = __clk_get_rate(__clk_get_parent(hw->clk));
117 return r / div;
118 }
119} 112}
120EXPORT_SYMBOL_GPL(clk_divider_round_rate);
121 113
122static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate) 114static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
115 unsigned long parent_rate)
123{ 116{
124 struct clk_divider *divider = to_clk_divider(hw); 117 struct clk_divider *divider = to_clk_divider(hw);
125 unsigned int div; 118 unsigned int div;
126 unsigned long flags = 0; 119 unsigned long flags = 0;
127 u32 val; 120 u32 val;
128 121
129 div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate; 122 div = parent_rate / rate;
130 123
131 if (!(divider->flags & CLK_DIVIDER_ONE_BASED)) 124 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
132 div--; 125 div--;
@@ -147,15 +140,26 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
147 140
148 return 0; 141 return 0;
149} 142}
150EXPORT_SYMBOL_GPL(clk_divider_set_rate);
151 143
152struct clk_ops clk_divider_ops = { 144const struct clk_ops clk_divider_ops = {
153 .recalc_rate = clk_divider_recalc_rate, 145 .recalc_rate = clk_divider_recalc_rate,
154 .round_rate = clk_divider_round_rate, 146 .round_rate = clk_divider_round_rate,
155 .set_rate = clk_divider_set_rate, 147 .set_rate = clk_divider_set_rate,
156}; 148};
157EXPORT_SYMBOL_GPL(clk_divider_ops); 149EXPORT_SYMBOL_GPL(clk_divider_ops);
158 150
151/**
152 * clk_register_divider - register a divider clock with the clock framework
153 * @dev: device registering this clock
154 * @name: name of this clock
155 * @parent_name: name of clock's parent
156 * @flags: framework-specific flags
157 * @reg: register address to adjust divider
158 * @shift: number of bits to shift the bitfield
159 * @width: width of the bitfield
160 * @clk_divider_flags: divider-specific flags for this clock
161 * @lock: shared register lock for this clock
162 */
159struct clk *clk_register_divider(struct device *dev, const char *name, 163struct clk *clk_register_divider(struct device *dev, const char *name,
160 const char *parent_name, unsigned long flags, 164 const char *parent_name, unsigned long flags,
161 void __iomem *reg, u8 shift, u8 width, 165 void __iomem *reg, u8 shift, u8 width,
@@ -163,38 +167,34 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
163{ 167{
164 struct clk_divider *div; 168 struct clk_divider *div;
165 struct clk *clk; 169 struct clk *clk;
170 struct clk_init_data init;
166 171
172 /* allocate the divider */
167 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); 173 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
168
169 if (!div) { 174 if (!div) {
170 pr_err("%s: could not allocate divider clk\n", __func__); 175 pr_err("%s: could not allocate divider clk\n", __func__);
171 return NULL; 176 return ERR_PTR(-ENOMEM);
172 } 177 }
173 178
179 init.name = name;
180 init.ops = &clk_divider_ops;
181 init.flags = flags;
182 init.parent_names = (parent_name ? &parent_name: NULL);
183 init.num_parents = (parent_name ? 1 : 0);
184
174 /* struct clk_divider assignments */ 185 /* struct clk_divider assignments */
175 div->reg = reg; 186 div->reg = reg;
176 div->shift = shift; 187 div->shift = shift;
177 div->width = width; 188 div->width = width;
178 div->flags = clk_divider_flags; 189 div->flags = clk_divider_flags;
179 div->lock = lock; 190 div->lock = lock;
191 div->hw.init = &init;
180 192
181 if (parent_name) { 193 /* register the clock */
182 div->parent[0] = kstrdup(parent_name, GFP_KERNEL); 194 clk = clk_register(dev, &div->hw);
183 if (!div->parent[0])
184 goto out;
185 }
186
187 clk = clk_register(dev, name,
188 &clk_divider_ops, &div->hw,
189 div->parent,
190 (parent_name ? 1 : 0),
191 flags);
192 if (clk)
193 return clk;
194 195
195out: 196 if (IS_ERR(clk))
196 kfree(div->parent[0]); 197 kfree(div);
197 kfree(div);
198 198
199 return NULL; 199 return clk;
200} 200}
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 000000000000..c8c003e217ad
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Standard functionality for the common clock API.
9 */
10#include <linux/module.h>
11#include <linux/clk-provider.h>
12#include <linux/slab.h>
13#include <linux/err.h>
14
15/*
16 * DOC: basic fixed multiplier and divider clock that cannot gate
17 *
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is fixed. clk->rate = parent->rate / div * mult
22 * parent - fixed parent. No clk_set_parent support
23 */
24
25#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
26
27static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
31
32 return parent_rate * fix->mult / fix->div;
33}
34
35static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
36 unsigned long *prate)
37{
38 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
39
40 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
41 unsigned long best_parent;
42
43 best_parent = (rate / fix->mult) * fix->div;
44 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
45 best_parent);
46 }
47
48 return (*prate / fix->div) * fix->mult;
49}
50
51static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
52 unsigned long parent_rate)
53{
54 return 0;
55}
56
57struct clk_ops clk_fixed_factor_ops = {
58 .round_rate = clk_factor_round_rate,
59 .set_rate = clk_factor_set_rate,
60 .recalc_rate = clk_factor_recalc_rate,
61};
62EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
63
64struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
65 const char *parent_name, unsigned long flags,
66 unsigned int mult, unsigned int div)
67{
68 struct clk_fixed_factor *fix;
69 struct clk_init_data init;
70 struct clk *clk;
71
72 fix = kmalloc(sizeof(*fix), GFP_KERNEL);
73 if (!fix) {
74 pr_err("%s: could not allocate fixed factor clk\n", __func__);
75 return ERR_PTR(-ENOMEM);
76 }
77
78 /* struct clk_fixed_factor assignments */
79 fix->mult = mult;
80 fix->div = div;
81 fix->hw.init = &init;
82
83 init.name = name;
84 init.ops = &clk_fixed_factor_ops;
85 init.flags = flags;
86 init.parent_names = &parent_name;
87 init.num_parents = 1;
88
89 clk = clk_register(dev, &fix->hw);
90
91 if (IS_ERR(clk))
92 kfree(fix);
93
94 return clk;
95}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb5d1bd..cbd246229786 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -32,51 +32,50 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
32{ 32{
33 return to_clk_fixed_rate(hw)->fixed_rate; 33 return to_clk_fixed_rate(hw)->fixed_rate;
34} 34}
35EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
36 35
37struct clk_ops clk_fixed_rate_ops = { 36const struct clk_ops clk_fixed_rate_ops = {
38 .recalc_rate = clk_fixed_rate_recalc_rate, 37 .recalc_rate = clk_fixed_rate_recalc_rate,
39}; 38};
40EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); 39EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
41 40
41/**
42 * clk_register_fixed_rate - register fixed-rate clock with the clock framework
43 * @dev: device that is registering this clock
44 * @name: name of this clock
45 * @parent_name: name of clock's parent
46 * @flags: framework-specific flags
47 * @fixed_rate: non-adjustable clock rate
48 */
42struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 49struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags, 50 const char *parent_name, unsigned long flags,
44 unsigned long fixed_rate) 51 unsigned long fixed_rate)
45{ 52{
46 struct clk_fixed_rate *fixed; 53 struct clk_fixed_rate *fixed;
47 char **parent_names = NULL; 54 struct clk *clk;
48 u8 len; 55 struct clk_init_data init;
49 56
57 /* allocate fixed-rate clock */
50 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); 58 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
51
52 if (!fixed) { 59 if (!fixed) {
53 pr_err("%s: could not allocate fixed clk\n", __func__); 60 pr_err("%s: could not allocate fixed clk\n", __func__);
54 return ERR_PTR(-ENOMEM); 61 return ERR_PTR(-ENOMEM);
55 } 62 }
56 63
64 init.name = name;
65 init.ops = &clk_fixed_rate_ops;
66 init.flags = flags;
67 init.parent_names = (parent_name ? &parent_name: NULL);
68 init.num_parents = (parent_name ? 1 : 0);
69
57 /* struct clk_fixed_rate assignments */ 70 /* struct clk_fixed_rate assignments */
58 fixed->fixed_rate = fixed_rate; 71 fixed->fixed_rate = fixed_rate;
72 fixed->hw.init = &init;
59 73
60 if (parent_name) { 74 /* register the clock */
61 parent_names = kmalloc(sizeof(char *), GFP_KERNEL); 75 clk = clk_register(dev, &fixed->hw);
62
63 if (! parent_names)
64 goto out;
65 76
66 len = sizeof(char) * strlen(parent_name); 77 if (IS_ERR(clk))
67 78 kfree(fixed);
68 parent_names[0] = kmalloc(len, GFP_KERNEL);
69
70 if (!parent_names[0])
71 goto out;
72
73 strncpy(parent_names[0], parent_name, len);
74 }
75 79
76out: 80 return clk;
77 return clk_register(dev, name,
78 &clk_fixed_rate_ops, &fixed->hw,
79 parent_names,
80 (parent_name ? 1 : 0),
81 flags);
82} 81}
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b5902e2ef2fd..578465e04be6 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,32 +28,38 @@
28 28
29#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 29#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
30 30
31static void clk_gate_set_bit(struct clk_gate *gate) 31/*
32 * It works on following logic:
33 *
34 * For enabling clock, enable = 1
35 * set2dis = 1 -> clear bit -> set = 0
36 * set2dis = 0 -> set bit -> set = 1
37 *
38 * For disabling clock, enable = 0
39 * set2dis = 1 -> set bit -> set = 1
40 * set2dis = 0 -> clear bit -> set = 0
41 *
42 * So, result is always: enable xor set2dis.
43 */
44static void clk_gate_endisable(struct clk_hw *hw, int enable)
32{ 45{
33 u32 reg; 46 struct clk_gate *gate = to_clk_gate(hw);
47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
34 unsigned long flags = 0; 48 unsigned long flags = 0;
49 u32 reg;
50
51 set ^= enable;
35 52
36 if (gate->lock) 53 if (gate->lock)
37 spin_lock_irqsave(gate->lock, flags); 54 spin_lock_irqsave(gate->lock, flags);
38 55
39 reg = readl(gate->reg); 56 reg = readl(gate->reg);
40 reg |= BIT(gate->bit_idx);
41 writel(reg, gate->reg);
42
43 if (gate->lock)
44 spin_unlock_irqrestore(gate->lock, flags);
45}
46
47static void clk_gate_clear_bit(struct clk_gate *gate)
48{
49 u32 reg;
50 unsigned long flags = 0;
51 57
52 if (gate->lock) 58 if (set)
53 spin_lock_irqsave(gate->lock, flags); 59 reg |= BIT(gate->bit_idx);
60 else
61 reg &= ~BIT(gate->bit_idx);
54 62
55 reg = readl(gate->reg);
56 reg &= ~BIT(gate->bit_idx);
57 writel(reg, gate->reg); 63 writel(reg, gate->reg);
58 64
59 if (gate->lock) 65 if (gate->lock)
@@ -62,27 +68,15 @@ static void clk_gate_clear_bit(struct clk_gate *gate)
62 68
63static int clk_gate_enable(struct clk_hw *hw) 69static int clk_gate_enable(struct clk_hw *hw)
64{ 70{
65 struct clk_gate *gate = to_clk_gate(hw); 71 clk_gate_endisable(hw, 1);
66
67 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
68 clk_gate_clear_bit(gate);
69 else
70 clk_gate_set_bit(gate);
71 72
72 return 0; 73 return 0;
73} 74}
74EXPORT_SYMBOL_GPL(clk_gate_enable);
75 75
76static void clk_gate_disable(struct clk_hw *hw) 76static void clk_gate_disable(struct clk_hw *hw)
77{ 77{
78 struct clk_gate *gate = to_clk_gate(hw); 78 clk_gate_endisable(hw, 0);
79
80 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
81 clk_gate_set_bit(gate);
82 else
83 clk_gate_clear_bit(gate);
84} 79}
85EXPORT_SYMBOL_GPL(clk_gate_disable);
86 80
87static int clk_gate_is_enabled(struct clk_hw *hw) 81static int clk_gate_is_enabled(struct clk_hw *hw)
88{ 82{
@@ -99,15 +93,25 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
99 93
100 return reg ? 1 : 0; 94 return reg ? 1 : 0;
101} 95}
102EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
103 96
104struct clk_ops clk_gate_ops = { 97const struct clk_ops clk_gate_ops = {
105 .enable = clk_gate_enable, 98 .enable = clk_gate_enable,
106 .disable = clk_gate_disable, 99 .disable = clk_gate_disable,
107 .is_enabled = clk_gate_is_enabled, 100 .is_enabled = clk_gate_is_enabled,
108}; 101};
109EXPORT_SYMBOL_GPL(clk_gate_ops); 102EXPORT_SYMBOL_GPL(clk_gate_ops);
110 103
104/**
105 * clk_register_gate - register a gate clock with the clock framework
106 * @dev: device that is registering this clock
107 * @name: name of this clock
108 * @parent_name: name of this clock's parent
109 * @flags: framework-specific flags for this clock
110 * @reg: register address to control gating of this clock
111 * @bit_idx: which bit in the register controls gating of this clock
112 * @clk_gate_flags: gate-specific flags for this clock
113 * @lock: shared register lock for this clock
114 */
111struct clk *clk_register_gate(struct device *dev, const char *name, 115struct clk *clk_register_gate(struct device *dev, const char *name,
112 const char *parent_name, unsigned long flags, 116 const char *parent_name, unsigned long flags,
113 void __iomem *reg, u8 bit_idx, 117 void __iomem *reg, u8 bit_idx,
@@ -115,36 +119,32 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
115{ 119{
116 struct clk_gate *gate; 120 struct clk_gate *gate;
117 struct clk *clk; 121 struct clk *clk;
122 struct clk_init_data init;
118 123
124 /* allocate the gate */
119 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 125 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
120
121 if (!gate) { 126 if (!gate) {
122 pr_err("%s: could not allocate gated clk\n", __func__); 127 pr_err("%s: could not allocate gated clk\n", __func__);
123 return NULL; 128 return ERR_PTR(-ENOMEM);
124 } 129 }
125 130
131 init.name = name;
132 init.ops = &clk_gate_ops;
133 init.flags = flags;
134 init.parent_names = (parent_name ? &parent_name: NULL);
135 init.num_parents = (parent_name ? 1 : 0);
136
126 /* struct clk_gate assignments */ 137 /* struct clk_gate assignments */
127 gate->reg = reg; 138 gate->reg = reg;
128 gate->bit_idx = bit_idx; 139 gate->bit_idx = bit_idx;
129 gate->flags = clk_gate_flags; 140 gate->flags = clk_gate_flags;
130 gate->lock = lock; 141 gate->lock = lock;
142 gate->hw.init = &init;
131 143
132 if (parent_name) { 144 clk = clk_register(dev, &gate->hw);
133 gate->parent[0] = kstrdup(parent_name, GFP_KERNEL); 145
134 if (!gate->parent[0]) 146 if (IS_ERR(clk))
135 goto out; 147 kfree(gate);
136 }
137 148
138 clk = clk_register(dev, name, 149 return clk;
139 &clk_gate_ops, &gate->hw,
140 gate->parent,
141 (parent_name ? 1 : 0),
142 flags);
143 if (clk)
144 return clk;
145out:
146 kfree(gate->parent[0]);
147 kfree(gate);
148
149 return NULL;
150} 150}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f41a97..fd36a8ea73d9 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -55,7 +55,6 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
55 55
56 return val; 56 return val;
57} 57}
58EXPORT_SYMBOL_GPL(clk_mux_get_parent);
59 58
60static int clk_mux_set_parent(struct clk_hw *hw, u8 index) 59static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
61{ 60{
@@ -82,35 +81,47 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
82 81
83 return 0; 82 return 0;
84} 83}
85EXPORT_SYMBOL_GPL(clk_mux_set_parent);
86 84
87struct clk_ops clk_mux_ops = { 85const struct clk_ops clk_mux_ops = {
88 .get_parent = clk_mux_get_parent, 86 .get_parent = clk_mux_get_parent,
89 .set_parent = clk_mux_set_parent, 87 .set_parent = clk_mux_set_parent,
90}; 88};
91EXPORT_SYMBOL_GPL(clk_mux_ops); 89EXPORT_SYMBOL_GPL(clk_mux_ops);
92 90
93struct clk *clk_register_mux(struct device *dev, const char *name, 91struct clk *clk_register_mux(struct device *dev, const char *name,
94 char **parent_names, u8 num_parents, unsigned long flags, 92 const char **parent_names, u8 num_parents, unsigned long flags,
95 void __iomem *reg, u8 shift, u8 width, 93 void __iomem *reg, u8 shift, u8 width,
96 u8 clk_mux_flags, spinlock_t *lock) 94 u8 clk_mux_flags, spinlock_t *lock)
97{ 95{
98 struct clk_mux *mux; 96 struct clk_mux *mux;
97 struct clk *clk;
98 struct clk_init_data init;
99 99
100 mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL); 100 /* allocate the mux */
101 101 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
102 if (!mux) { 102 if (!mux) {
103 pr_err("%s: could not allocate mux clk\n", __func__); 103 pr_err("%s: could not allocate mux clk\n", __func__);
104 return ERR_PTR(-ENOMEM); 104 return ERR_PTR(-ENOMEM);
105 } 105 }
106 106
107 init.name = name;
108 init.ops = &clk_mux_ops;
109 init.flags = flags;
110 init.parent_names = parent_names;
111 init.num_parents = num_parents;
112
107 /* struct clk_mux assignments */ 113 /* struct clk_mux assignments */
108 mux->reg = reg; 114 mux->reg = reg;
109 mux->shift = shift; 115 mux->shift = shift;
110 mux->width = width; 116 mux->width = width;
111 mux->flags = clk_mux_flags; 117 mux->flags = clk_mux_flags;
112 mux->lock = lock; 118 mux->lock = lock;
119 mux->hw.init = &init;
120
121 clk = clk_register(dev, &mux->hw);
122
123 if (IS_ERR(clk))
124 kfree(mux);
113 125
114 return clk_register(dev, name, &clk_mux_ops, &mux->hw, 126 return clk;
115 parent_names, num_parents, flags);
116} 127}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59e3e19..e5d5dc13bcfd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -194,9 +194,8 @@ static int __init clk_debug_init(void)
194late_initcall(clk_debug_init); 194late_initcall(clk_debug_init);
195#else 195#else
196static inline int clk_debug_register(struct clk *clk) { return 0; } 196static inline int clk_debug_register(struct clk *clk) { return 0; }
197#endif /* CONFIG_COMMON_CLK_DEBUG */ 197#endif
198 198
199#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
200/* caller must hold prepare_lock */ 199/* caller must hold prepare_lock */
201static void clk_disable_unused_subtree(struct clk *clk) 200static void clk_disable_unused_subtree(struct clk *clk)
202{ 201{
@@ -246,9 +245,6 @@ static int clk_disable_unused(void)
246 return 0; 245 return 0;
247} 246}
248late_initcall(clk_disable_unused); 247late_initcall(clk_disable_unused);
249#else
250static inline int clk_disable_unused(struct clk *clk) { return 0; }
251#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
252 248
253/*** helper functions ***/ 249/*** helper functions ***/
254 250
@@ -287,7 +283,7 @@ unsigned long __clk_get_rate(struct clk *clk)
287 unsigned long ret; 283 unsigned long ret;
288 284
289 if (!clk) { 285 if (!clk) {
290 ret = -EINVAL; 286 ret = 0;
291 goto out; 287 goto out;
292 } 288 }
293 289
@@ -297,7 +293,7 @@ unsigned long __clk_get_rate(struct clk *clk)
297 goto out; 293 goto out;
298 294
299 if (!clk->parent) 295 if (!clk->parent)
300 ret = -ENODEV; 296 ret = 0;
301 297
302out: 298out:
303 return ret; 299 return ret;
@@ -562,7 +558,7 @@ EXPORT_SYMBOL_GPL(clk_enable);
562 * @clk: the clk whose rate is being returned 558 * @clk: the clk whose rate is being returned
563 * 559 *
564 * Simply returns the cached rate of the clk. Does not query the hardware. If 560 * Simply returns the cached rate of the clk. Does not query the hardware. If
565 * clk is NULL then returns -EINVAL. 561 * clk is NULL then returns 0.
566 */ 562 */
567unsigned long clk_get_rate(struct clk *clk) 563unsigned long clk_get_rate(struct clk *clk)
568{ 564{
@@ -584,18 +580,22 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
584 */ 580 */
585unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) 581unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
586{ 582{
587 unsigned long unused; 583 unsigned long parent_rate = 0;
588 584
589 if (!clk) 585 if (!clk)
590 return -EINVAL; 586 return -EINVAL;
591 587
592 if (!clk->ops->round_rate) 588 if (!clk->ops->round_rate) {
593 return clk->rate; 589 if (clk->flags & CLK_SET_RATE_PARENT)
590 return __clk_round_rate(clk->parent, rate);
591 else
592 return clk->rate;
593 }
594 594
595 if (clk->flags & CLK_SET_RATE_PARENT) 595 if (clk->parent)
596 return clk->ops->round_rate(clk->hw, rate, &unused); 596 parent_rate = clk->parent->rate;
597 else 597
598 return clk->ops->round_rate(clk->hw, rate, NULL); 598 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
599} 599}
600 600
601/** 601/**
@@ -765,25 +765,41 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
765static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) 765static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
766{ 766{
767 struct clk *top = clk; 767 struct clk *top = clk;
768 unsigned long best_parent_rate = clk->parent->rate; 768 unsigned long best_parent_rate = 0;
769 unsigned long new_rate; 769 unsigned long new_rate;
770 770
771 if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) { 771 /* sanity */
772 clk->new_rate = clk->rate; 772 if (IS_ERR_OR_NULL(clk))
773 return NULL; 773 return NULL;
774
775 /* save parent rate, if it exists */
776 if (clk->parent)
777 best_parent_rate = clk->parent->rate;
778
779 /* never propagate up to the parent */
780 if (!(clk->flags & CLK_SET_RATE_PARENT)) {
781 if (!clk->ops->round_rate) {
782 clk->new_rate = clk->rate;
783 return NULL;
784 }
785 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
786 goto out;
774 } 787 }
775 788
776 if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) { 789 /* need clk->parent from here on out */
790 if (!clk->parent) {
791 pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
792 return NULL;
793 }
794
795 if (!clk->ops->round_rate) {
777 top = clk_calc_new_rates(clk->parent, rate); 796 top = clk_calc_new_rates(clk->parent, rate);
778 new_rate = clk->new_rate = clk->parent->new_rate; 797 new_rate = clk->parent->new_rate;
779 798
780 goto out; 799 goto out;
781 } 800 }
782 801
783 if (clk->flags & CLK_SET_RATE_PARENT) 802 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
784 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
785 else
786 new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
787 803
788 if (best_parent_rate != clk->parent->rate) { 804 if (best_parent_rate != clk->parent->rate) {
789 top = clk_calc_new_rates(clk->parent, best_parent_rate); 805 top = clk_calc_new_rates(clk->parent, best_parent_rate);
@@ -839,7 +855,7 @@ static void clk_change_rate(struct clk *clk)
839 old_rate = clk->rate; 855 old_rate = clk->rate;
840 856
841 if (clk->ops->set_rate) 857 if (clk->ops->set_rate)
842 clk->ops->set_rate(clk->hw, clk->new_rate); 858 clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate);
843 859
844 if (clk->ops->recalc_rate) 860 if (clk->ops->recalc_rate)
845 clk->rate = clk->ops->recalc_rate(clk->hw, 861 clk->rate = clk->ops->recalc_rate(clk->hw,
@@ -859,38 +875,19 @@ static void clk_change_rate(struct clk *clk)
859 * @clk: the clk whose rate is being changed 875 * @clk: the clk whose rate is being changed
860 * @rate: the new rate for clk 876 * @rate: the new rate for clk
861 * 877 *
862 * In the simplest case clk_set_rate will only change the rate of clk. 878 * In the simplest case clk_set_rate will only adjust the rate of clk.
863 * 879 *
864 * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call 880 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
865 * will fail; only when the clk is disabled will it be able to change 881 * propagate up to clk's parent; whether or not this happens depends on the
866 * its rate. 882 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
883 * after calling .round_rate then upstream parent propagation is ignored. If
884 * *parent_rate comes back with a new rate for clk's parent then we propagate
885 * up to clk's parent and set it's rate. Upward propagation will continue
886 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
887 * .round_rate stops requesting changes to clk's parent_rate.
867 * 888 *
868 * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to 889 * Rate changes are accomplished via tree traversal that also recalculates the
869 * recursively propagate up to clk's parent; whether or not this happens 890 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
870 * depends on the outcome of clk's .round_rate implementation. If
871 * *parent_rate is 0 after calling .round_rate then upstream parent
872 * propagation is ignored. If *parent_rate comes back with a new rate
873 * for clk's parent then we propagate up to clk's parent and set it's
874 * rate. Upward propagation will continue until either a clk does not
875 * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
876 * changes to clk's parent_rate. If there is a failure during upstream
877 * propagation then clk_set_rate will unwind and restore each clk's rate
878 * that had been successfully changed. Afterwards a rate change abort
879 * notification will be propagated downstream, starting from the clk
880 * that failed.
881 *
882 * At the end of all of the rate setting, clk_set_rate internally calls
883 * __clk_recalc_rates and propagates the rate changes downstream,
884 * starting from the highest clk whose rate was changed. This has the
885 * added benefit of propagating post-rate change notifiers.
886 *
887 * Note that while post-rate change and rate change abort notifications
888 * are guaranteed to be sent to a clk only once per call to
889 * clk_set_rate, pre-change notifications will be sent for every clk
890 * whose rate is changed. Stacking pre-change notifications is noisy
891 * for the drivers subscribed to them, but this allows drivers to react
892 * to intermediate clk rate changes up until the point where the final
893 * rate is achieved at the end of upstream propagation.
894 * 891 *
895 * Returns 0 on success, -EERROR otherwise. 892 * Returns 0 on success, -EERROR otherwise.
896 */ 893 */
@@ -906,6 +903,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
906 if (rate == clk->rate) 903 if (rate == clk->rate)
907 goto out; 904 goto out;
908 905
906 if ((clk->flags & CLK_SET_RATE_GATE) && __clk_is_enabled(clk)) {
907 ret = -EBUSY;
908 goto out;
909 }
910
909 /* calculate new rates and get the topmost changed clock */ 911 /* calculate new rates and get the topmost changed clock */
910 top = clk_calc_new_rates(clk, rate); 912 top = clk_calc_new_rates(clk, rate);
911 if (!top) { 913 if (!top) {
@@ -1175,40 +1177,41 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
1175 * 1177 *
1176 * Initializes the lists in struct clk, queries the hardware for the 1178 * Initializes the lists in struct clk, queries the hardware for the
1177 * parent and rate and sets them both. 1179 * parent and rate and sets them both.
1178 *
1179 * Any struct clk passed into __clk_init must have the following members
1180 * populated:
1181 * .name
1182 * .ops
1183 * .hw
1184 * .parent_names
1185 * .num_parents
1186 * .flags
1187 *
1188 * Essentially, everything that would normally be passed into clk_register is
1189 * assumed to be initialized already in __clk_init. The other members may be
1190 * populated, but are optional.
1191 *
1192 * __clk_init is only exposed via clk-private.h and is intended for use with
1193 * very large numbers of clocks that need to be statically initialized. It is
1194 * a layering violation to include clk-private.h from any code which implements
1195 * a clock's .ops; as such any statically initialized clock data MUST be in a
1196 * separate C file from the logic that implements it's operations.
1197 */ 1180 */
1198void __clk_init(struct device *dev, struct clk *clk) 1181int __clk_init(struct device *dev, struct clk *clk)
1199{ 1182{
1200 int i; 1183 int i, ret = 0;
1201 struct clk *orphan; 1184 struct clk *orphan;
1202 struct hlist_node *tmp, *tmp2; 1185 struct hlist_node *tmp, *tmp2;
1203 1186
1204 if (!clk) 1187 if (!clk)
1205 return; 1188 return -EINVAL;
1206 1189
1207 mutex_lock(&prepare_lock); 1190 mutex_lock(&prepare_lock);
1208 1191
1209 /* check to see if a clock with this name is already registered */ 1192 /* check to see if a clock with this name is already registered */
1210 if (__clk_lookup(clk->name)) 1193 if (__clk_lookup(clk->name)) {
1194 pr_debug("%s: clk %s already initialized\n",
1195 __func__, clk->name);
1196 ret = -EEXIST;
1197 goto out;
1198 }
1199
1200 /* check that clk_ops are sane. See Documentation/clk.txt */
1201 if (clk->ops->set_rate &&
1202 !(clk->ops->round_rate && clk->ops->recalc_rate)) {
1203 pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
1204 __func__, clk->name);
1205 ret = -EINVAL;
1211 goto out; 1206 goto out;
1207 }
1208
1209 if (clk->ops->set_parent && !clk->ops->get_parent) {
1210 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
1211 __func__, clk->name);
1212 ret = -EINVAL;
1213 goto out;
1214 }
1212 1215
1213 /* throw a WARN if any entries in parent_names are NULL */ 1216 /* throw a WARN if any entries in parent_names are NULL */
1214 for (i = 0; i < clk->num_parents; i++) 1217 for (i = 0; i < clk->num_parents; i++)
@@ -1302,45 +1305,118 @@ void __clk_init(struct device *dev, struct clk *clk)
1302out: 1305out:
1303 mutex_unlock(&prepare_lock); 1306 mutex_unlock(&prepare_lock);
1304 1307
1305 return; 1308 return ret;
1306} 1309}
1307 1310
1308/** 1311/**
1312 * __clk_register - register a clock and return a cookie.
1313 *
1314 * Same as clk_register, except that the .clk field inside hw shall point to a
1315 * preallocated (generally statically allocated) struct clk. None of the fields
1316 * of the struct clk need to be initialized.
1317 *
1318 * The data pointed to by .init and .clk field shall NOT be marked as init
1319 * data.
1320 *
1321 * __clk_register is only exposed via clk-private.h and is intended for use with
1322 * very large numbers of clocks that need to be statically initialized. It is
1323 * a layering violation to include clk-private.h from any code which implements
1324 * a clock's .ops; as such any statically initialized clock data MUST be in a
1325 * separate C file from the logic that implements it's operations. Returns 0
1326 * on success, otherwise an error code.
1327 */
1328struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
1329{
1330 int ret;
1331 struct clk *clk;
1332
1333 clk = hw->clk;
1334 clk->name = hw->init->name;
1335 clk->ops = hw->init->ops;
1336 clk->hw = hw;
1337 clk->flags = hw->init->flags;
1338 clk->parent_names = hw->init->parent_names;
1339 clk->num_parents = hw->init->num_parents;
1340
1341 ret = __clk_init(dev, clk);
1342 if (ret)
1343 return ERR_PTR(ret);
1344
1345 return clk;
1346}
1347EXPORT_SYMBOL_GPL(__clk_register);
1348
1349/**
1309 * clk_register - allocate a new clock, register it and return an opaque cookie 1350 * clk_register - allocate a new clock, register it and return an opaque cookie
1310 * @dev: device that is registering this clock 1351 * @dev: device that is registering this clock
1311 * @name: clock name
1312 * @ops: operations this clock supports
1313 * @hw: link to hardware-specific clock data 1352 * @hw: link to hardware-specific clock data
1314 * @parent_names: array of string names for all possible parents
1315 * @num_parents: number of possible parents
1316 * @flags: framework-level hints and quirks
1317 * 1353 *
1318 * clk_register is the primary interface for populating the clock tree with new 1354 * clk_register is the primary interface for populating the clock tree with new
1319 * clock nodes. It returns a pointer to the newly allocated struct clk which 1355 * clock nodes. It returns a pointer to the newly allocated struct clk which
1320 * cannot be dereferenced by driver code but may be used in conjuction with the 1356 * cannot be dereferenced by driver code but may be used in conjuction with the
1321 * rest of the clock API. 1357 * rest of the clock API. In the event of an error clk_register will return an
1358 * error code; drivers must test for an error code after calling clk_register.
1322 */ 1359 */
1323struct clk *clk_register(struct device *dev, const char *name, 1360struct clk *clk_register(struct device *dev, struct clk_hw *hw)
1324 const struct clk_ops *ops, struct clk_hw *hw,
1325 char **parent_names, u8 num_parents, unsigned long flags)
1326{ 1361{
1362 int i, ret;
1327 struct clk *clk; 1363 struct clk *clk;
1328 1364
1329 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 1365 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
1330 if (!clk) 1366 if (!clk) {
1331 return NULL; 1367 pr_err("%s: could not allocate clk\n", __func__);
1368 ret = -ENOMEM;
1369 goto fail_out;
1370 }
1332 1371
1333 clk->name = name; 1372 clk->name = kstrdup(hw->init->name, GFP_KERNEL);
1334 clk->ops = ops; 1373 if (!clk->name) {
1374 pr_err("%s: could not allocate clk->name\n", __func__);
1375 ret = -ENOMEM;
1376 goto fail_name;
1377 }
1378 clk->ops = hw->init->ops;
1335 clk->hw = hw; 1379 clk->hw = hw;
1336 clk->flags = flags; 1380 clk->flags = hw->init->flags;
1337 clk->parent_names = parent_names; 1381 clk->num_parents = hw->init->num_parents;
1338 clk->num_parents = num_parents;
1339 hw->clk = clk; 1382 hw->clk = clk;
1340 1383
1341 __clk_init(dev, clk); 1384 /* allocate local copy in case parent_names is __initdata */
1385 clk->parent_names = kzalloc((sizeof(char*) * clk->num_parents),
1386 GFP_KERNEL);
1342 1387
1343 return clk; 1388 if (!clk->parent_names) {
1389 pr_err("%s: could not allocate clk->parent_names\n", __func__);
1390 ret = -ENOMEM;
1391 goto fail_parent_names;
1392 }
1393
1394
1395 /* copy each string name in case parent_names is __initdata */
1396 for (i = 0; i < clk->num_parents; i++) {
1397 clk->parent_names[i] = kstrdup(hw->init->parent_names[i],
1398 GFP_KERNEL);
1399 if (!clk->parent_names[i]) {
1400 pr_err("%s: could not copy parent_names\n", __func__);
1401 ret = -ENOMEM;
1402 goto fail_parent_names_copy;
1403 }
1404 }
1405
1406 ret = __clk_init(dev, clk);
1407 if (!ret)
1408 return clk;
1409
1410fail_parent_names_copy:
1411 while (--i >= 0)
1412 kfree(clk->parent_names[i]);
1413 kfree(clk->parent_names);
1414fail_parent_names:
1415 kfree(clk->name);
1416fail_name:
1417 kfree(clk);
1418fail_out:
1419 return ERR_PTR(ret);
1344} 1420}
1345EXPORT_SYMBOL_GPL(clk_register); 1421EXPORT_SYMBOL_GPL(clk_register);
1346 1422
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f64ae0..c535cf8c5770 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -35,7 +35,12 @@ static DEFINE_MUTEX(clocks_mutex);
35static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) 35static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
36{ 36{
37 struct clk_lookup *p, *cl = NULL; 37 struct clk_lookup *p, *cl = NULL;
38 int match, best = 0; 38 int match, best_found = 0, best_possible = 0;
39
40 if (dev_id)
41 best_possible += 2;
42 if (con_id)
43 best_possible += 1;
39 44
40 list_for_each_entry(p, &clocks, node) { 45 list_for_each_entry(p, &clocks, node) {
41 match = 0; 46 match = 0;
@@ -50,10 +55,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
50 match += 1; 55 match += 1;
51 } 56 }
52 57
53 if (match > best) { 58 if (match > best_found) {
54 cl = p; 59 cl = p;
55 if (match != 3) 60 if (match != best_possible)
56 best = match; 61 best_found = match;
57 else 62 else
58 break; 63 break;
59 } 64 }
@@ -89,6 +94,51 @@ void clk_put(struct clk *clk)
89} 94}
90EXPORT_SYMBOL(clk_put); 95EXPORT_SYMBOL(clk_put);
91 96
97static void devm_clk_release(struct device *dev, void *res)
98{
99 clk_put(*(struct clk **)res);
100}
101
102struct clk *devm_clk_get(struct device *dev, const char *id)
103{
104 struct clk **ptr, *clk;
105
106 ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
107 if (!ptr)
108 return ERR_PTR(-ENOMEM);
109
110 clk = clk_get(dev, id);
111 if (!IS_ERR(clk)) {
112 *ptr = clk;
113 devres_add(dev, ptr);
114 } else {
115 devres_free(ptr);
116 }
117
118 return clk;
119}
120EXPORT_SYMBOL(devm_clk_get);
121
122static int devm_clk_match(struct device *dev, void *res, void *data)
123{
124 struct clk **c = res;
125 if (!c || !*c) {
126 WARN_ON(!c || !*c);
127 return 0;
128 }
129 return *c == data;
130}
131
132void devm_clk_put(struct device *dev, struct clk *clk)
133{
134 int ret;
135
136 ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk);
137
138 WARN_ON(ret);
139}
140EXPORT_SYMBOL(devm_clk_put);
141
92void clkdev_add(struct clk_lookup *cl) 142void clkdev_add(struct clk_lookup *cl)
93{ 143{
94 mutex_lock(&clocks_mutex); 144 mutex_lock(&clocks_mutex);
@@ -116,8 +166,9 @@ struct clk_lookup_alloc {
116 char con_id[MAX_CON_ID]; 166 char con_id[MAX_CON_ID];
117}; 167};
118 168
119struct clk_lookup * __init_refok 169static struct clk_lookup * __init_refok
120clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) 170vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt,
171 va_list ap)
121{ 172{
122 struct clk_lookup_alloc *cla; 173 struct clk_lookup_alloc *cla;
123 174
@@ -132,16 +183,25 @@ clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
132 } 183 }
133 184
134 if (dev_fmt) { 185 if (dev_fmt) {
135 va_list ap;
136
137 va_start(ap, dev_fmt);
138 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); 186 vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
139 cla->cl.dev_id = cla->dev_id; 187 cla->cl.dev_id = cla->dev_id;
140 va_end(ap);
141 } 188 }
142 189
143 return &cla->cl; 190 return &cla->cl;
144} 191}
192
193struct clk_lookup * __init_refok
194clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
195{
196 struct clk_lookup *cl;
197 va_list ap;
198
199 va_start(ap, dev_fmt);
200 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
201 va_end(ap);
202
203 return cl;
204}
145EXPORT_SYMBOL(clkdev_alloc); 205EXPORT_SYMBOL(clkdev_alloc);
146 206
147int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, 207int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
@@ -173,3 +233,65 @@ void clkdev_drop(struct clk_lookup *cl)
173 kfree(cl); 233 kfree(cl);
174} 234}
175EXPORT_SYMBOL(clkdev_drop); 235EXPORT_SYMBOL(clkdev_drop);
236
237/**
238 * clk_register_clkdev - register one clock lookup for a struct clk
239 * @clk: struct clk to associate with all clk_lookups
240 * @con_id: connection ID string on device
241 * @dev_id: format string describing device name
242 *
243 * con_id or dev_id may be NULL as a wildcard, just as in the rest of
244 * clkdev.
245 *
246 * To make things easier for mass registration, we detect error clks
247 * from a previous clk_register() call, and return the error code for
248 * those. This is to permit this function to be called immediately
249 * after clk_register().
250 */
251int clk_register_clkdev(struct clk *clk, const char *con_id,
252 const char *dev_fmt, ...)
253{
254 struct clk_lookup *cl;
255 va_list ap;
256
257 if (IS_ERR(clk))
258 return PTR_ERR(clk);
259
260 va_start(ap, dev_fmt);
261 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
262 va_end(ap);
263
264 if (!cl)
265 return -ENOMEM;
266
267 clkdev_add(cl);
268
269 return 0;
270}
271
272/**
273 * clk_register_clkdevs - register a set of clk_lookup for a struct clk
274 * @clk: struct clk to associate with all clk_lookups
275 * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized
276 * @num: number of clk_lookup structures to register
277 *
278 * To make things easier for mass registration, we detect error clks
279 * from a previous clk_register() call, and return the error code for
280 * those. This is to permit this function to be called immediately
281 * after clk_register().
282 */
283int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
284{
285 unsigned i;
286
287 if (IS_ERR(clk))
288 return PTR_ERR(clk);
289
290 for (i = 0; i < num; i++, cl++) {
291 cl->clk = clk;
292 clkdev_add(cl);
293 }
294
295 return 0;
296}
297EXPORT_SYMBOL(clk_register_clkdevs);
diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
new file mode 100644
index 000000000000..cdb425d3b8ee
--- /dev/null
+++ b/drivers/clk/spear/Makefile
@@ -0,0 +1,10 @@
1#
2# SPEAr Clock specific Makefile
3#
4
5obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
6
7obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o
8obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o
9obj-$(CONFIG_MACH_SPEAR1310) += spear1310_clock.o
10obj-$(CONFIG_MACH_SPEAR1340) += spear1340_clock.o
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
new file mode 100644
index 000000000000..af34074e702b
--- /dev/null
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -0,0 +1,198 @@
1/*
2 * Copyright (C) 2012 ST Microelectronics
3 * Viresh Kumar <viresh.kumar@st.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * Auxiliary Synthesizer clock implementation
10 */
11
12#define pr_fmt(fmt) "clk-aux-synth: " fmt
13
14#include <linux/clk-provider.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include "clk.h"
19
20/*
21 * DOC: Auxiliary Synthesizer clock
22 *
23 * Aux synth gives rate for different values of eq, x and y
24 *
25 * Fout from synthesizer can be given from two equations:
26 * Fout1 = (Fin * X/Y)/2 EQ1
27 * Fout2 = Fin * X/Y EQ2
28 */
29
30#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
31
32static struct aux_clk_masks default_aux_masks = {
33 .eq_sel_mask = AUX_EQ_SEL_MASK,
34 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
35 .eq1_mask = AUX_EQ1_SEL,
36 .eq2_mask = AUX_EQ2_SEL,
37 .xscale_sel_mask = AUX_XSCALE_MASK,
38 .xscale_sel_shift = AUX_XSCALE_SHIFT,
39 .yscale_sel_mask = AUX_YSCALE_MASK,
40 .yscale_sel_shift = AUX_YSCALE_SHIFT,
41 .enable_bit = AUX_SYNT_ENB,
42};
43
44static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
45 int index)
46{
47 struct clk_aux *aux = to_clk_aux(hw);
48 struct aux_rate_tbl *rtbl = aux->rtbl;
49 u8 eq = rtbl[index].eq ? 1 : 2;
50
51 return (((prate / 10000) * rtbl[index].xscale) /
52 (rtbl[index].yscale * eq)) * 10000;
53}
54
55static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
56 unsigned long *prate)
57{
58 struct clk_aux *aux = to_clk_aux(hw);
59 int unused;
60
61 return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
62 aux->rtbl_cnt, &unused);
63}
64
65static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
66 unsigned long parent_rate)
67{
68 struct clk_aux *aux = to_clk_aux(hw);
69 unsigned int num = 1, den = 1, val, eqn;
70 unsigned long flags = 0;
71
72 if (aux->lock)
73 spin_lock_irqsave(aux->lock, flags);
74
75 val = readl_relaxed(aux->reg);
76
77 if (aux->lock)
78 spin_unlock_irqrestore(aux->lock, flags);
79
80 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
81 if (eqn == aux->masks->eq1_mask)
82 den = 2;
83
84 /* calculate numerator */
85 num = (val >> aux->masks->xscale_sel_shift) &
86 aux->masks->xscale_sel_mask;
87
88 /* calculate denominator */
89 den *= (val >> aux->masks->yscale_sel_shift) &
90 aux->masks->yscale_sel_mask;
91
92 if (!den)
93 return 0;
94
95 return (((parent_rate / 10000) * num) / den) * 10000;
96}
97
98/* Configures new clock rate of aux */
99static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
100 unsigned long prate)
101{
102 struct clk_aux *aux = to_clk_aux(hw);
103 struct aux_rate_tbl *rtbl = aux->rtbl;
104 unsigned long val, flags = 0;
105 int i;
106
107 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
108 &i);
109
110 if (aux->lock)
111 spin_lock_irqsave(aux->lock, flags);
112
113 val = readl_relaxed(aux->reg) &
114 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
115 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
116 aux->masks->eq_sel_shift;
117 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
118 val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
119 aux->masks->xscale_sel_shift;
120 val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
121 val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
122 aux->masks->yscale_sel_shift;
123 writel_relaxed(val, aux->reg);
124
125 if (aux->lock)
126 spin_unlock_irqrestore(aux->lock, flags);
127
128 return 0;
129}
130
131static struct clk_ops clk_aux_ops = {
132 .recalc_rate = clk_aux_recalc_rate,
133 .round_rate = clk_aux_round_rate,
134 .set_rate = clk_aux_set_rate,
135};
136
137struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
138 const char *parent_name, unsigned long flags, void __iomem *reg,
139 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
140 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
141{
142 struct clk_aux *aux;
143 struct clk_init_data init;
144 struct clk *clk;
145
146 if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
147 pr_err("Invalid arguments passed");
148 return ERR_PTR(-EINVAL);
149 }
150
151 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
152 if (!aux) {
153 pr_err("could not allocate aux clk\n");
154 return ERR_PTR(-ENOMEM);
155 }
156
157 /* struct clk_aux assignments */
158 if (!masks)
159 aux->masks = &default_aux_masks;
160 else
161 aux->masks = masks;
162
163 aux->reg = reg;
164 aux->rtbl = rtbl;
165 aux->rtbl_cnt = rtbl_cnt;
166 aux->lock = lock;
167 aux->hw.init = &init;
168
169 init.name = aux_name;
170 init.ops = &clk_aux_ops;
171 init.flags = flags;
172 init.parent_names = &parent_name;
173 init.num_parents = 1;
174
175 clk = clk_register(NULL, &aux->hw);
176 if (IS_ERR_OR_NULL(clk))
177 goto free_aux;
178
179 if (gate_name) {
180 struct clk *tgate_clk;
181
182 tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg,
183 aux->masks->enable_bit, 0, lock);
184 if (IS_ERR_OR_NULL(tgate_clk))
185 goto free_aux;
186
187 if (gate_clk)
188 *gate_clk = tgate_clk;
189 }
190
191 return clk;
192
193free_aux:
194 kfree(aux);
195 pr_err("clk register failed\n");
196
197 return NULL;
198}
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
new file mode 100644
index 000000000000..4dbdb3fe18e0
--- /dev/null
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2012 ST Microelectronics
3 * Viresh Kumar <viresh.kumar@st.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * Fractional Synthesizer clock implementation
10 */
11
12#define pr_fmt(fmt) "clk-frac-synth: " fmt
13
14#include <linux/clk-provider.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include "clk.h"
19
20#define DIV_FACTOR_MASK 0x1FFFF
21
22/*
23 * DOC: Fractional Synthesizer clock
24 *
25 * Fout from synthesizer can be given from below equation:
26 *
27 * Fout= Fin/2*div (division factor)
28 * div is 17 bits:-
29 * 0-13 (fractional part)
30 * 14-16 (integer part)
31 * div is (16-14 bits).(13-0 bits) (in binary)
32 *
33 * Fout = Fin/(2 * div)
34 * Fout = ((Fin / 10000)/(2 * div)) * 10000
35 * Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
36 * Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
37 *
38 * div << 14 simply 17 bit value written at register.
39 * Max error due to scaling down by 10000 is 10 KHz
40 */
41
42#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
43
44static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
45 int index)
46{
47 struct clk_frac *frac = to_clk_frac(hw);
48 struct frac_rate_tbl *rtbl = frac->rtbl;
49
50 prate /= 10000;
51 prate <<= 14;
52 prate /= (2 * rtbl[index].div);
53 prate *= 10000;
54
55 return prate;
56}
57
58static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
59 unsigned long *prate)
60{
61 struct clk_frac *frac = to_clk_frac(hw);
62 int unused;
63
64 return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
65 frac->rtbl_cnt, &unused);
66}
67
68static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
69 unsigned long parent_rate)
70{
71 struct clk_frac *frac = to_clk_frac(hw);
72 unsigned long flags = 0;
73 unsigned int div = 1, val;
74
75 if (frac->lock)
76 spin_lock_irqsave(frac->lock, flags);
77
78 val = readl_relaxed(frac->reg);
79
80 if (frac->lock)
81 spin_unlock_irqrestore(frac->lock, flags);
82
83 div = val & DIV_FACTOR_MASK;
84
85 if (!div)
86 return 0;
87
88 parent_rate = parent_rate / 10000;
89
90 parent_rate = (parent_rate << 14) / (2 * div);
91 return parent_rate * 10000;
92}
93
94/* Configures new clock rate of frac */
95static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
96 unsigned long prate)
97{
98 struct clk_frac *frac = to_clk_frac(hw);
99 struct frac_rate_tbl *rtbl = frac->rtbl;
100 unsigned long flags = 0, val;
101 int i;
102
103 clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt,
104 &i);
105
106 if (frac->lock)
107 spin_lock_irqsave(frac->lock, flags);
108
109 val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK;
110 val |= rtbl[i].div & DIV_FACTOR_MASK;
111 writel_relaxed(val, frac->reg);
112
113 if (frac->lock)
114 spin_unlock_irqrestore(frac->lock, flags);
115
116 return 0;
117}
118
119struct clk_ops clk_frac_ops = {
120 .recalc_rate = clk_frac_recalc_rate,
121 .round_rate = clk_frac_round_rate,
122 .set_rate = clk_frac_set_rate,
123};
124
125struct clk *clk_register_frac(const char *name, const char *parent_name,
126 unsigned long flags, void __iomem *reg,
127 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock)
128{
129 struct clk_init_data init;
130 struct clk_frac *frac;
131 struct clk *clk;
132
133 if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
134 pr_err("Invalid arguments passed");
135 return ERR_PTR(-EINVAL);
136 }
137
138 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
139 if (!frac) {
140 pr_err("could not allocate frac clk\n");
141 return ERR_PTR(-ENOMEM);
142 }
143
144 /* struct clk_frac assignments */
145 frac->reg = reg;
146 frac->rtbl = rtbl;
147 frac->rtbl_cnt = rtbl_cnt;
148 frac->lock = lock;
149 frac->hw.init = &init;
150
151 init.name = name;
152 init.ops = &clk_frac_ops;
153 init.flags = flags;
154 init.parent_names = &parent_name;
155 init.num_parents = 1;
156
157 clk = clk_register(NULL, &frac->hw);
158 if (!IS_ERR_OR_NULL(clk))
159 return clk;
160
161 pr_err("clk register failed\n");
162 kfree(frac);
163
164 return NULL;
165}
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
new file mode 100644
index 000000000000..b471c9762a97
--- /dev/null
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -0,0 +1,154 @@
1/*
2 * Copyright (C) 2012 ST Microelectronics
3 * Viresh Kumar <viresh.kumar@st.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * General Purpose Timer Synthesizer clock implementation
10 */
11
12#define pr_fmt(fmt) "clk-gpt-synth: " fmt
13
14#include <linux/clk-provider.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include "clk.h"
19
20#define GPT_MSCALE_MASK 0xFFF
21#define GPT_NSCALE_SHIFT 12
22#define GPT_NSCALE_MASK 0xF
23
24/*
25 * DOC: General Purpose Timer Synthesizer clock
26 *
27 * Calculates gpt synth clk rate for different values of mscale and nscale
28 *
29 * Fout= Fin/((2 ^ (N+1)) * (M+1))
30 */
31
32#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
33
34static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
35 int index)
36{
37 struct clk_gpt *gpt = to_clk_gpt(hw);
38 struct gpt_rate_tbl *rtbl = gpt->rtbl;
39
40 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
41
42 return prate;
43}
44
45static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
46 unsigned long *prate)
47{
48 struct clk_gpt *gpt = to_clk_gpt(hw);
49 int unused;
50
51 return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
52 gpt->rtbl_cnt, &unused);
53}
54
55static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw,
56 unsigned long parent_rate)
57{
58 struct clk_gpt *gpt = to_clk_gpt(hw);
59 unsigned long flags = 0;
60 unsigned int div = 1, val;
61
62 if (gpt->lock)
63 spin_lock_irqsave(gpt->lock, flags);
64
65 val = readl_relaxed(gpt->reg);
66
67 if (gpt->lock)
68 spin_unlock_irqrestore(gpt->lock, flags);
69
70 div += val & GPT_MSCALE_MASK;
71 div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
72
73 if (!div)
74 return 0;
75
76 return parent_rate / div;
77}
78
79/* Configures new clock rate of gpt */
80static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate,
81 unsigned long prate)
82{
83 struct clk_gpt *gpt = to_clk_gpt(hw);
84 struct gpt_rate_tbl *rtbl = gpt->rtbl;
85 unsigned long flags = 0, val;
86 int i;
87
88 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
89 &i);
90
91 if (gpt->lock)
92 spin_lock_irqsave(gpt->lock, flags);
93
94 val = readl(gpt->reg) & ~GPT_MSCALE_MASK;
95 val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT);
96
97 val |= rtbl[i].mscale & GPT_MSCALE_MASK;
98 val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT;
99
100 writel_relaxed(val, gpt->reg);
101
102 if (gpt->lock)
103 spin_unlock_irqrestore(gpt->lock, flags);
104
105 return 0;
106}
107
108static struct clk_ops clk_gpt_ops = {
109 .recalc_rate = clk_gpt_recalc_rate,
110 .round_rate = clk_gpt_round_rate,
111 .set_rate = clk_gpt_set_rate,
112};
113
114struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
115 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
116 rtbl_cnt, spinlock_t *lock)
117{
118 struct clk_init_data init;
119 struct clk_gpt *gpt;
120 struct clk *clk;
121
122 if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
123 pr_err("Invalid arguments passed");
124 return ERR_PTR(-EINVAL);
125 }
126
127 gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
128 if (!gpt) {
129 pr_err("could not allocate gpt clk\n");
130 return ERR_PTR(-ENOMEM);
131 }
132
133 /* struct clk_gpt assignments */
134 gpt->reg = reg;
135 gpt->rtbl = rtbl;
136 gpt->rtbl_cnt = rtbl_cnt;
137 gpt->lock = lock;
138 gpt->hw.init = &init;
139
140 init.name = name;
141 init.ops = &clk_gpt_ops;
142 init.flags = flags;
143 init.parent_names = &parent_name;
144 init.num_parents = 1;
145
146 clk = clk_register(NULL, &gpt->hw);
147 if (!IS_ERR_OR_NULL(clk))
148 return clk;
149
150 pr_err("clk register failed\n");
151 kfree(gpt);
152
153 return NULL;
154}
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
new file mode 100644
index 000000000000..dcd4bdf4b0d9
--- /dev/null
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -0,0 +1,363 @@
1/*
2 * Copyright (C) 2012 ST Microelectronics
3 * Viresh Kumar <viresh.kumar@st.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * VCO-PLL clock implementation
10 */
11
12#define pr_fmt(fmt) "clk-vco-pll: " fmt
13
14#include <linux/clk-provider.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include "clk.h"
19
20/*
21 * DOC: VCO-PLL clock
22 *
23 * VCO and PLL rate are derived from following equations:
24 *
25 * In normal mode
26 * vco = (2 * M[15:8] * Fin)/N
27 *
28 * In Dithered mode
29 * vco = (2 * M[15:0] * Fin)/(256 * N)
30 *
31 * pll_rate = pll/2^p
32 *
33 * vco and pll are very closely bound to each other, "vco needs to program:
34 * mode, m & n" and "pll needs to program p", both share common enable/disable
35 * logic.
36 *
37 * clk_register_vco_pll() registers instances of both vco & pll.
38 * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
39 * set_rate to vco. A single rate table exists for both the clocks, which
40 * configures m, n and p.
41 */
42
43/* PLL_CTR register masks */
44#define PLL_MODE_NORMAL 0
45#define PLL_MODE_FRACTION 1
46#define PLL_MODE_DITH_DSM 2
47#define PLL_MODE_DITH_SSM 3
48#define PLL_MODE_MASK 3
49#define PLL_MODE_SHIFT 3
50#define PLL_ENABLE 2
51
52#define PLL_LOCK_SHIFT 0
53#define PLL_LOCK_MASK 1
54
55/* PLL FRQ register masks */
56#define PLL_NORM_FDBK_M_MASK 0xFF
57#define PLL_NORM_FDBK_M_SHIFT 24
58#define PLL_DITH_FDBK_M_MASK 0xFFFF
59#define PLL_DITH_FDBK_M_SHIFT 16
60#define PLL_DIV_P_MASK 0x7
61#define PLL_DIV_P_SHIFT 8
62#define PLL_DIV_N_MASK 0xFF
63#define PLL_DIV_N_SHIFT 0
64
65#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
66#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
67
68/* Calculates pll clk rate for specific value of mode, m, n and p */
69static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
70 unsigned long prate, int index, unsigned long *pll_rate)
71{
72 unsigned long rate = prate;
73 unsigned int mode;
74
75 mode = rtbl[index].mode ? 256 : 1;
76 rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
77
78 if (pll_rate)
79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
80
81 return rate * 10000;
82}
83
84static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
85 unsigned long *prate, int *index)
86{
87 struct clk_pll *pll = to_clk_pll(hw);
88 unsigned long prev_rate, vco_prev_rate, rate = 0;
89 unsigned long vco_parent_rate =
90 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
91
92 if (!prate) {
93 pr_err("%s: prate is must for pll clk\n", __func__);
94 return -EINVAL;
95 }
96
97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
98 prev_rate = rate;
99 vco_prev_rate = *prate;
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
101 &rate);
102 if (drate < rate) {
103 /* previous clock was best */
104 if (*index) {
105 rate = prev_rate;
106 *prate = vco_prev_rate;
107 (*index)--;
108 }
109 break;
110 }
111 }
112
113 return rate;
114}
115
116static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
117 unsigned long *prate)
118{
119 int unused;
120
121 return clk_pll_round_rate_index(hw, drate, prate, &unused);
122}
123
124static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
125 parent_rate)
126{
127 struct clk_pll *pll = to_clk_pll(hw);
128 unsigned long flags = 0;
129 unsigned int p;
130
131 if (pll->vco->lock)
132 spin_lock_irqsave(pll->vco->lock, flags);
133
134 p = readl_relaxed(pll->vco->cfg_reg);
135
136 if (pll->vco->lock)
137 spin_unlock_irqrestore(pll->vco->lock, flags);
138
139 p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
140
141 return parent_rate / (1 << p);
142}
143
144static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
145 unsigned long prate)
146{
147 struct clk_pll *pll = to_clk_pll(hw);
148 struct pll_rate_tbl *rtbl = pll->vco->rtbl;
149 unsigned long flags = 0, val;
150 int i;
151
152 clk_pll_round_rate_index(hw, drate, NULL, &i);
153
154 if (pll->vco->lock)
155 spin_lock_irqsave(pll->vco->lock, flags);
156
157 val = readl_relaxed(pll->vco->cfg_reg);
158 val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
159 val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
160 writel_relaxed(val, pll->vco->cfg_reg);
161
162 if (pll->vco->lock)
163 spin_unlock_irqrestore(pll->vco->lock, flags);
164
165 return 0;
166}
167
168static struct clk_ops clk_pll_ops = {
169 .recalc_rate = clk_pll_recalc_rate,
170 .round_rate = clk_pll_round_rate,
171 .set_rate = clk_pll_set_rate,
172};
173
174static inline unsigned long vco_calc_rate(struct clk_hw *hw,
175 unsigned long prate, int index)
176{
177 struct clk_vco *vco = to_clk_vco(hw);
178
179 return pll_calc_rate(vco->rtbl, prate, index, NULL);
180}
181
182static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
183 unsigned long *prate)
184{
185 struct clk_vco *vco = to_clk_vco(hw);
186 int unused;
187
188 return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
189 vco->rtbl_cnt, &unused);
190}
191
192static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
193 unsigned long parent_rate)
194{
195 struct clk_vco *vco = to_clk_vco(hw);
196 unsigned long flags = 0;
197 unsigned int num = 2, den = 0, val, mode = 0;
198
199 if (vco->lock)
200 spin_lock_irqsave(vco->lock, flags);
201
202 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
203
204 val = readl_relaxed(vco->cfg_reg);
205
206 if (vco->lock)
207 spin_unlock_irqrestore(vco->lock, flags);
208
209 den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
210
211 /* calculate numerator & denominator */
212 if (!mode) {
213 /* Normal mode */
214 num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
215 } else {
216 /* Dithered mode */
217 num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
218 den *= 256;
219 }
220
221 if (!den) {
222 WARN(1, "%s: denominator can't be zero\n", __func__);
223 return 0;
224 }
225
226 return (((parent_rate / 10000) * num) / den) * 10000;
227}
228
229/* Configures new clock rate of vco */
230static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
231 unsigned long prate)
232{
233 struct clk_vco *vco = to_clk_vco(hw);
234 struct pll_rate_tbl *rtbl = vco->rtbl;
235 unsigned long flags = 0, val;
236 int i;
237
238 clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
239 &i);
240
241 if (vco->lock)
242 spin_lock_irqsave(vco->lock, flags);
243
244 val = readl_relaxed(vco->mode_reg);
245 val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
246 val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
247 writel_relaxed(val, vco->mode_reg);
248
249 val = readl_relaxed(vco->cfg_reg);
250 val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
251 val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
252
253 val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
254 if (rtbl[i].mode)
255 val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
256 PLL_DITH_FDBK_M_SHIFT;
257 else
258 val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
259 PLL_NORM_FDBK_M_SHIFT;
260
261 writel_relaxed(val, vco->cfg_reg);
262
263 if (vco->lock)
264 spin_unlock_irqrestore(vco->lock, flags);
265
266 return 0;
267}
268
269static struct clk_ops clk_vco_ops = {
270 .recalc_rate = clk_vco_recalc_rate,
271 .round_rate = clk_vco_round_rate,
272 .set_rate = clk_vco_set_rate,
273};
274
275struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
276 const char *vco_gate_name, const char *parent_name,
277 unsigned long flags, void __iomem *mode_reg, void __iomem
278 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
279 spinlock_t *lock, struct clk **pll_clk,
280 struct clk **vco_gate_clk)
281{
282 struct clk_vco *vco;
283 struct clk_pll *pll;
284 struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
285 struct clk_init_data vco_init, pll_init;
286 const char **vco_parent_name;
287
288 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
289 !rtbl || !rtbl_cnt) {
290 pr_err("Invalid arguments passed");
291 return ERR_PTR(-EINVAL);
292 }
293
294 vco = kzalloc(sizeof(*vco), GFP_KERNEL);
295 if (!vco) {
296 pr_err("could not allocate vco clk\n");
297 return ERR_PTR(-ENOMEM);
298 }
299
300 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
301 if (!pll) {
302 pr_err("could not allocate pll clk\n");
303 goto free_vco;
304 }
305
306 /* struct clk_vco assignments */
307 vco->mode_reg = mode_reg;
308 vco->cfg_reg = cfg_reg;
309 vco->rtbl = rtbl;
310 vco->rtbl_cnt = rtbl_cnt;
311 vco->lock = lock;
312 vco->hw.init = &vco_init;
313
314 pll->vco = vco;
315 pll->hw.init = &pll_init;
316
317 if (vco_gate_name) {
318 tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
319 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
320 if (IS_ERR_OR_NULL(tvco_gate_clk))
321 goto free_pll;
322
323 if (vco_gate_clk)
324 *vco_gate_clk = tvco_gate_clk;
325 vco_parent_name = &vco_gate_name;
326 } else {
327 vco_parent_name = &parent_name;
328 }
329
330 vco_init.name = vco_name;
331 vco_init.ops = &clk_vco_ops;
332 vco_init.flags = flags;
333 vco_init.parent_names = vco_parent_name;
334 vco_init.num_parents = 1;
335
336 pll_init.name = pll_name;
337 pll_init.ops = &clk_pll_ops;
338 pll_init.flags = CLK_SET_RATE_PARENT;
339 pll_init.parent_names = &vco_name;
340 pll_init.num_parents = 1;
341
342 vco_clk = clk_register(NULL, &vco->hw);
343 if (IS_ERR_OR_NULL(vco_clk))
344 goto free_pll;
345
346 tpll_clk = clk_register(NULL, &pll->hw);
347 if (IS_ERR_OR_NULL(tpll_clk))
348 goto free_pll;
349
350 if (pll_clk)
351 *pll_clk = tpll_clk;
352
353 return vco_clk;
354
355free_pll:
356 kfree(pll);
357free_vco:
358 kfree(vco);
359
360 pr_err("Failed to register vco pll clock\n");
361
362 return ERR_PTR(-ENOMEM);
363}
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
new file mode 100644
index 000000000000..376d4e5ff326
--- /dev/null
+++ b/drivers/clk/spear/clk.c
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2012 ST Microelectronics
3 * Viresh Kumar <viresh.kumar@st.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * SPEAr clk - Common routines
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/types.h>
14#include "clk.h"
15
16long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
17 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
18 int *index)
19{
20 unsigned long prev_rate, rate = 0;
21
22 for (*index = 0; *index < rtbl_cnt; (*index)++) {
23 prev_rate = rate;
24 rate = calc_rate(hw, parent_rate, *index);
25 if (drate < rate) {
26 /* previous clock was best */
27 if (*index) {
28 rate = prev_rate;
29 (*index)--;
30 }
31 break;
32 }
33 }
34
35 return rate;
36}
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
new file mode 100644
index 000000000000..3321c46a071c
--- /dev/null
+++ b/drivers/clk/spear/clk.h
@@ -0,0 +1,134 @@
1/*
2 * Clock framework definitions for SPEAr platform
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __SPEAR_CLK_H
13#define __SPEAR_CLK_H
14
15#include <linux/clk-provider.h>
16#include <linux/spinlock_types.h>
17#include <linux/types.h>
18
19/* Auxiliary Synth clk */
20/* Default masks */
21#define AUX_EQ_SEL_SHIFT 30
22#define AUX_EQ_SEL_MASK 1
23#define AUX_EQ1_SEL 0
24#define AUX_EQ2_SEL 1
25#define AUX_XSCALE_SHIFT 16
26#define AUX_XSCALE_MASK 0xFFF
27#define AUX_YSCALE_SHIFT 0
28#define AUX_YSCALE_MASK 0xFFF
29#define AUX_SYNT_ENB 31
30
31struct aux_clk_masks {
32 u32 eq_sel_mask;
33 u32 eq_sel_shift;
34 u32 eq1_mask;
35 u32 eq2_mask;
36 u32 xscale_sel_mask;
37 u32 xscale_sel_shift;
38 u32 yscale_sel_mask;
39 u32 yscale_sel_shift;
40 u32 enable_bit;
41};
42
43struct aux_rate_tbl {
44 u16 xscale;
45 u16 yscale;
46 u8 eq;
47};
48
49struct clk_aux {
50 struct clk_hw hw;
51 void __iomem *reg;
52 struct aux_clk_masks *masks;
53 struct aux_rate_tbl *rtbl;
54 u8 rtbl_cnt;
55 spinlock_t *lock;
56};
57
58/* Fractional Synth clk */
59struct frac_rate_tbl {
60 u32 div;
61};
62
63struct clk_frac {
64 struct clk_hw hw;
65 void __iomem *reg;
66 struct frac_rate_tbl *rtbl;
67 u8 rtbl_cnt;
68 spinlock_t *lock;
69};
70
71/* GPT clk */
72struct gpt_rate_tbl {
73 u16 mscale;
74 u16 nscale;
75};
76
77struct clk_gpt {
78 struct clk_hw hw;
79 void __iomem *reg;
80 struct gpt_rate_tbl *rtbl;
81 u8 rtbl_cnt;
82 spinlock_t *lock;
83};
84
85/* VCO-PLL clk */
86struct pll_rate_tbl {
87 u8 mode;
88 u16 m;
89 u8 n;
90 u8 p;
91};
92
93struct clk_vco {
94 struct clk_hw hw;
95 void __iomem *mode_reg;
96 void __iomem *cfg_reg;
97 struct pll_rate_tbl *rtbl;
98 u8 rtbl_cnt;
99 spinlock_t *lock;
100};
101
102struct clk_pll {
103 struct clk_hw hw;
104 struct clk_vco *vco;
105 const char *parent[1];
106 spinlock_t *lock;
107};
108
109typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
110 int index);
111
112/* clk register routines */
113struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
114 const char *parent_name, unsigned long flags, void __iomem *reg,
115 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
116 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
117struct clk *clk_register_frac(const char *name, const char *parent_name,
118 unsigned long flags, void __iomem *reg,
119 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
120struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
121 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
122 rtbl_cnt, spinlock_t *lock);
123struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
124 const char *vco_gate_name, const char *parent_name,
125 unsigned long flags, void __iomem *mode_reg, void __iomem
126 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
127 spinlock_t *lock, struct clk **pll_clk,
128 struct clk **vco_gate_clk);
129
130long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
131 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
132 int *index);
133
134#endif /* __SPEAR_CLK_H */
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
new file mode 100644
index 000000000000..42b68df9aeef
--- /dev/null
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -0,0 +1,1106 @@
1/*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* PLL related registers and bit values */
24#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
25 /* PLL_CFG bit values */
26 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
27 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
28 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
29 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
30 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
31 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
32 #define SPEAR1310_PLL_CLK_MASK 2
33 #define SPEAR1310_PLL3_CLK_SHIFT 24
34 #define SPEAR1310_PLL2_CLK_SHIFT 22
35 #define SPEAR1310_PLL1_CLK_SHIFT 20
36
37#define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214)
38#define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218)
39#define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220)
40#define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224)
41#define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C)
42#define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230)
43#define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238)
44#define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C)
45#define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
46 /* PERIP_CLK_CFG bit values */
47 #define SPEAR1310_GPT_OSC24_VAL 0
48 #define SPEAR1310_GPT_APB_VAL 1
49 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_GPT3_CLK_SHIFT 11
51 #define SPEAR1310_GPT2_CLK_SHIFT 10
52 #define SPEAR1310_GPT1_CLK_SHIFT 9
53 #define SPEAR1310_GPT0_CLK_SHIFT 8
54 #define SPEAR1310_UART_CLK_PLL5_VAL 0
55 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_UART_CLK_SYNT_VAL 2
57 #define SPEAR1310_UART_CLK_MASK 2
58 #define SPEAR1310_UART_CLK_SHIFT 4
59
60 #define SPEAR1310_AUX_CLK_PLL5_VAL 0
61 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
62 #define SPEAR1310_CLCD_CLK_MASK 2
63 #define SPEAR1310_CLCD_CLK_SHIFT 2
64 #define SPEAR1310_C3_CLK_MASK 1
65 #define SPEAR1310_C3_CLK_SHIFT 1
66
67#define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
68 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
69 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
70 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
74
75#define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1310_I2S_REF_SEL_MASK 1
89 #define SPEAR1310_I2S_REF_SHIFT 2
90 #define SPEAR1310_I2S_SRC_CLK_MASK 2
91 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268)
100#define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270)
101#define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280)
102#define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288)
103#define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290)
104#define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298)
105 /* Check Fractional synthesizer reg masks */
106
107#define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300)
108 /* PERIP1_CLK_ENB register masks */
109 #define SPEAR1310_RTC_CLK_ENB 31
110 #define SPEAR1310_ADC_CLK_ENB 30
111 #define SPEAR1310_C3_CLK_ENB 29
112 #define SPEAR1310_JPEG_CLK_ENB 28
113 #define SPEAR1310_CLCD_CLK_ENB 27
114 #define SPEAR1310_DMA_CLK_ENB 25
115 #define SPEAR1310_GPIO1_CLK_ENB 24
116 #define SPEAR1310_GPIO0_CLK_ENB 23
117 #define SPEAR1310_GPT1_CLK_ENB 22
118 #define SPEAR1310_GPT0_CLK_ENB 21
119 #define SPEAR1310_I2S0_CLK_ENB 20
120 #define SPEAR1310_I2S1_CLK_ENB 19
121 #define SPEAR1310_I2C0_CLK_ENB 18
122 #define SPEAR1310_SSP_CLK_ENB 17
123 #define SPEAR1310_UART_CLK_ENB 15
124 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
125 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
126 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
127 #define SPEAR1310_UOC_CLK_ENB 11
128 #define SPEAR1310_UHC1_CLK_ENB 10
129 #define SPEAR1310_UHC0_CLK_ENB 9
130 #define SPEAR1310_GMAC_CLK_ENB 8
131 #define SPEAR1310_CFXD_CLK_ENB 7
132 #define SPEAR1310_SDHCI_CLK_ENB 6
133 #define SPEAR1310_SMI_CLK_ENB 5
134 #define SPEAR1310_FSMC_CLK_ENB 4
135 #define SPEAR1310_SYSRAM0_CLK_ENB 3
136 #define SPEAR1310_SYSRAM1_CLK_ENB 2
137 #define SPEAR1310_SYSROM_CLK_ENB 1
138 #define SPEAR1310_BUS_CLK_ENB 0
139
140#define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304)
141 /* PERIP2_CLK_ENB register masks */
142 #define SPEAR1310_THSENS_CLK_ENB 8
143 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
144 #define SPEAR1310_ACP_CLK_ENB 6
145 #define SPEAR1310_GPT3_CLK_ENB 5
146 #define SPEAR1310_GPT2_CLK_ENB 4
147 #define SPEAR1310_KBD_CLK_ENB 3
148 #define SPEAR1310_CPU_DBG_CLK_ENB 2
149 #define SPEAR1310_DDR_CORE_CLK_ENB 1
150 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
151
152#define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310)
153 /* RAS_CLK_ENB register masks */
154 #define SPEAR1310_SYNT3_CLK_ENB 17
155 #define SPEAR1310_SYNT2_CLK_ENB 16
156 #define SPEAR1310_SYNT1_CLK_ENB 15
157 #define SPEAR1310_SYNT0_CLK_ENB 14
158 #define SPEAR1310_PCLK3_CLK_ENB 13
159 #define SPEAR1310_PCLK2_CLK_ENB 12
160 #define SPEAR1310_PCLK1_CLK_ENB 11
161 #define SPEAR1310_PCLK0_CLK_ENB 10
162 #define SPEAR1310_PLL3_CLK_ENB 9
163 #define SPEAR1310_PLL2_CLK_ENB 8
164 #define SPEAR1310_C125M_PAD_CLK_ENB 7
165 #define SPEAR1310_C30M_CLK_ENB 6
166 #define SPEAR1310_C48M_CLK_ENB 5
167 #define SPEAR1310_OSC_25M_CLK_ENB 4
168 #define SPEAR1310_OSC_32K_CLK_ENB 3
169 #define SPEAR1310_OSC_24M_CLK_ENB 2
170 #define SPEAR1310_PCLK_CLK_ENB 1
171 #define SPEAR1310_ACLK_CLK_ENB 0
172
173/* RAS Area Control Register */
174#define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000)
175 #define SPEAR1310_SSP1_CLK_MASK 3
176 #define SPEAR1310_SSP1_CLK_SHIFT 26
177 #define SPEAR1310_TDM_CLK_MASK 1
178 #define SPEAR1310_TDM2_CLK_SHIFT 24
179 #define SPEAR1310_TDM1_CLK_SHIFT 23
180 #define SPEAR1310_I2C_CLK_MASK 1
181 #define SPEAR1310_I2C7_CLK_SHIFT 22
182 #define SPEAR1310_I2C6_CLK_SHIFT 21
183 #define SPEAR1310_I2C5_CLK_SHIFT 20
184 #define SPEAR1310_I2C4_CLK_SHIFT 19
185 #define SPEAR1310_I2C3_CLK_SHIFT 18
186 #define SPEAR1310_I2C2_CLK_SHIFT 17
187 #define SPEAR1310_I2C1_CLK_SHIFT 16
188 #define SPEAR1310_GPT64_CLK_MASK 1
189 #define SPEAR1310_GPT64_CLK_SHIFT 15
190 #define SPEAR1310_RAS_UART_CLK_MASK 1
191 #define SPEAR1310_UART5_CLK_SHIFT 14
192 #define SPEAR1310_UART4_CLK_SHIFT 13
193 #define SPEAR1310_UART3_CLK_SHIFT 12
194 #define SPEAR1310_UART2_CLK_SHIFT 11
195 #define SPEAR1310_UART1_CLK_SHIFT 10
196 #define SPEAR1310_PCI_CLK_MASK 1
197 #define SPEAR1310_PCI_CLK_SHIFT 0
198
199#define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004)
200 #define SPEAR1310_PHY_CLK_MASK 0x3
201 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
202 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
203
204#define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148)
205 #define SPEAR1310_CAN1_CLK_ENB 25
206 #define SPEAR1310_CAN0_CLK_ENB 24
207 #define SPEAR1310_GPT64_CLK_ENB 23
208 #define SPEAR1310_SSP1_CLK_ENB 22
209 #define SPEAR1310_I2C7_CLK_ENB 21
210 #define SPEAR1310_I2C6_CLK_ENB 20
211 #define SPEAR1310_I2C5_CLK_ENB 19
212 #define SPEAR1310_I2C4_CLK_ENB 18
213 #define SPEAR1310_I2C3_CLK_ENB 17
214 #define SPEAR1310_I2C2_CLK_ENB 16
215 #define SPEAR1310_I2C1_CLK_ENB 15
216 #define SPEAR1310_UART5_CLK_ENB 14
217 #define SPEAR1310_UART4_CLK_ENB 13
218 #define SPEAR1310_UART3_CLK_ENB 12
219 #define SPEAR1310_UART2_CLK_ENB 11
220 #define SPEAR1310_UART1_CLK_ENB 10
221 #define SPEAR1310_RS485_1_CLK_ENB 9
222 #define SPEAR1310_RS485_0_CLK_ENB 8
223 #define SPEAR1310_TDM2_CLK_ENB 7
224 #define SPEAR1310_TDM1_CLK_ENB 6
225 #define SPEAR1310_PCI_CLK_ENB 5
226 #define SPEAR1310_GMII_CLK_ENB 4
227 #define SPEAR1310_MII2_CLK_ENB 3
228 #define SPEAR1310_MII1_CLK_ENB 2
229 #define SPEAR1310_MII0_CLK_ENB 1
230 #define SPEAR1310_ESRAM_CLK_ENB 0
231
232static DEFINE_SPINLOCK(_lock);
233
234/* pll rate configuration table, in ascending order of rates */
235static struct pll_rate_tbl pll_rtbl[] = {
236 /* PCLK 24MHz */
237 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
239 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
240 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
241 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
242 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
244};
245
246/* vco-pll4 rate configuration table, in ascending order of rates */
247static struct pll_rate_tbl pll4_rtbl[] = {
248 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
249 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
250 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
251 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
283 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
286};
287
288/* i2s prescaler1 masks */
289static struct aux_clk_masks i2s_prs1_masks = {
290 .eq_sel_mask = AUX_EQ_SEL_MASK,
291 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
292 .eq1_mask = AUX_EQ1_SEL,
293 .eq2_mask = AUX_EQ2_SEL,
294 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
295 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
296 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
297 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
298};
299
300/* i2s sclk (bit clock) syynthesizers masks */
301static struct aux_clk_masks i2s_sclk_masks = {
302 .eq_sel_mask = AUX_EQ_SEL_MASK,
303 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
304 .eq1_mask = AUX_EQ1_SEL,
305 .eq2_mask = AUX_EQ2_SEL,
306 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
307 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
308 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
309 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
310 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
311};
312
313/* i2s prs1 aux rate configuration table, in ascending order of rates */
314static struct aux_rate_tbl i2s_prs1_rtbl[] = {
315 /* For parent clk = 49.152 MHz */
316 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
317};
318
319/* i2s sclk aux rate configuration table, in ascending order of rates */
320static struct aux_rate_tbl i2s_sclk_rtbl[] = {
321 /* For i2s_ref_clk = 12.288MHz */
322 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
323 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
324};
325
326/* adc rate configuration table, in ascending order of rates */
327/* possible adc range is 2.5 MHz to 20 MHz. */
328static struct aux_rate_tbl adc_rtbl[] = {
329 /* For ahb = 166.67 MHz */
330 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
331 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
332 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
333 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
334};
335
336/* General synth rate configuration table, in ascending order of rates */
337static struct frac_rate_tbl gen_rtbl[] = {
338 /* For vco1div4 = 250 MHz */
339 {.div = 0x14000}, /* 25 MHz */
340 {.div = 0x0A000}, /* 50 MHz */
341 {.div = 0x05000}, /* 100 MHz */
342 {.div = 0x02000}, /* 250 MHz */
343};
344
345/* clock parents */
346static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
347static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
348static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
349static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
350static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
351 "osc_25m_clk", };
352static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
353 "gmac_phy_synth_gate_clk", };
354static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
355static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
356static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
357 "i2s_src_pad_clk", };
358static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
359static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
360 "pll3_clk", };
361static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
362 "pll2_clk", };
363static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
364 "ras_pll2_clk", "ras_synth0_clk", };
365static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
366 "ras_pll2_clk", "ras_synth0_clk", };
367static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
368static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
369static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
370 "ras_plclk0_clk", };
371static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
372static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
373
374void __init spear1310_clk_init(void)
375{
376 struct clk *clk, *clk1;
377
378 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
379 clk_register_clkdev(clk, "apb_pclk", NULL);
380
381 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
382 32000);
383 clk_register_clkdev(clk, "osc_32k_clk", NULL);
384
385 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
386 24000000);
387 clk_register_clkdev(clk, "osc_24m_clk", NULL);
388
389 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
390 25000000);
391 clk_register_clkdev(clk, "osc_25m_clk", NULL);
392
393 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
394 CLK_IS_ROOT, 125000000);
395 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
396
397 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
398 CLK_IS_ROOT, 12288000);
399 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
400
401 /* clock derived from 32 KHz osc clk */
402 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
403 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
404 &_lock);
405 clk_register_clkdev(clk, NULL, "fc900000.rtc");
406
407 /* clock derived from 24 or 25 MHz osc clk */
408 /* vco-pll */
409 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
410 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
411 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
412 &_lock);
413 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
414 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
415 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
417 clk_register_clkdev(clk, "vco1_clk", NULL);
418 clk_register_clkdev(clk1, "pll1_clk", NULL);
419
420 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
421 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
422 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
423 &_lock);
424 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
425 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
426 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
427 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
428 clk_register_clkdev(clk, "vco2_clk", NULL);
429 clk_register_clkdev(clk1, "pll2_clk", NULL);
430
431 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
432 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
433 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
434 &_lock);
435 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
436 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
437 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
438 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
439 clk_register_clkdev(clk, "vco3_clk", NULL);
440 clk_register_clkdev(clk1, "pll3_clk", NULL);
441
442 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
443 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
444 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
445 clk_register_clkdev(clk, "vco4_clk", NULL);
446 clk_register_clkdev(clk1, "pll4_clk", NULL);
447
448 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
449 48000000);
450 clk_register_clkdev(clk, "pll5_clk", NULL);
451
452 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
453 25000000);
454 clk_register_clkdev(clk, "pll6_clk", NULL);
455
456 /* vco div n clocks */
457 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
458 2);
459 clk_register_clkdev(clk, "vco1div2_clk", NULL);
460
461 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
462 4);
463 clk_register_clkdev(clk, "vco1div4_clk", NULL);
464
465 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
466 2);
467 clk_register_clkdev(clk, "vco2div2_clk", NULL);
468
469 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
470 2);
471 clk_register_clkdev(clk, "vco3div2_clk", NULL);
472
473 /* peripherals */
474 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
475 128);
476 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
477 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
478 &_lock);
479 clk_register_clkdev(clk, NULL, "spear_thermal");
480
481 /* clock derived from pll4 clk */
482 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
483 1);
484 clk_register_clkdev(clk, "ddr_clk", NULL);
485
486 /* clock derived from pll1 clk */
487 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
488 clk_register_clkdev(clk, "cpu_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, NULL, "ec800620.wdt");
493
494 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
495 6);
496 clk_register_clkdev(clk, "ahb_clk", NULL);
497
498 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
499 12);
500 clk_register_clkdev(clk, "apb_clk", NULL);
501
502 /* gpt clocks */
503 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
504 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
505 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
506 &_lock);
507 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
508 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
509 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
510 &_lock);
511 clk_register_clkdev(clk, NULL, "gpt0");
512
513 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
514 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
515 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
516 &_lock);
517 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
518 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
519 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
520 &_lock);
521 clk_register_clkdev(clk, NULL, "gpt1");
522
523 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
524 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
525 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
526 &_lock);
527 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
528 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
529 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
530 &_lock);
531 clk_register_clkdev(clk, NULL, "gpt2");
532
533 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
534 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
535 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
536 &_lock);
537 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
538 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
539 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
540 &_lock);
541 clk_register_clkdev(clk, NULL, "gpt3");
542
543 /* others */
544 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
545 "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
546 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
547 clk_register_clkdev(clk, "uart_synth_clk", NULL);
548 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
549
550 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
551 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
552 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
553 &_lock);
554 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
555
556 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
557 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "e0000000.serial");
560
561 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
562 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
563 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
564 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
565 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
566
567 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
568 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
569 &_lock);
570 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
571
572 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
573 "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
574 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
576 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
577
578 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
579 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
580 &_lock);
581 clk_register_clkdev(clk, NULL, "b2800000.cf");
582 clk_register_clkdev(clk, NULL, "arasan_xd");
583
584 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
585 "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
586 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
587 clk_register_clkdev(clk, "c3_synth_clk", NULL);
588 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
589
590 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
591 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
592 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
593 &_lock);
594 clk_register_clkdev(clk, "c3_mux_clk", NULL);
595
596 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
597 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
598 &_lock);
599 clk_register_clkdev(clk, NULL, "c3");
600
601 /* gmac */
602 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
603 gmac_phy_input_parents,
604 ARRAY_SIZE(gmac_phy_input_parents), 0,
605 SPEAR1310_GMAC_CLK_CFG,
606 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
607 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
609
610 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
611 "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
612 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
613 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
614 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
615
616 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
617 ARRAY_SIZE(gmac_phy_parents), 0,
618 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
619 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, NULL, "stmmacphy.0");
621
622 /* clcd */
623 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
624 ARRAY_SIZE(clcd_synth_parents), 0,
625 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
626 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
627 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
628
629 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
630 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
631 ARRAY_SIZE(clcd_rtbl), &_lock);
632 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
633
634 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
635 ARRAY_SIZE(clcd_pixel_parents), 0,
636 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
637 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
638 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
639
640 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
641 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
642 &_lock);
643 clk_register_clkdev(clk, "clcd_clk", NULL);
644
645 /* i2s */
646 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
647 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
648 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
649 0, &_lock);
650 clk_register_clkdev(clk, "i2s_src_clk", NULL);
651
652 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
653 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
654 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
655 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
656
657 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
658 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
659 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
660 &_lock);
661 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
662
663 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
664 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
665 0, &_lock);
666 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
667
668 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
669 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
670 &i2s_sclk_masks, i2s_sclk_rtbl,
671 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
672 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
673 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
674
675 /* clock derived from ahb clk */
676 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
677 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
678 &_lock);
679 clk_register_clkdev(clk, NULL, "e0280000.i2c");
680
681 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
682 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
683 &_lock);
684 clk_register_clkdev(clk, NULL, "ea800000.dma");
685 clk_register_clkdev(clk, NULL, "eb000000.dma");
686
687 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
688 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
689 &_lock);
690 clk_register_clkdev(clk, NULL, "b2000000.jpeg");
691
692 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
693 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
694 &_lock);
695 clk_register_clkdev(clk, NULL, "e2000000.eth");
696
697 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
698 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
699 &_lock);
700 clk_register_clkdev(clk, NULL, "b0000000.flash");
701
702 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
703 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
704 &_lock);
705 clk_register_clkdev(clk, NULL, "ea000000.flash");
706
707 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
708 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
709 &_lock);
710 clk_register_clkdev(clk, "usbh.0_clk", NULL);
711
712 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
713 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
714 &_lock);
715 clk_register_clkdev(clk, "usbh.1_clk", NULL);
716
717 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
718 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
719 &_lock);
720 clk_register_clkdev(clk, NULL, "uoc");
721
722 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
723 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
724 0, &_lock);
725 clk_register_clkdev(clk, NULL, "dw_pcie.0");
726 clk_register_clkdev(clk, NULL, "ahci.0");
727
728 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
729 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, NULL, "dw_pcie.1");
732 clk_register_clkdev(clk, NULL, "ahci.1");
733
734 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
735 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
736 0, &_lock);
737 clk_register_clkdev(clk, NULL, "dw_pcie.2");
738 clk_register_clkdev(clk, NULL, "ahci.2");
739
740 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
741 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
742 &_lock);
743 clk_register_clkdev(clk, "sysram0_clk", NULL);
744
745 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
746 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
747 &_lock);
748 clk_register_clkdev(clk, "sysram1_clk", NULL);
749
750 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
751 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
752 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
753 clk_register_clkdev(clk, "adc_synth_clk", NULL);
754 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
755
756 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
758 &_lock);
759 clk_register_clkdev(clk, NULL, "adc_clk");
760
761 /* clock derived from apb clk */
762 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
763 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "e0100000.spi");
766
767 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
768 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "e0600000.gpio");
771
772 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
773 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, NULL, "e0680000.gpio");
776
777 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
778 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, NULL, "e0180000.i2s");
781
782 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
783 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "e0200000.i2s");
786
787 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
788 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
789 &_lock);
790 clk_register_clkdev(clk, NULL, "e0300000.kbd");
791
792 /* RAS clks */
793 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
794 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
795 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
796 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
797 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
798
799 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
800 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
801 0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
802 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
803 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
804
805 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
806 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
807 &_lock);
808 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
809
810 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
811 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
812 &_lock);
813 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
814
815 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
816 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
817 &_lock);
818 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
819
820 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
821 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
822 &_lock);
823 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
824
825 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
826 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
829
830 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
831 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
834
835 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
836 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
839
840 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
841 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
844
845 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
846 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
847 &_lock);
848 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
849
850 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
851 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
852 &_lock);
853 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
854
855 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
856 30000000);
857 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
858 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
859 &_lock);
860 clk_register_clkdev(clk, "ras_30m_clk", NULL);
861
862 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
863 48000000);
864 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
865 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
866 &_lock);
867 clk_register_clkdev(clk, "ras_48m_clk", NULL);
868
869 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
870 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
871 &_lock);
872 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
873
874 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
875 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
876 &_lock);
877 clk_register_clkdev(clk, "ras_apb_clk", NULL);
878
879 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
880 50000000);
881
882 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
883 50000000);
884
885 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
886 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
887 &_lock);
888 clk_register_clkdev(clk, NULL, "c_can_platform.0");
889
890 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
891 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
892 &_lock);
893 clk_register_clkdev(clk, NULL, "c_can_platform.1");
894
895 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
896 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
897 &_lock);
898 clk_register_clkdev(clk, NULL, "5c400000.eth");
899
900 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
901 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
902 &_lock);
903 clk_register_clkdev(clk, NULL, "5c500000.eth");
904
905 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
906 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
907 &_lock);
908 clk_register_clkdev(clk, NULL, "5c600000.eth");
909
910 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
911 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "5c700000.eth");
914
915 clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
916 smii_rgmii_phy_parents,
917 ARRAY_SIZE(smii_rgmii_phy_parents), 0,
918 SPEAR1310_RAS_CTRL_REG1,
919 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
920 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
921 clk_register_clkdev(clk, NULL, "stmmacphy.1");
922 clk_register_clkdev(clk, NULL, "stmmacphy.2");
923 clk_register_clkdev(clk, NULL, "stmmacphy.4");
924
925 clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
926 ARRAY_SIZE(rmii_phy_parents), 0,
927 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
928 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
929 clk_register_clkdev(clk, NULL, "stmmacphy.3");
930
931 clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
932 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
933 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
934 0, &_lock);
935 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
936
937 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
938 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
939 &_lock);
940 clk_register_clkdev(clk, NULL, "5c800000.serial");
941
942 clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
943 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
944 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
945 0, &_lock);
946 clk_register_clkdev(clk, "uart2_mux_clk", NULL);
947
948 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
949 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
950 &_lock);
951 clk_register_clkdev(clk, NULL, "5c900000.serial");
952
953 clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
954 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
955 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
956 0, &_lock);
957 clk_register_clkdev(clk, "uart3_mux_clk", NULL);
958
959 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
960 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
961 &_lock);
962 clk_register_clkdev(clk, NULL, "5ca00000.serial");
963
964 clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
965 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
966 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
967 0, &_lock);
968 clk_register_clkdev(clk, "uart4_mux_clk", NULL);
969
970 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
971 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
972 &_lock);
973 clk_register_clkdev(clk, NULL, "5cb00000.serial");
974
975 clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
976 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
977 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
978 0, &_lock);
979 clk_register_clkdev(clk, "uart5_mux_clk", NULL);
980
981 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
982 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
983 &_lock);
984 clk_register_clkdev(clk, NULL, "5cc00000.serial");
985
986 clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
987 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
988 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
989 &_lock);
990 clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
991
992 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
993 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
994 &_lock);
995 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
996
997 clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
998 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
999 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1000 &_lock);
1001 clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
1002
1003 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
1004 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1005 &_lock);
1006 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1007
1008 clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
1009 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1010 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1011 &_lock);
1012 clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
1013
1014 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
1015 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1016 &_lock);
1017 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1018
1019 clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
1020 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1021 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1022 &_lock);
1023 clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
1024
1025 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
1026 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1027 &_lock);
1028 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1029
1030 clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
1031 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1032 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1033 &_lock);
1034 clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
1035
1036 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
1037 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1038 &_lock);
1039 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1040
1041 clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
1042 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1043 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1044 &_lock);
1045 clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
1046
1047 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
1048 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1049 &_lock);
1050 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1051
1052 clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
1053 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1054 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1055 &_lock);
1056 clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
1057
1058 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
1059 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1060 &_lock);
1061 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1062
1063 clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
1064 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1065 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1066 &_lock);
1067 clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
1068
1069 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
1070 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1071 &_lock);
1072 clk_register_clkdev(clk, NULL, "5d400000.spi");
1073
1074 clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
1075 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1076 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1077 &_lock);
1078 clk_register_clkdev(clk, "pci_mux_clk", NULL);
1079
1080 clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
1081 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1082 &_lock);
1083 clk_register_clkdev(clk, NULL, "pci");
1084
1085 clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
1086 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1087 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1088 &_lock);
1089 clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
1090
1091 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
1092 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1093 &_lock);
1094 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1095
1096 clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
1097 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1098 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1099 &_lock);
1100 clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
1101
1102 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
1103 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1104 &_lock);
1105 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1106}
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
new file mode 100644
index 000000000000..f130919d5bf8
--- /dev/null
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -0,0 +1,964 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29
30/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
32 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38 #define SPEAR1340_PLL_CLK_MASK 2
39 #define SPEAR1340_PLL3_CLK_SHIFT 24
40 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20
42
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
52 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56 #define SPEAR1340_GPT3_CLK_SHIFT 13
57 #define SPEAR1340_GPT2_CLK_SHIFT 12
58 #define SPEAR1340_GPT_CLK_MASK 1
59 #define SPEAR1340_GPT1_CLK_SHIFT 9
60 #define SPEAR1340_GPT0_CLK_SHIFT 8
61 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_UART1_CLK_SHIFT 6
63 #define SPEAR1340_UART0_CLK_SHIFT 4
64 #define SPEAR1340_CLCD_CLK_MASK 2
65 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1
68
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1340_I2S_REF_SEL_MASK 1
89 #define SPEAR1340_I2S_REF_SHIFT 2
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29
111 #define SPEAR1340_CLCD_CLK_ENB 27
112 #define SPEAR1340_DMA_CLK_ENB 25
113 #define SPEAR1340_GPIO1_CLK_ENB 24
114 #define SPEAR1340_GPIO0_CLK_ENB 23
115 #define SPEAR1340_GPT1_CLK_ENB 22
116 #define SPEAR1340_GPT0_CLK_ENB 21
117 #define SPEAR1340_I2S_PLAY_CLK_ENB 20
118 #define SPEAR1340_I2S_REC_CLK_ENB 19
119 #define SPEAR1340_I2C0_CLK_ENB 18
120 #define SPEAR1340_SSP_CLK_ENB 17
121 #define SPEAR1340_UART0_CLK_ENB 15
122 #define SPEAR1340_PCIE_SATA_CLK_ENB 12
123 #define SPEAR1340_UOC_CLK_ENB 11
124 #define SPEAR1340_UHC1_CLK_ENB 10
125 #define SPEAR1340_UHC0_CLK_ENB 9
126 #define SPEAR1340_GMAC_CLK_ENB 8
127 #define SPEAR1340_CFXD_CLK_ENB 7
128 #define SPEAR1340_SDHCI_CLK_ENB 6
129 #define SPEAR1340_SMI_CLK_ENB 5
130 #define SPEAR1340_FSMC_CLK_ENB 4
131 #define SPEAR1340_SYSRAM0_CLK_ENB 3
132 #define SPEAR1340_SYSRAM1_CLK_ENB 2
133 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0
135
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6
140 #define SPEAR1340_GPT3_CLK_ENB 5
141 #define SPEAR1340_GPT2_CLK_ENB 4
142 #define SPEAR1340_KBD_CLK_ENB 3
143 #define SPEAR1340_CPU_DBG_CLK_ENB 2
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154 #define SPEAR1340_CAM0_CLK_ENB 10
155 #define SPEAR1340_CAM1_CLK_ENB 9
156 #define SPEAR1340_CAM2_CLK_ENB 8
157 #define SPEAR1340_CAM3_CLK_ENB 7
158 #define SPEAR1340_MALI_CLK_ENB 6
159 #define SPEAR1340_CEC0_CLK_ENB 5
160 #define SPEAR1340_CEC1_CLK_ENB 4
161 #define SPEAR1340_PWM_CLK_ENB 3
162 #define SPEAR1340_I2C1_CLK_ENB 2
163 #define SPEAR1340_UART1_CLK_ENB 1
164
165static DEFINE_SPINLOCK(_lock);
166
167/* pll rate configuration table, in ascending order of rates */
168static struct pll_rate_tbl pll_rtbl[] = {
169 /* PCLK 24MHz */
170 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
172 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
173 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
174 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
175 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
177 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178};
179
180/* vco-pll4 rate configuration table, in ascending order of rates */
181static struct pll_rate_tbl pll4_rtbl[] = {
182 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
183 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
184 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
186};
187
188/*
189 * All below entries generate 166 MHz for
190 * different values of vco1div2
191 */
192static struct frac_rate_tbl amba_synth_rtbl[] = {
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198};
199
200/*
201 * Synthesizer Clock derived from vcodiv2. This clock is one of the
202 * possible clocks to feed cpu directly.
203 * We can program this synthesizer to make cpu run on different clock
204 * frequencies.
205 * Following table provides configuration values to let cpu run on 200,
206 * 250, 332, 400 or 500 MHz considering different possibilites of input
207 * (vco1div2) clock.
208 *
209 * --------------------------------------------------------------------
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211 * --------------------------------------------------------------------
212 * 400 200 100 0x04000
213 * 400 250 125 0x03333
214 * 400 332 166 0x0268D
215 * 400 400 200 0x02000
216 * --------------------------------------------------------------------
217 * 500 200 100 0x05000
218 * 500 250 125 0x04000
219 * 500 332 166 0x03031
220 * 500 400 200 0x02800
221 * 500 500 250 0x02000
222 * --------------------------------------------------------------------
223 * 664 200 100 0x06a38
224 * 664 250 125 0x054FD
225 * 664 332 166 0x04000
226 * 664 400 200 0x0351E
227 * 664 500 250 0x02A7E
228 * --------------------------------------------------------------------
229 * 800 200 100 0x08000
230 * 800 250 125 0x06666
231 * 800 332 166 0x04D18
232 * 800 400 200 0x04000
233 * 800 500 250 0x03333
234 * --------------------------------------------------------------------
235 * sys rate configuration table is in descending order of divisor.
236 */
237static struct frac_rate_tbl sys_synth_rtbl[] = {
238 {.div = 0x08000},
239 {.div = 0x06a38},
240 {.div = 0x06666},
241 {.div = 0x054FD},
242 {.div = 0x05000},
243 {.div = 0x04D18},
244 {.div = 0x04000},
245 {.div = 0x0351E},
246 {.div = 0x03333},
247 {.div = 0x03031},
248 {.div = 0x02A7E},
249 {.div = 0x02800},
250 {.div = 0x0268D},
251 {.div = 0x02000},
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
289};
290
291/* i2s prescaler1 masks */
292static struct aux_clk_masks i2s_prs1_masks = {
293 .eq_sel_mask = AUX_EQ_SEL_MASK,
294 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
295 .eq1_mask = AUX_EQ1_SEL,
296 .eq2_mask = AUX_EQ2_SEL,
297 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
298 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
299 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
300 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
301};
302
303/* i2s sclk (bit clock) syynthesizers masks */
304static struct aux_clk_masks i2s_sclk_masks = {
305 .eq_sel_mask = AUX_EQ_SEL_MASK,
306 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
307 .eq1_mask = AUX_EQ1_SEL,
308 .eq2_mask = AUX_EQ2_SEL,
309 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
310 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
311 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
312 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
313 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
314};
315
316/* i2s prs1 aux rate configuration table, in ascending order of rates */
317static struct aux_rate_tbl i2s_prs1_rtbl[] = {
318 /* For parent clk = 49.152 MHz */
319 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
320 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
321 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
322 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
323
324 /*
325 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
326 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
327 */
328 {.xscale = 1, .yscale = 3, .eq = 0},
329
330 /* For parent clk = 49.152 MHz */
331 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
333};
334
335/* i2s sclk aux rate configuration table, in ascending order of rates */
336static struct aux_rate_tbl i2s_sclk_rtbl[] = {
337 /* For sclk = ref_clk * x/2/y */
338 {.xscale = 1, .yscale = 4, .eq = 0},
339 {.xscale = 1, .yscale = 2, .eq = 0},
340};
341
342/* adc rate configuration table, in ascending order of rates */
343/* possible adc range is 2.5 MHz to 20 MHz. */
344static struct aux_rate_tbl adc_rtbl[] = {
345 /* For ahb = 166.67 MHz */
346 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
347 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
348 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
349 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350};
351
352/* General synth rate configuration table, in ascending order of rates */
353static struct frac_rate_tbl gen_rtbl[] = {
354 /* For vco1div4 = 250 MHz */
355 {.div = 0x1624E}, /* 22.5792 MHz */
356 {.div = 0x14585}, /* 24.576 MHz */
357 {.div = 0x14000}, /* 25 MHz */
358 {.div = 0x0B127}, /* 45.1584 MHz */
359 {.div = 0x0A000}, /* 50 MHz */
360 {.div = 0x061A8}, /* 81.92 MHz */
361 {.div = 0x05000}, /* 100 MHz */
362 {.div = 0x02800}, /* 200 MHz */
363 {.div = 0x02620}, /* 210 MHz */
364 {.div = 0x02460}, /* 220 MHz */
365 {.div = 0x022C0}, /* 230 MHz */
366 {.div = 0x02160}, /* 240 MHz */
367 {.div = 0x02000}, /* 250 MHz */
368};
369
370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
373 "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377 "uart0_synth_gate_clk", };
378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379 "uart1_synth_gate_clk", };
380static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
381static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
382 "osc_25m_clk", };
383static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
384 "gmac_phy_synth_gate_clk", };
385static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
386static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
387static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
388 "i2s_src_pad_clk", };
389static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
390static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
391};
392static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
393
394static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
395 "pll3_clk", };
396static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
397 "pll2_clk", };
398
399void __init spear1340_clk_init(void)
400{
401 struct clk *clk, *clk1;
402
403 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
404 clk_register_clkdev(clk, "apb_pclk", NULL);
405
406 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
407 32000);
408 clk_register_clkdev(clk, "osc_32k_clk", NULL);
409
410 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
411 24000000);
412 clk_register_clkdev(clk, "osc_24m_clk", NULL);
413
414 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
415 25000000);
416 clk_register_clkdev(clk, "osc_25m_clk", NULL);
417
418 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
419 CLK_IS_ROOT, 125000000);
420 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
421
422 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
423 CLK_IS_ROOT, 12288000);
424 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
425
426 /* clock derived from 32 KHz osc clk */
427 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
428 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
429 &_lock);
430 clk_register_clkdev(clk, NULL, "fc900000.rtc");
431
432 /* clock derived from 24 or 25 MHz osc clk */
433 /* vco-pll */
434 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
435 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
436 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
437 &_lock);
438 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
439 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
440 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
441 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
442 clk_register_clkdev(clk, "vco1_clk", NULL);
443 clk_register_clkdev(clk1, "pll1_clk", NULL);
444
445 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
446 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
447 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
448 &_lock);
449 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
450 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
451 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
452 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
453 clk_register_clkdev(clk, "vco2_clk", NULL);
454 clk_register_clkdev(clk1, "pll2_clk", NULL);
455
456 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
457 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
458 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
459 &_lock);
460 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
461 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
462 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
463 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
464 clk_register_clkdev(clk, "vco3_clk", NULL);
465 clk_register_clkdev(clk1, "pll3_clk", NULL);
466
467 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
468 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
469 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
470 clk_register_clkdev(clk, "vco4_clk", NULL);
471 clk_register_clkdev(clk1, "pll4_clk", NULL);
472
473 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
474 48000000);
475 clk_register_clkdev(clk, "pll5_clk", NULL);
476
477 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
478 25000000);
479 clk_register_clkdev(clk, "pll6_clk", NULL);
480
481 /* vco div n clocks */
482 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
483 2);
484 clk_register_clkdev(clk, "vco1div2_clk", NULL);
485
486 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
487 4);
488 clk_register_clkdev(clk, "vco1div4_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, "vco2div2_clk", NULL);
493
494 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
495 2);
496 clk_register_clkdev(clk, "vco3div2_clk", NULL);
497
498 /* peripherals */
499 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
500 128);
501 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
502 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
503 &_lock);
504 clk_register_clkdev(clk, NULL, "spear_thermal");
505
506 /* clock derived from pll4 clk */
507 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
508 1);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 /* clock derived from pll1 clk */
512 clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
513 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
514 ARRAY_SIZE(sys_synth_rtbl), &_lock);
515 clk_register_clkdev(clk, "sys_synth_clk", NULL);
516
517 clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
518 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
519 ARRAY_SIZE(amba_synth_rtbl), &_lock);
520 clk_register_clkdev(clk, "amba_synth_clk", NULL);
521
522 clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
523 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
524 SPEAR1340_SCLK_SRC_SEL_SHIFT,
525 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
526 clk_register_clkdev(clk, "sys_clk", NULL);
527
528 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
529 2);
530 clk_register_clkdev(clk, "cpu_clk", NULL);
531
532 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
533 3);
534 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
535
536 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
537 2);
538 clk_register_clkdev(clk, NULL, "ec800620.wdt");
539
540 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
541 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
542 SPEAR1340_HCLK_SRC_SEL_SHIFT,
543 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
544 clk_register_clkdev(clk, "ahb_clk", NULL);
545
546 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
547 2);
548 clk_register_clkdev(clk, "apb_clk", NULL);
549
550 /* gpt clocks */
551 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
552 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
553 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
554 &_lock);
555 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
556 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
557 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "gpt0");
560
561 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
562 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
563 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
564 &_lock);
565 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
566 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
567 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
568 &_lock);
569 clk_register_clkdev(clk, NULL, "gpt1");
570
571 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
572 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
573 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
574 &_lock);
575 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
576 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
577 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
578 &_lock);
579 clk_register_clkdev(clk, NULL, "gpt2");
580
581 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
582 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
583 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
584 &_lock);
585 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
586 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
587 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
588 &_lock);
589 clk_register_clkdev(clk, NULL, "gpt3");
590
591 /* others */
592 clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
593 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
594 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
595 clk_register_clkdev(clk, "uart0_synth_clk", NULL);
596 clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
597
598 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
599 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
600 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
601 &_lock);
602 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
603
604 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
606 &_lock);
607 clk_register_clkdev(clk, NULL, "e0000000.serial");
608
609 clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
610 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
611 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
612 clk_register_clkdev(clk, "uart1_synth_clk", NULL);
613 clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
614
615 clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
616 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
617 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
618 &_lock);
619 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
620
621 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
622 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
623 &_lock);
624 clk_register_clkdev(clk, NULL, "b4100000.serial");
625
626 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
627 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
628 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
629 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
630 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
631
632 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
633 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
634 &_lock);
635 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
636
637 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
638 "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
641 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
642
643 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
644 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
645 &_lock);
646 clk_register_clkdev(clk, NULL, "b2800000.cf");
647 clk_register_clkdev(clk, NULL, "arasan_xd");
648
649 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
650 "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
651 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
652 clk_register_clkdev(clk, "c3_synth_clk", NULL);
653 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
654
655 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
656 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
657 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
658 &_lock);
659 clk_register_clkdev(clk, "c3_mux_clk", NULL);
660
661 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
662 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
663 &_lock);
664 clk_register_clkdev(clk, NULL, "c3");
665
666 /* gmac */
667 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
668 gmac_phy_input_parents,
669 ARRAY_SIZE(gmac_phy_input_parents), 0,
670 SPEAR1340_GMAC_CLK_CFG,
671 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
672 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
673 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
674
675 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
676 "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
677 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
678 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
679 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
680
681 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
682 ARRAY_SIZE(gmac_phy_parents), 0,
683 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
684 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
685 clk_register_clkdev(clk, NULL, "stmmacphy.0");
686
687 /* clcd */
688 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
689 ARRAY_SIZE(clcd_synth_parents), 0,
690 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
691 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
692 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
693
694 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
695 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
696 ARRAY_SIZE(clcd_rtbl), &_lock);
697 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
698
699 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
700 ARRAY_SIZE(clcd_pixel_parents), 0,
701 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
702 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
703 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
704
705 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
706 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
707 &_lock);
708 clk_register_clkdev(clk, "clcd_clk", NULL);
709
710 /* i2s */
711 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
712 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
713 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
714 0, &_lock);
715 clk_register_clkdev(clk, "i2s_src_clk", NULL);
716
717 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
718 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
719 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
720 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
721
722 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
723 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
724 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
725 &_lock);
726 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
727
728 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
729 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
732
733 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
734 "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
735 &i2s_sclk_masks, i2s_sclk_rtbl,
736 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
737 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
738 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
739
740 /* clock derived from ahb clk */
741 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
742 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
743 &_lock);
744 clk_register_clkdev(clk, NULL, "e0280000.i2c");
745
746 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
748 &_lock);
749 clk_register_clkdev(clk, NULL, "b4000000.i2c");
750
751 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
752 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
753 &_lock);
754 clk_register_clkdev(clk, NULL, "ea800000.dma");
755 clk_register_clkdev(clk, NULL, "eb000000.dma");
756
757 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
758 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
759 &_lock);
760 clk_register_clkdev(clk, NULL, "e2000000.eth");
761
762 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
763 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "b0000000.flash");
766
767 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
768 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "ea000000.flash");
771
772 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
773 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, "usbh.0_clk", NULL);
776
777 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
778 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, "usbh.1_clk", NULL);
781
782 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
783 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "uoc");
786
787 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
788 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
789 0, &_lock);
790 clk_register_clkdev(clk, NULL, "dw_pcie");
791 clk_register_clkdev(clk, NULL, "ahci");
792
793 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
794 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
795 &_lock);
796 clk_register_clkdev(clk, "sysram0_clk", NULL);
797
798 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
799 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
800 &_lock);
801 clk_register_clkdev(clk, "sysram1_clk", NULL);
802
803 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
804 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
805 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
806 clk_register_clkdev(clk, "adc_synth_clk", NULL);
807 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
808
809 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
810 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
811 &_lock);
812 clk_register_clkdev(clk, NULL, "adc_clk");
813
814 /* clock derived from apb clk */
815 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
817 &_lock);
818 clk_register_clkdev(clk, NULL, "e0100000.spi");
819
820 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
821 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
822 &_lock);
823 clk_register_clkdev(clk, NULL, "e0600000.gpio");
824
825 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
826 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, NULL, "e0680000.gpio");
829
830 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, NULL, "b2400000.i2s");
834
835 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, NULL, "b2000000.i2s");
839
840 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
841 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, NULL, "e0300000.kbd");
844
845 /* RAS clks */
846 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
847 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
848 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
849 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
850 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
851
852 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
853 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
854 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
855 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
856 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
857
858 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
859 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
860 &_lock);
861 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
862
863 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
864 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
865 &_lock);
866 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
867
868 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
869 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
870 &_lock);
871 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
872
873 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
874 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
875 &_lock);
876 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
877
878 clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
879 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
880 &_lock);
881 clk_register_clkdev(clk, NULL, "mali");
882
883 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
884 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
885 &_lock);
886 clk_register_clkdev(clk, NULL, "spear_cec.0");
887
888 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
889 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
890 &_lock);
891 clk_register_clkdev(clk, NULL, "spear_cec.1");
892
893 clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
894 ARRAY_SIZE(spdif_out_parents), 0,
895 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
896 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
898
899 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
900 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
901 0, &_lock);
902 clk_register_clkdev(clk, NULL, "spdif-out");
903
904 clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
905 ARRAY_SIZE(spdif_in_parents), 0,
906 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
907 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
908 clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
909
910 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
911 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "spdif-in");
914
915 clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
916 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
917 &_lock);
918 clk_register_clkdev(clk, NULL, "acp_clk");
919
920 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
921 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
922 &_lock);
923 clk_register_clkdev(clk, NULL, "plgpio");
924
925 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
926 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
927 0, &_lock);
928 clk_register_clkdev(clk, NULL, "video_dec");
929
930 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
932 0, &_lock);
933 clk_register_clkdev(clk, NULL, "video_enc");
934
935 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
937 &_lock);
938 clk_register_clkdev(clk, NULL, "spear_vip");
939
940 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
941 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
942 &_lock);
943 clk_register_clkdev(clk, NULL, "spear_camif.0");
944
945 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
946 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
947 &_lock);
948 clk_register_clkdev(clk, NULL, "spear_camif.1");
949
950 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
951 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
952 &_lock);
953 clk_register_clkdev(clk, NULL, "spear_camif.2");
954
955 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
956 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
957 &_lock);
958 clk_register_clkdev(clk, NULL, "spear_camif.3");
959
960 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
961 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
962 &_lock);
963 clk_register_clkdev(clk, NULL, "pwm");
964}
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
new file mode 100644
index 000000000000..440bb3e4c971
--- /dev/null
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -0,0 +1,612 @@
1/*
2 * SPEAr3xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/of_platform.h>
17#include <linux/spinlock_types.h>
18#include <mach/misc_regs.h>
19#include "clk.h"
20
21static DEFINE_SPINLOCK(_lock);
22
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL2_CTR (MISC_BASE + 0x014)
26#define PLL2_FRQ (MISC_BASE + 0x018)
27#define PLL_CLK_CFG (MISC_BASE + 0x020)
28 /* PLL_CLK_CFG register masks */
29 #define MCTR_CLK_SHIFT 28
30 #define MCTR_CLK_MASK 3
31
32#define CORE_CLK_CFG (MISC_BASE + 0x024)
33 /* CORE CLK CFG register masks */
34 #define GEN_SYNTH2_3_CLK_SHIFT 18
35 #define GEN_SYNTH2_3_CLK_MASK 1
36
37 #define HCLK_RATIO_SHIFT 10
38 #define HCLK_RATIO_MASK 2
39 #define PCLK_RATIO_SHIFT 8
40 #define PCLK_RATIO_MASK 2
41
42#define PERIP_CLK_CFG (MISC_BASE + 0x028)
43 /* PERIP_CLK_CFG register masks */
44 #define UART_CLK_SHIFT 4
45 #define UART_CLK_MASK 1
46 #define FIRDA_CLK_SHIFT 5
47 #define FIRDA_CLK_MASK 2
48 #define GPT0_CLK_SHIFT 8
49 #define GPT1_CLK_SHIFT 11
50 #define GPT2_CLK_SHIFT 12
51 #define GPT_CLK_MASK 1
52
53#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
54 /* PERIP1_CLK_ENB register masks */
55 #define UART_CLK_ENB 3
56 #define SSP_CLK_ENB 5
57 #define I2C_CLK_ENB 7
58 #define JPEG_CLK_ENB 8
59 #define FIRDA_CLK_ENB 10
60 #define GPT1_CLK_ENB 11
61 #define GPT2_CLK_ENB 12
62 #define ADC_CLK_ENB 15
63 #define RTC_CLK_ENB 17
64 #define GPIO_CLK_ENB 18
65 #define DMA_CLK_ENB 19
66 #define SMI_CLK_ENB 21
67 #define GMAC_CLK_ENB 23
68 #define USBD_CLK_ENB 24
69 #define USBH_CLK_ENB 25
70 #define C3_CLK_ENB 31
71
72#define RAS_CLK_ENB (MISC_BASE + 0x034)
73 #define RAS_AHB_CLK_ENB 0
74 #define RAS_PLL1_CLK_ENB 1
75 #define RAS_APB_CLK_ENB 2
76 #define RAS_32K_CLK_ENB 3
77 #define RAS_24M_CLK_ENB 4
78 #define RAS_48M_CLK_ENB 5
79 #define RAS_PLL2_CLK_ENB 7
80 #define RAS_SYNT0_CLK_ENB 8
81 #define RAS_SYNT1_CLK_ENB 9
82 #define RAS_SYNT2_CLK_ENB 10
83 #define RAS_SYNT3_CLK_ENB 11
84
85#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
86#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
87#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
88#define AMEM_CLK_CFG (MISC_BASE + 0x050)
89 #define AMEM_CLK_ENB 0
90
91#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
92#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
93#define UART_CLK_SYNT (MISC_BASE + 0x064)
94#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
95#define GEN0_CLK_SYNT (MISC_BASE + 0x06C)
96#define GEN1_CLK_SYNT (MISC_BASE + 0x070)
97#define GEN2_CLK_SYNT (MISC_BASE + 0x074)
98#define GEN3_CLK_SYNT (MISC_BASE + 0x078)
99
100/* pll rate configuration table, in ascending order of rates */
101static struct pll_rate_tbl pll_rtbl[] = {
102 {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
103 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
104 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
105};
106
107/* aux rate configuration table, in ascending order of rates */
108static struct aux_rate_tbl aux_rtbl[] = {
109 /* For PLL1 = 332 MHz */
110 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
111 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
112 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
113 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
114};
115
116/* gpt rate configuration table, in ascending order of rates */
117static struct gpt_rate_tbl gpt_rtbl[] = {
118 /* For pll1 = 332 MHz */
119 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
120 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
121 {.mscale = 1, .nscale = 0}, /* 83 MHz */
122};
123
124/* clock parents */
125static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
126static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
127};
128static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
129static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
130static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
131static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
132static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
133 "pll2_clk", };
134
135#ifdef CONFIG_MACH_SPEAR300
136static void __init spear300_clk_init(void)
137{
138 struct clk *clk;
139
140 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
141 1, 1);
142 clk_register_clkdev(clk, NULL, "60000000.clcd");
143
144 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
145 1);
146 clk_register_clkdev(clk, NULL, "94000000.flash");
147
148 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
149 1);
150 clk_register_clkdev(clk, NULL, "70000000.sdhci");
151
152 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
153 1);
154 clk_register_clkdev(clk, NULL, "a9000000.gpio");
155
156 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
157 1);
158 clk_register_clkdev(clk, NULL, "a0000000.kbd");
159}
160#endif
161
162/* array of all spear 310 clock lookups */
163#ifdef CONFIG_MACH_SPEAR310
164static void __init spear310_clk_init(void)
165{
166 struct clk *clk;
167
168 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
169 1);
170 clk_register_clkdev(clk, "emi", NULL);
171
172 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
173 1);
174 clk_register_clkdev(clk, NULL, "44000000.flash");
175
176 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
177 1);
178 clk_register_clkdev(clk, NULL, "tdm");
179
180 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
181 1);
182 clk_register_clkdev(clk, NULL, "b2000000.serial");
183
184 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
185 1);
186 clk_register_clkdev(clk, NULL, "b2080000.serial");
187
188 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
189 1);
190 clk_register_clkdev(clk, NULL, "b2100000.serial");
191
192 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
193 1);
194 clk_register_clkdev(clk, NULL, "b2180000.serial");
195
196 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
197 1);
198 clk_register_clkdev(clk, NULL, "b2200000.serial");
199}
200#endif
201
202/* array of all spear 320 clock lookups */
203#ifdef CONFIG_MACH_SPEAR320
204 #define SMII_PCLK_SHIFT 18
205 #define SMII_PCLK_MASK 2
206 #define SMII_PCLK_VAL_PAD 0x0
207 #define SMII_PCLK_VAL_PLL2 0x1
208 #define SMII_PCLK_VAL_SYNTH0 0x2
209 #define SDHCI_PCLK_SHIFT 15
210 #define SDHCI_PCLK_MASK 1
211 #define SDHCI_PCLK_VAL_48M 0x0
212 #define SDHCI_PCLK_VAL_SYNTH3 0x1
213 #define I2S_REF_PCLK_SHIFT 8
214 #define I2S_REF_PCLK_MASK 1
215 #define I2S_REF_PCLK_SYNTH_VAL 0x1
216 #define I2S_REF_PCLK_PLL2_VAL 0x0
217 #define UART1_PCLK_SHIFT 6
218 #define UART1_PCLK_MASK 1
219 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
220 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
221
222static const char *i2s_ref_parents[] = { "ras_pll2_clk",
223 "ras_gen2_synth_gate_clk", };
224static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
225 "ras_gen3_synth_gate_clk",
226};
227static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
228 "ras_gen0_synth_gate_clk", };
229static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
230};
231
232static void __init spear320_clk_init(void)
233{
234 struct clk *clk;
235
236 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
237 CLK_IS_ROOT, 125000000);
238 clk_register_clkdev(clk, "smii_125m_pad", NULL);
239
240 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
241 1, 1);
242 clk_register_clkdev(clk, NULL, "90000000.clcd");
243
244 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
245 1);
246 clk_register_clkdev(clk, "emi", NULL);
247
248 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
249 1);
250 clk_register_clkdev(clk, NULL, "4c000000.flash");
251
252 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
253 1);
254 clk_register_clkdev(clk, NULL, "a7000000.i2c");
255
256 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
257 1);
258 clk_register_clkdev(clk, "pwm", NULL);
259
260 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
261 1);
262 clk_register_clkdev(clk, NULL, "a5000000.spi");
263
264 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
265 1);
266 clk_register_clkdev(clk, NULL, "a6000000.spi");
267
268 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
269 1);
270 clk_register_clkdev(clk, NULL, "c_can_platform.0");
271
272 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
273 1);
274 clk_register_clkdev(clk, NULL, "c_can_platform.1");
275
276 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
277 1);
278 clk_register_clkdev(clk, NULL, "i2s");
279
280 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
281 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
282 I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
283 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
284
285 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
286 4);
287 clk_register_clkdev(clk, "i2s_sclk", NULL);
288
289 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
290 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
291 SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
292 &_lock);
293 clk_register_clkdev(clk, NULL, "a9300000.serial");
294
295 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
296 ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
297 SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
298 clk_register_clkdev(clk, NULL, "70000000.sdhci");
299
300 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
301 ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
302 SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
303 clk_register_clkdev(clk, NULL, "smii_pclk");
304
305 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
306 clk_register_clkdev(clk, NULL, "smii");
307
308 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
309 ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
310 UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
311 clk_register_clkdev(clk, NULL, "a3000000.serial");
312
313 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
314 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
315 SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
316 &_lock);
317 clk_register_clkdev(clk, NULL, "a4000000.serial");
318
319 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
320 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
321 SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
322 &_lock);
323 clk_register_clkdev(clk, NULL, "a9100000.serial");
324
325 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
326 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
327 SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
328 &_lock);
329 clk_register_clkdev(clk, NULL, "a9200000.serial");
330
331 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
332 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
333 SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
334 &_lock);
335 clk_register_clkdev(clk, NULL, "60000000.serial");
336
337 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
338 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
339 SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
340 &_lock);
341 clk_register_clkdev(clk, NULL, "60100000.serial");
342}
343#endif
344
345void __init spear3xx_clk_init(void)
346{
347 struct clk *clk, *clk1;
348
349 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
350 clk_register_clkdev(clk, "apb_pclk", NULL);
351
352 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
353 32000);
354 clk_register_clkdev(clk, "osc_32k_clk", NULL);
355
356 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
357 24000000);
358 clk_register_clkdev(clk, "osc_24m_clk", NULL);
359
360 /* clock derived from 32 KHz osc clk */
361 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
362 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
363 clk_register_clkdev(clk, NULL, "fc900000.rtc");
364
365 /* clock derived from 24 MHz osc clk */
366 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
367 48000000);
368 clk_register_clkdev(clk, "pll3_48m_clk", NULL);
369
370 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
371 1);
372 clk_register_clkdev(clk, NULL, "fc880000.wdt");
373
374 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
375 "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
376 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
377 clk_register_clkdev(clk, "vco1_clk", NULL);
378 clk_register_clkdev(clk1, "pll1_clk", NULL);
379
380 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
381 "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
382 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
383 clk_register_clkdev(clk, "vco2_clk", NULL);
384 clk_register_clkdev(clk1, "pll2_clk", NULL);
385
386 /* clock derived from pll1 clk */
387 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
388 clk_register_clkdev(clk, "cpu_clk", NULL);
389
390 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
391 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
392 HCLK_RATIO_MASK, 0, &_lock);
393 clk_register_clkdev(clk, "ahb_clk", NULL);
394
395 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
396 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
397 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
398 clk_register_clkdev(clk, "uart_synth_clk", NULL);
399 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
400
401 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
402 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
403 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
404 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
405
406 clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
407 PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
408 clk_register_clkdev(clk, NULL, "d0000000.serial");
409
410 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
411 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
412 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
413 clk_register_clkdev(clk, "firda_synth_clk", NULL);
414 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
415
416 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
417 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
418 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
419 clk_register_clkdev(clk, "firda_mux_clk", NULL);
420
421 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
422 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
423 clk_register_clkdev(clk, NULL, "firda");
424
425 /* gpt clocks */
426 clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
427 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
428 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
429 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
430 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
431 clk_register_clkdev(clk, NULL, "gpt0");
432
433 clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
434 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
435 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
436 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
437 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
438 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
439 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
440 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
441 clk_register_clkdev(clk, NULL, "gpt1");
442
443 clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
444 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
445 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
446 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
447 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
448 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
449 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
450 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
451 clk_register_clkdev(clk, NULL, "gpt2");
452
453 /* general synths clocks */
454 clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
455 "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
456 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
457 clk_register_clkdev(clk, "gen0_synth_clk", NULL);
458 clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
459
460 clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
461 "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
462 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
463 clk_register_clkdev(clk, "gen1_synth_clk", NULL);
464 clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
465
466 clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
467 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
468 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
469 &_lock);
470 clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
471
472 clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
473 "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
474 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
475 clk_register_clkdev(clk, "gen2_synth_clk", NULL);
476 clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
477
478 clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
479 "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
480 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
481 clk_register_clkdev(clk, "gen3_synth_clk", NULL);
482 clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
483
484 /* clock derived from pll3 clk */
485 clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
486 PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
487 clk_register_clkdev(clk, "usbh_clk", NULL);
488
489 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
490 1);
491 clk_register_clkdev(clk, "usbh.0_clk", NULL);
492
493 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
494 1);
495 clk_register_clkdev(clk, "usbh.1_clk", NULL);
496
497 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
498 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
499 clk_register_clkdev(clk, NULL, "designware_udc");
500
501 /* clock derived from ahb clk */
502 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
503 1);
504 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
505
506 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
507 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
508 MCTR_CLK_MASK, 0, &_lock);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
512 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
513 PCLK_RATIO_MASK, 0, &_lock);
514 clk_register_clkdev(clk, "apb_clk", NULL);
515
516 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
517 AMEM_CLK_ENB, 0, &_lock);
518 clk_register_clkdev(clk, "amem_clk", NULL);
519
520 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
521 C3_CLK_ENB, 0, &_lock);
522 clk_register_clkdev(clk, NULL, "c3_clk");
523
524 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
525 DMA_CLK_ENB, 0, &_lock);
526 clk_register_clkdev(clk, NULL, "fc400000.dma");
527
528 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
529 GMAC_CLK_ENB, 0, &_lock);
530 clk_register_clkdev(clk, NULL, "e0800000.eth");
531
532 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
533 I2C_CLK_ENB, 0, &_lock);
534 clk_register_clkdev(clk, NULL, "d0180000.i2c");
535
536 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
537 JPEG_CLK_ENB, 0, &_lock);
538 clk_register_clkdev(clk, NULL, "jpeg");
539
540 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
541 SMI_CLK_ENB, 0, &_lock);
542 clk_register_clkdev(clk, NULL, "fc000000.flash");
543
544 /* clock derived from apb clk */
545 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
546 ADC_CLK_ENB, 0, &_lock);
547 clk_register_clkdev(clk, NULL, "adc");
548
549 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
550 GPIO_CLK_ENB, 0, &_lock);
551 clk_register_clkdev(clk, NULL, "fc980000.gpio");
552
553 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
554 SSP_CLK_ENB, 0, &_lock);
555 clk_register_clkdev(clk, NULL, "d0100000.spi");
556
557 /* RAS clk enable */
558 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
559 RAS_AHB_CLK_ENB, 0, &_lock);
560 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
561
562 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
563 RAS_APB_CLK_ENB, 0, &_lock);
564 clk_register_clkdev(clk, "ras_apb_clk", NULL);
565
566 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
567 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
568 clk_register_clkdev(clk, "ras_32k_clk", NULL);
569
570 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
571 RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
572 clk_register_clkdev(clk, "ras_24m_clk", NULL);
573
574 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
575 RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
576 clk_register_clkdev(clk, "ras_pll1_clk", NULL);
577
578 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
579 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
581
582 clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
583 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
584 clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
585
586 clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
587 "gen0_synth_gate_clk", 0, RAS_CLK_ENB,
588 RAS_SYNT0_CLK_ENB, 0, &_lock);
589 clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
590
591 clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
592 "gen1_synth_gate_clk", 0, RAS_CLK_ENB,
593 RAS_SYNT1_CLK_ENB, 0, &_lock);
594 clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
595
596 clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
597 "gen2_synth_gate_clk", 0, RAS_CLK_ENB,
598 RAS_SYNT2_CLK_ENB, 0, &_lock);
599 clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
600
601 clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
602 "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
603 RAS_SYNT3_CLK_ENB, 0, &_lock);
604 clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
605
606 if (of_machine_is_compatible("st,spear300"))
607 spear300_clk_init();
608 else if (of_machine_is_compatible("st,spear310"))
609 spear310_clk_init();
610 else if (of_machine_is_compatible("st,spear320"))
611 spear320_clk_init();
612}
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
new file mode 100644
index 000000000000..f9a20b382304
--- /dev/null
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -0,0 +1,342 @@
1/*
2 * SPEAr6xx machines clock framework source file
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/io.h>
15#include <linux/spinlock_types.h>
16#include <mach/misc_regs.h>
17#include "clk.h"
18
19static DEFINE_SPINLOCK(_lock);
20
21#define PLL1_CTR (MISC_BASE + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C)
23#define PLL2_CTR (MISC_BASE + 0x014)
24#define PLL2_FRQ (MISC_BASE + 0x018)
25#define PLL_CLK_CFG (MISC_BASE + 0x020)
26 /* PLL_CLK_CFG register masks */
27 #define MCTR_CLK_SHIFT 28
28 #define MCTR_CLK_MASK 3
29
30#define CORE_CLK_CFG (MISC_BASE + 0x024)
31 /* CORE CLK CFG register masks */
32 #define HCLK_RATIO_SHIFT 10
33 #define HCLK_RATIO_MASK 2
34 #define PCLK_RATIO_SHIFT 8
35 #define PCLK_RATIO_MASK 2
36
37#define PERIP_CLK_CFG (MISC_BASE + 0x028)
38 /* PERIP_CLK_CFG register masks */
39 #define CLCD_CLK_SHIFT 2
40 #define CLCD_CLK_MASK 2
41 #define UART_CLK_SHIFT 4
42 #define UART_CLK_MASK 1
43 #define FIRDA_CLK_SHIFT 5
44 #define FIRDA_CLK_MASK 2
45 #define GPT0_CLK_SHIFT 8
46 #define GPT1_CLK_SHIFT 10
47 #define GPT2_CLK_SHIFT 11
48 #define GPT3_CLK_SHIFT 12
49 #define GPT_CLK_MASK 1
50
51#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
52 /* PERIP1_CLK_ENB register masks */
53 #define UART0_CLK_ENB 3
54 #define UART1_CLK_ENB 4
55 #define SSP0_CLK_ENB 5
56 #define SSP1_CLK_ENB 6
57 #define I2C_CLK_ENB 7
58 #define JPEG_CLK_ENB 8
59 #define FSMC_CLK_ENB 9
60 #define FIRDA_CLK_ENB 10
61 #define GPT2_CLK_ENB 11
62 #define GPT3_CLK_ENB 12
63 #define GPIO2_CLK_ENB 13
64 #define SSP2_CLK_ENB 14
65 #define ADC_CLK_ENB 15
66 #define GPT1_CLK_ENB 11
67 #define RTC_CLK_ENB 17
68 #define GPIO1_CLK_ENB 18
69 #define DMA_CLK_ENB 19
70 #define SMI_CLK_ENB 21
71 #define CLCD_CLK_ENB 22
72 #define GMAC_CLK_ENB 23
73 #define USBD_CLK_ENB 24
74 #define USBH0_CLK_ENB 25
75 #define USBH1_CLK_ENB 26
76
77#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
78#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
79#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
80
81#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
82#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
83#define UART_CLK_SYNT (MISC_BASE + 0x064)
84
85/* vco rate configuration table, in ascending order of rates */
86static struct pll_rate_tbl pll_rtbl[] = {
87 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
88 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
89 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
90};
91
92/* aux rate configuration table, in ascending order of rates */
93static struct aux_rate_tbl aux_rtbl[] = {
94 /* For PLL1 = 332 MHz */
95 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
96 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
98};
99
100static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", };
101static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
102};
103static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
104static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", };
105static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
106static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
107static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
108 "pll2_clk", };
109
110/* gpt rate configuration table, in ascending order of rates */
111static struct gpt_rate_tbl gpt_rtbl[] = {
112 /* For pll1 = 332 MHz */
113 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
114 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
115 {.mscale = 1, .nscale = 0}, /* 83 MHz */
116};
117
118void __init spear6xx_clk_init(void)
119{
120 struct clk *clk, *clk1;
121
122 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
123 clk_register_clkdev(clk, "apb_pclk", NULL);
124
125 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
126 32000);
127 clk_register_clkdev(clk, "osc_32k_clk", NULL);
128
129 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
130 30000000);
131 clk_register_clkdev(clk, "osc_30m_clk", NULL);
132
133 /* clock derived from 32 KHz osc clk */
134 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
135 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
136 clk_register_clkdev(clk, NULL, "rtc-spear");
137
138 /* clock derived from 30 MHz osc clk */
139 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
140 48000000);
141 clk_register_clkdev(clk, "pll3_48m_clk", NULL);
142
143 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
144 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
145 &_lock, &clk1, NULL);
146 clk_register_clkdev(clk, "vco1_clk", NULL);
147 clk_register_clkdev(clk1, "pll1_clk", NULL);
148
149 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
150 "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
151 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
152 clk_register_clkdev(clk, "vco2_clk", NULL);
153 clk_register_clkdev(clk1, "pll2_clk", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
156 1);
157 clk_register_clkdev(clk, NULL, "wdt");
158
159 /* clock derived from pll1 clk */
160 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
161 clk_register_clkdev(clk, "cpu_clk", NULL);
162
163 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
164 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
165 HCLK_RATIO_MASK, 0, &_lock);
166 clk_register_clkdev(clk, "ahb_clk", NULL);
167
168 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
169 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
170 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
171 clk_register_clkdev(clk, "uart_synth_clk", NULL);
172 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
173
174 clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents,
175 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
176 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
177 clk_register_clkdev(clk, "uart_mux_clk", NULL);
178
179 clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0,
180 PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock);
181 clk_register_clkdev(clk, NULL, "d0000000.serial");
182
183 clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0,
184 PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock);
185 clk_register_clkdev(clk, NULL, "d0080000.serial");
186
187 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
188 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
189 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
190 clk_register_clkdev(clk, "firda_synth_clk", NULL);
191 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
192
193 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
194 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
195 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
196 clk_register_clkdev(clk, "firda_mux_clk", NULL);
197
198 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
199 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
200 clk_register_clkdev(clk, NULL, "firda");
201
202 clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk",
203 "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl,
204 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
205 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
206 clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL);
207
208 clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents,
209 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
210 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
211 clk_register_clkdev(clk, "clcd_mux_clk", NULL);
212
213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0,
214 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
215 clk_register_clkdev(clk, NULL, "clcd");
216
217 /* gpt clocks */
218 clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
219 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
220 clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL);
221
222 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents,
223 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
224 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
225 clk_register_clkdev(clk, NULL, "gpt0");
226
227 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents,
228 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
229 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
230 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
231
232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
233 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
234 clk_register_clkdev(clk, NULL, "gpt1");
235
236 clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
237 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
238 clk_register_clkdev(clk, "gpt2_synth_clk", NULL);
239
240 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
241 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
242 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
243 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
244
245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
246 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
247 clk_register_clkdev(clk, NULL, "gpt2");
248
249 clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
250 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
251 clk_register_clkdev(clk, "gpt3_synth_clk", NULL);
252
253 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents,
254 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
255 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
256 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
257
258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
259 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
260 clk_register_clkdev(clk, NULL, "gpt3");
261
262 /* clock derived from pll3 clk */
263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0,
264 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
265 clk_register_clkdev(clk, NULL, "usbh.0_clk");
266
267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0,
268 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
269 clk_register_clkdev(clk, NULL, "usbh.1_clk");
270
271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
272 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
273 clk_register_clkdev(clk, NULL, "designware_udc");
274
275 /* clock derived from ahb clk */
276 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
277 1);
278 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
279
280 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
281 ARRAY_SIZE(ddr_parents),
282 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0,
283 &_lock);
284 clk_register_clkdev(clk, "ddr_clk", NULL);
285
286 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
287 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
288 PCLK_RATIO_MASK, 0, &_lock);
289 clk_register_clkdev(clk, "apb_clk", NULL);
290
291 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
292 DMA_CLK_ENB, 0, &_lock);
293 clk_register_clkdev(clk, NULL, "fc400000.dma");
294
295 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
296 FSMC_CLK_ENB, 0, &_lock);
297 clk_register_clkdev(clk, NULL, "d1800000.flash");
298
299 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
300 GMAC_CLK_ENB, 0, &_lock);
301 clk_register_clkdev(clk, NULL, "gmac");
302
303 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
304 I2C_CLK_ENB, 0, &_lock);
305 clk_register_clkdev(clk, NULL, "d0200000.i2c");
306
307 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
308 JPEG_CLK_ENB, 0, &_lock);
309 clk_register_clkdev(clk, NULL, "jpeg");
310
311 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
312 SMI_CLK_ENB, 0, &_lock);
313 clk_register_clkdev(clk, NULL, "fc000000.flash");
314
315 /* clock derived from apb clk */
316 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
317 ADC_CLK_ENB, 0, &_lock);
318 clk_register_clkdev(clk, NULL, "adc");
319
320 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
321 clk_register_clkdev(clk, NULL, "f0100000.gpio");
322
323 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
324 GPIO1_CLK_ENB, 0, &_lock);
325 clk_register_clkdev(clk, NULL, "fc980000.gpio");
326
327 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
328 GPIO2_CLK_ENB, 0, &_lock);
329 clk_register_clkdev(clk, NULL, "d8100000.gpio");
330
331 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
332 SSP0_CLK_ENB, 0, &_lock);
333 clk_register_clkdev(clk, NULL, "ssp-pl022.0");
334
335 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
336 SSP1_CLK_ENB, 0, &_lock);
337 clk_register_clkdev(clk, NULL, "ssp-pl022.1");
338
339 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
340 SSP2_CLK_ENB, 0, &_lock);
341 clk_register_clkdev(clk, NULL, "ssp-pl022.2");
342}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 01:08:05 -0500