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path: root/drivers/clk/zynq/clkc.c
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Diffstat (limited to 'drivers/clk/zynq/clkc.c')
-rw-r--r--drivers/clk/zynq/clkc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index c812b93a52b2..52c09afdcfb7 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -149,7 +149,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
149 clks[fclk] = clk_register_gate(NULL, clk_name, 149 clks[fclk] = clk_register_gate(NULL, clk_name,
150 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 150 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
151 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 151 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
152 enable_reg = readl(fclk_gate_reg) & 1; 152 enable_reg = clk_readl(fclk_gate_reg) & 1;
153 if (enable && !enable_reg) { 153 if (enable && !enable_reg) {
154 if (clk_prepare_enable(clks[fclk])) 154 if (clk_prepare_enable(clks[fclk]))
155 pr_warn("%s: FCLK%u enable failed\n", __func__, 155 pr_warn("%s: FCLK%u enable failed\n", __func__,
@@ -278,7 +278,7 @@ static void __init zynq_clk_setup(struct device_node *np)
278 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 278 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
279 279
280 /* CPU clocks */ 280 /* CPU clocks */
281 tmp = readl(SLCR_621_TRUE) & 1; 281 tmp = clk_readl(SLCR_621_TRUE) & 1;
282 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 282 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
283 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 283 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
284 &armclk_lock); 284 &armclk_lock);