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path: root/drivers/clk/zynq/clkc.c
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Diffstat (limited to 'drivers/clk/zynq/clkc.c')
-rw-r--r--drivers/clk/zynq/clkc.c82
1 files changed, 48 insertions, 34 deletions
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 089d3e30e221..cc40fe64f2dc 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -125,8 +125,9 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
125 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 125 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
126 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 126 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
127 127
128 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 128 clk = clk_register_mux(NULL, mux_name, parents, 4,
129 fclk_ctrl_reg, 4, 2, 0, fclk_lock); 129 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
130 fclk_lock);
130 131
131 clk = clk_register_divider(NULL, div0_name, mux_name, 132 clk = clk_register_divider(NULL, div0_name, mux_name,
132 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 133 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
@@ -168,8 +169,8 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
168 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 169 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
169 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 170 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
170 171
171 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 172 clk = clk_register_mux(NULL, mux_name, parents, 4,
172 clk_ctrl, 4, 2, 0, lock); 173 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
173 174
174 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 175 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
175 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 176 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
@@ -236,25 +237,26 @@ static void __init zynq_clk_setup(struct device_node *np)
236 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 237 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
237 SLCR_PLL_STATUS, 0, &armpll_lock); 238 SLCR_PLL_STATUS, 0, &armpll_lock);
238 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 239 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
239 armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, 240 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
240 &armpll_lock); 241 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
241 242
242 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 243 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
243 SLCR_PLL_STATUS, 1, &ddrpll_lock); 244 SLCR_PLL_STATUS, 1, &ddrpll_lock);
244 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 245 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
245 ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, 246 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
246 &ddrpll_lock); 247 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
247 248
248 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 249 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
249 SLCR_PLL_STATUS, 2, &iopll_lock); 250 SLCR_PLL_STATUS, 2, &iopll_lock);
250 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 251 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
251 iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, 252 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
252 &iopll_lock); 253 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
253 254
254 /* CPU clocks */ 255 /* CPU clocks */
255 tmp = readl(SLCR_621_TRUE) & 1; 256 tmp = readl(SLCR_621_TRUE) & 1;
256 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, 257 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
257 SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); 258 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
259 &armclk_lock);
258 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 260 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
259 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 261 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
260 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 262 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
@@ -293,8 +295,9 @@ static void __init zynq_clk_setup(struct device_node *np)
293 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 295 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
294 } 296 }
295 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 297 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
296 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, 298 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
297 SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock); 299 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
300 &swdtclk_lock);
298 301
299 /* DDR clocks */ 302 /* DDR clocks */
300 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 303 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@ -356,8 +359,9 @@ static void __init zynq_clk_setup(struct device_node *np)
356 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 359 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
357 idx); 360 idx);
358 } 361 }
359 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, 362 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
360 SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); 363 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
364 &gem0clk_lock);
361 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 365 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
362 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 366 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
363 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 367 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
@@ -366,7 +370,8 @@ static void __init zynq_clk_setup(struct device_node *np)
366 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 370 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
367 &gem0clk_lock); 371 &gem0clk_lock);
368 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 372 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
369 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0, 373 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
374 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
370 &gem0clk_lock); 375 &gem0clk_lock);
371 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 376 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
372 "gem0_emio_mux", CLK_SET_RATE_PARENT, 377 "gem0_emio_mux", CLK_SET_RATE_PARENT,
@@ -379,8 +384,9 @@ static void __init zynq_clk_setup(struct device_node *np)
379 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 384 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
380 idx); 385 idx);
381 } 386 }
382 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, 387 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
383 SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); 388 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
389 &gem1clk_lock);
384 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 390 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
385 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 391 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
386 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 392 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
@@ -389,7 +395,8 @@ static void __init zynq_clk_setup(struct device_node *np)
389 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 395 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
390 &gem1clk_lock); 396 &gem1clk_lock);
391 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 397 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
392 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0, 398 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
399 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
393 &gem1clk_lock); 400 &gem1clk_lock);
394 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 401 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
395 "gem1_emio_mux", CLK_SET_RATE_PARENT, 402 "gem1_emio_mux", CLK_SET_RATE_PARENT,
@@ -409,8 +416,9 @@ static void __init zynq_clk_setup(struct device_node *np)
409 can_mio_mux_parents[i] = dummy_nm; 416 can_mio_mux_parents[i] = dummy_nm;
410 } 417 }
411 kfree(clk_name); 418 kfree(clk_name);
412 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, 419 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
413 SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); 420 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
421 &canclk_lock);
414 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 422 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
415 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 423 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
416 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 424 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
@@ -425,17 +433,21 @@ static void __init zynq_clk_setup(struct device_node *np)
425 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 433 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
426 &canclk_lock); 434 &canclk_lock);
427 clk = clk_register_mux(NULL, "can0_mio_mux", 435 clk = clk_register_mux(NULL, "can0_mio_mux",
428 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 436 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
429 SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); 437 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
438 &canmioclk_lock);
430 clk = clk_register_mux(NULL, "can1_mio_mux", 439 clk = clk_register_mux(NULL, "can1_mio_mux",
431 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 440 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
432 SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); 441 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
442 0, &canmioclk_lock);
433 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 443 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
434 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 444 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
435 SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); 445 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
446 &canmioclk_lock);
436 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 447 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
437 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 448 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
438 SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); 449 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
450 0, &canmioclk_lock);
439 451
440 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 452 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
441 int idx = of_property_match_string(np, "clock-names", 453 int idx = of_property_match_string(np, "clock-names",
@@ -444,13 +456,15 @@ static void __init zynq_clk_setup(struct device_node *np)
444 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 456 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
445 idx); 457 idx);
446 } 458 }
447 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, 459 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
448 SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); 460 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
461 &dbgclk_lock);
449 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 462 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
450 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 463 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
451 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 464 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
452 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, 465 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
453 SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); 466 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
467 &dbgclk_lock);
454 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 468 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
455 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 469 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
456 0, 0, &dbgclk_lock); 470 0, 0, &dbgclk_lock);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 10:23:38 -0500