1 files changed, 103 insertions, 35 deletions

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 7e498a44f97d..abd956d5f838 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -25,8 +25,6 @@
 #undef pr_fmt
 #define pr_fmt(fmt) "%s: " fmt, __func__
 
-#define DPLL_HAS_AUTOIDLE       0x1
-
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
         defined(CONFIG_SOC_DRA7XX)
 static const struct clk_ops dpll_m4xen_ck_ops = {
@@ -37,21 +35,18 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
         .get_parent     = &omap2_init_dpll_parent,
 };
+#else
+static const struct clk_ops dpll_m4xen_ck_ops = {};
 #endif
 
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+        defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
+        defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static const struct clk_ops dpll_core_ck_ops = {
         .recalc_rate    = &omap3_dpll_recalc,
         .get_parent     = &omap2_init_dpll_parent,
 };
 
-#ifdef CONFIG_ARCH_OMAP3
-static const struct clk_ops omap3_dpll_core_ck_ops = {
-        .get_parent     = &omap2_init_dpll_parent,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-};
-#endif
-
 static const struct clk_ops dpll_ck_ops = {
         .enable         = &omap3_noncore_dpll_enable,
         .disable        = &omap3_noncore_dpll_disable,
@@ -67,6 +62,33 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
         .round_rate     = &omap2_dpll_round_rate,
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
+#else
+static const struct clk_ops dpll_core_ck_ops = {};
+static const struct clk_ops dpll_ck_ops = {};
+static const struct clk_ops dpll_no_gate_ck_ops = {};
+const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2
+static const struct clk_ops omap2_dpll_core_ck_ops = {
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap2_dpllcore_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+#else
+static const struct clk_ops omap2_dpll_core_ck_ops = {};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+};
+#else
+static const struct clk_ops omap3_dpll_core_ck_ops = {};
+#endif
 
 #ifdef CONFIG_ARCH_OMAP3
 static const struct clk_ops omap3_dpll_ck_ops = {
@@ -193,14 +215,12 @@ static void ti_clk_register_dpll_x2(struct device_node *node,
  * @node: device node containing the DPLL info
  * @ops: ops for the DPLL
  * @ddt: DPLL data template to use
- * @init_flags: flags for controlling init types
  *
  * Initializes a DPLL clock from device tree data.
  */
 static void __init of_ti_dpll_setup(struct device_node *node,
                                     const struct clk_ops *ops,
-                                    const struct dpll_data *ddt,
-                                    u8 init_flags)
+                                    const struct dpll_data *ddt)
 {
         struct clk_hw_omap *clk_hw = NULL;
         struct clk_init_data *init = NULL;
@@ -241,13 +261,30 @@ static void __init of_ti_dpll_setup(struct device_node *node,
         init->parent_names = parent_names;
 
         dd->control_reg = ti_clk_get_reg_addr(node, 0);
-        dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
-        dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
 
-        if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
+        /*
+         * Special case for OMAP2 DPLL, register order is different due to
+         * missing idlest_reg, also clkhwops is different. Detected from
+         * missing idlest_mask.
+         */
+        if (!dd->idlest_mask) {
+                dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
+#ifdef CONFIG_ARCH_OMAP2
+                clk_hw->ops = &clkhwops_omap2xxx_dpll;
+                omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
+#endif
+        } else {
+                dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
+                if (!dd->idlest_reg)
+                        goto cleanup;
+
+                dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
+        }
+
+        if (!dd->control_reg || !dd->mult_div1_reg)
                 goto cleanup;
 
-        if (init_flags & DPLL_HAS_AUTOIDLE) {
+        if (dd->autoidle_mask) {
                 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
                 if (!dd->autoidle_reg)
                         goto cleanup;
@@ -310,7 +347,7 @@ static void __init of_ti_omap3_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
                of_ti_omap3_dpll_setup);
@@ -329,7 +366,7 @@ static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
                 .freqsel_mask = 0xf0,
         };
 
-        of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
                of_ti_omap3_core_dpll_setup);
@@ -349,7 +386,7 @@ static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
                of_ti_omap3_per_dpll_setup);
@@ -371,7 +408,7 @@ static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
                of_ti_omap3_per_jtype_dpll_setup);
@@ -391,11 +428,32 @@ static void __init of_ti_omap4_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
                of_ti_omap4_dpll_setup);
 
+static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
+{
+        const struct dpll_data dd = {
+                .idlest_mask = 0x1,
+                .enable_mask = 0x7,
+                .autoidle_mask = 0x7,
+                .mult_mask = 0x7ff << 8,
+                .div1_mask = 0x7f,
+                .max_multiplier = 2047,
+                .max_divider = 128,
+                .dcc_mask = BIT(22),
+                .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
+                .min_divider = 1,
+                .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        };
+
+        of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
+}
+CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
+               of_ti_omap5_mpu_dpll_setup);
+
 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
 {
         const struct dpll_data dd = {
@@ -410,7 +468,7 @@ static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
                of_ti_omap4_core_dpll_setup);
@@ -433,7 +491,7 @@ static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
                of_ti_omap4_m4xen_dpll_setup);
@@ -454,7 +512,7 @@ static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
+        of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
                of_ti_omap4_jtype_dpll_setup);
@@ -465,7 +523,6 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
         const struct dpll_data dd = {
                 .idlest_mask = 0x1,
                 .enable_mask = 0x7,
-                .autoidle_mask = 0x7,
                 .mult_mask = 0x7ff << 8,
                 .div1_mask = 0x7f,
                 .max_multiplier = 2047,
@@ -474,7 +531,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+        of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
                of_ti_am3_no_gate_dpll_setup);
@@ -484,7 +541,6 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
         const struct dpll_data dd = {
                 .idlest_mask = 0x1,
                 .enable_mask = 0x7,
-                .autoidle_mask = 0x7,
                 .mult_mask = 0x7ff << 8,
                 .div1_mask = 0x7f,
                 .max_multiplier = 4095,
@@ -494,7 +550,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+        of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
                of_ti_am3_jtype_dpll_setup);
@@ -504,7 +560,6 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
         const struct dpll_data dd = {
                 .idlest_mask = 0x1,
                 .enable_mask = 0x7,
-                .autoidle_mask = 0x7,
                 .mult_mask = 0x7ff << 8,
                 .div1_mask = 0x7f,
                 .max_multiplier = 2047,
@@ -514,7 +569,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
+        of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
                "ti,am3-dpll-no-gate-j-type-clock",
@@ -525,7 +580,6 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
         const struct dpll_data dd = {
                 .idlest_mask = 0x1,
                 .enable_mask = 0x7,
-                .autoidle_mask = 0x7,
                 .mult_mask = 0x7ff << 8,
                 .div1_mask = 0x7f,
                 .max_multiplier = 2047,
@@ -534,7 +588,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
+        of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
 
@@ -543,7 +597,6 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
         const struct dpll_data dd = {
                 .idlest_mask = 0x1,
                 .enable_mask = 0x7,
-                .autoidle_mask = 0x7,
                 .mult_mask = 0x7ff << 8,
                 .div1_mask = 0x7f,
                 .max_multiplier = 2047,
@@ -552,7 +605,22 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         };
 
-        of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
+        of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 }
 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
                of_ti_am3_core_dpll_setup);
+
+static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
+{
+        const struct dpll_data dd = {
+                .enable_mask = 0x3,
+                .mult_mask = 0x3ff << 12,
+                .div1_mask = 0xf << 8,
+                .max_divider = 16,
+                .min_divider = 1,
+        };
+
+        of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
+               of_ti_omap2_core_dpll_setup);