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path: root/drivers/clk/tegra
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-rw-r--r--drivers/clk/tegra/clk-periph-gate.c8
-rw-r--r--drivers/clk/tegra/clk-periph.c6
-rw-r--r--drivers/clk/tegra/clk-tegra114.c376
-rw-r--r--drivers/clk/tegra/clk-tegra20.c220
-rw-r--r--drivers/clk/tegra/clk-tegra30.c317
-rw-r--r--drivers/clk/tegra/clk.c104
-rw-r--r--drivers/clk/tegra/clk.h17
7 files changed, 464 insertions, 584 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index bafee9895a24..f38f33e3c65d 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -151,12 +151,16 @@ const struct clk_ops tegra_clk_periph_gate_ops = {
151 151
152struct clk *tegra_clk_register_periph_gate(const char *name, 152struct clk *tegra_clk_register_periph_gate(const char *name,
153 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 153 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
154 unsigned long flags, int clk_num, 154 unsigned long flags, int clk_num, int *enable_refcnt)
155 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
156{ 155{
157 struct tegra_clk_periph_gate *gate; 156 struct tegra_clk_periph_gate *gate;
158 struct clk *clk; 157 struct clk *clk;
159 struct clk_init_data init; 158 struct clk_init_data init;
159 struct tegra_clk_periph_regs *pregs;
160
161 pregs = get_reg_bank(clk_num);
162 if (!pregs)
163 return ERR_PTR(-EINVAL);
160 164
161 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 165 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
162 if (!gate) { 166 if (!gate) {
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b2309d37a963..735b0243261c 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -178,6 +178,7 @@ static struct clk *_tegra_clk_register_periph(const char *name,
178{ 178{
179 struct clk *clk; 179 struct clk *clk;
180 struct clk_init_data init; 180 struct clk_init_data init;
181 struct tegra_clk_periph_regs *bank;
181 182
182 init.name = name; 183 init.name = name;
183 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops; 184 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
@@ -185,12 +186,17 @@ static struct clk *_tegra_clk_register_periph(const char *name,
185 init.parent_names = parent_names; 186 init.parent_names = parent_names;
186 init.num_parents = num_parents; 187 init.num_parents = num_parents;
187 188
189 bank = get_reg_bank(periph->gate.clk_num);
190 if (!bank)
191 return ERR_PTR(-EINVAL);
192
188 /* Data in .init is copied by clk_register(), so stack variable OK */ 193 /* Data in .init is copied by clk_register(), so stack variable OK */
189 periph->hw.init = &init; 194 periph->hw.init = &init;
190 periph->magic = TEGRA_CLK_PERIPH_MAGIC; 195 periph->magic = TEGRA_CLK_PERIPH_MAGIC;
191 periph->mux.reg = clk_base + offset; 196 periph->mux.reg = clk_base + offset;
192 periph->divider.reg = div ? (clk_base + offset) : NULL; 197 periph->divider.reg = div ? (clk_base + offset) : NULL;
193 periph->gate.clk_base = clk_base; 198 periph->gate.clk_base = clk_base;
199 periph->gate.regs = bank;
194 200
195 clk = clk_register(NULL, &periph->hw); 201 clk = clk_register(NULL, &periph->hw);
196 if (IS_ERR(clk)) 202 if (IS_ERR(clk))
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 2471742d68de..8507067d5dd6 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -27,27 +27,10 @@
27 27
28#include "clk.h" 28#include "clk.h"
29 29
30#define RST_DEVICES_L 0x004
31#define RST_DEVICES_H 0x008
32#define RST_DEVICES_U 0x00C
33#define RST_DFLL_DVCO 0x2F4 30#define RST_DFLL_DVCO 0x2F4
34#define RST_DEVICES_V 0x358
35#define RST_DEVICES_W 0x35C
36#define RST_DEVICES_X 0x28C
37#define RST_DEVICES_SET_L 0x300
38#define RST_DEVICES_CLR_L 0x304
39#define RST_DEVICES_SET_H 0x308
40#define RST_DEVICES_CLR_H 0x30c
41#define RST_DEVICES_SET_U 0x310
42#define RST_DEVICES_CLR_U 0x314
43#define RST_DEVICES_SET_V 0x430
44#define RST_DEVICES_CLR_V 0x434
45#define RST_DEVICES_SET_W 0x438
46#define RST_DEVICES_CLR_W 0x43c
47#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 31#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
48#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 32#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
49#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 33#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
50#define RST_DEVICES_NUM 5
51 34
52/* RST_DFLL_DVCO bitfields */ 35/* RST_DFLL_DVCO bitfields */
53#define DVFS_DFLL_RESET_SHIFT 0 36#define DVFS_DFLL_RESET_SHIFT 0
@@ -74,26 +57,10 @@
74#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 57#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
75#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 58#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
76 59
77#define CLK_OUT_ENB_L 0x010
78#define CLK_OUT_ENB_H 0x014
79#define CLK_OUT_ENB_U 0x018
80#define CLK_OUT_ENB_V 0x360
81#define CLK_OUT_ENB_W 0x364
82#define CLK_OUT_ENB_X 0x280
83#define CLK_OUT_ENB_SET_L 0x320
84#define CLK_OUT_ENB_CLR_L 0x324
85#define CLK_OUT_ENB_SET_H 0x328
86#define CLK_OUT_ENB_CLR_H 0x32c
87#define CLK_OUT_ENB_SET_U 0x330
88#define CLK_OUT_ENB_CLR_U 0x334
89#define CLK_OUT_ENB_SET_V 0x440
90#define CLK_OUT_ENB_CLR_V 0x444
91#define CLK_OUT_ENB_SET_W 0x448
92#define CLK_OUT_ENB_CLR_W 0x44c
93#define CLK_OUT_ENB_SET_X 0x284
94#define CLK_OUT_ENB_CLR_X 0x288
95#define CLK_OUT_ENB_NUM 6 60#define CLK_OUT_ENB_NUM 6
96 61
62#define TEGRA114_CLK_PERIPH_BANKS 5
63
97#define PLLC_BASE 0x80 64#define PLLC_BASE 0x80
98#define PLLC_MISC2 0x88 65#define PLLC_MISC2 0x88
99#define PLLC_MISC 0x8c 66#define PLLC_MISC 0x8c
@@ -728,53 +695,6 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
728 .div_nmp = &pllre_nmp, 695 .div_nmp = &pllre_nmp,
729}; 696};
730 697
731/* Peripheral clock registers */
732
733static struct tegra_clk_periph_regs periph_l_regs = {
734 .enb_reg = CLK_OUT_ENB_L,
735 .enb_set_reg = CLK_OUT_ENB_SET_L,
736 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
737 .rst_reg = RST_DEVICES_L,
738 .rst_set_reg = RST_DEVICES_SET_L,
739 .rst_clr_reg = RST_DEVICES_CLR_L,
740};
741
742static struct tegra_clk_periph_regs periph_h_regs = {
743 .enb_reg = CLK_OUT_ENB_H,
744 .enb_set_reg = CLK_OUT_ENB_SET_H,
745 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
746 .rst_reg = RST_DEVICES_H,
747 .rst_set_reg = RST_DEVICES_SET_H,
748 .rst_clr_reg = RST_DEVICES_CLR_H,
749};
750
751static struct tegra_clk_periph_regs periph_u_regs = {
752 .enb_reg = CLK_OUT_ENB_U,
753 .enb_set_reg = CLK_OUT_ENB_SET_U,
754 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
755 .rst_reg = RST_DEVICES_U,
756 .rst_set_reg = RST_DEVICES_SET_U,
757 .rst_clr_reg = RST_DEVICES_CLR_U,
758};
759
760static struct tegra_clk_periph_regs periph_v_regs = {
761 .enb_reg = CLK_OUT_ENB_V,
762 .enb_set_reg = CLK_OUT_ENB_SET_V,
763 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
764 .rst_reg = RST_DEVICES_V,
765 .rst_set_reg = RST_DEVICES_SET_V,
766 .rst_clr_reg = RST_DEVICES_CLR_V,
767};
768
769static struct tegra_clk_periph_regs periph_w_regs = {
770 .enb_reg = CLK_OUT_ENB_W,
771 .enb_set_reg = CLK_OUT_ENB_SET_W,
772 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
773 .rst_reg = RST_DEVICES_W,
774 .rst_set_reg = RST_DEVICES_SET_W,
775 .rst_clr_reg = RST_DEVICES_CLR_W,
776};
777
778/* possible OSC frequencies in Hz */ 698/* possible OSC frequencies in Hz */
779static unsigned long tegra114_input_freq[] = { 699static unsigned long tegra114_input_freq[] = {
780 [0] = 13000000, 700 [0] = 13000000,
@@ -789,77 +709,77 @@ static unsigned long tegra114_input_freq[] = {
789#define MASK(x) (BIT(x) - 1) 709#define MASK(x) (BIT(x) - 1)
790 710
791#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 711#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
792 _clk_num, _regs, _gate_flags, _clk_id) \ 712 _clk_num, _gate_flags, _clk_id) \
793 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 713 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
794 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 714 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
795 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 715 _clk_num, periph_clk_enb_refcnt, _gate_flags,\
796 _clk_id, _parents##_idx, 0) 716 _clk_id, _parents##_idx, 0)
797 717
798#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 718#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
799 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 719 _clk_num, _gate_flags, _clk_id, flags)\
800 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 720 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
801 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 721 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
802 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 722 _clk_num, periph_clk_enb_refcnt, _gate_flags,\
803 _clk_id, _parents##_idx, flags) 723 _clk_id, _parents##_idx, flags)
804 724
805#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 725#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
806 _clk_num, _regs, _gate_flags, _clk_id) \ 726 _clk_num, _gate_flags, _clk_id) \
807 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 727 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
808 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 728 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
809 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 729 _clk_num, periph_clk_enb_refcnt, _gate_flags,\
810 _clk_id, _parents##_idx, 0) 730 _clk_id, _parents##_idx, 0)
811 731
812#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 732#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
813 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 733 _clk_num, _gate_flags, _clk_id, flags)\
814 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 734 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
815 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 735 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
816 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 736 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
817 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 737 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
818 _parents##_idx, flags) 738 _parents##_idx, flags)
819 739
820#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 740#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
821 _clk_num, _regs, _gate_flags, _clk_id) \ 741 _clk_num, _gate_flags, _clk_id) \
822 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 742 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
823 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 743 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
824 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 744 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
825 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 745 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
826 _parents##_idx, 0) 746 _parents##_idx, 0)
827 747
828#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 748#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
829 _clk_num, _regs, _clk_id) \ 749 _clk_num, _clk_id) \
830 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 750 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
831 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ 751 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
832 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 752 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
833 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 753 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
834 754
835#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 755#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
836 _clk_num, _regs, _clk_id) \ 756 _clk_num, _clk_id) \
837 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 757 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
838 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 758 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
839 _regs, _clk_num, periph_clk_enb_refcnt, 0, _clk_id,\ 759 _clk_num, periph_clk_enb_refcnt, 0, _clk_id,\
840 _parents##_idx, 0) 760 _parents##_idx, 0)
841 761
842#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 762#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
843 _mux_shift, _mux_mask, _clk_num, _regs, \ 763 _mux_shift, _mux_mask, _clk_num, \
844 _gate_flags, _clk_id) \ 764 _gate_flags, _clk_id) \
845 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 765 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
846 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 766 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
847 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 767 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
848 _clk_id, _parents##_idx, 0) 768 _clk_id, _parents##_idx, 0)
849 769
850#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 770#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
851 _clk_num, _regs, _gate_flags, _clk_id) \ 771 _clk_num, _gate_flags, _clk_id) \
852 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 772 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
853 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 773 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
854 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 774 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
855 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 775 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
856 _parents##_idx, 0) 776 _parents##_idx, 0)
857 777
858#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 778#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
859 _regs, _gate_flags, _clk_id) \ 779 _gate_flags, _clk_id) \
860 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 780 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
861 _offset, 16, 0xE01F, 0, 0, 8, 1, \ 781 _offset, 16, 0xE01F, 0, 0, 8, 1, \
862 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 782 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
863 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 783 periph_clk_enb_refcnt, _gate_flags , _clk_id, \
864 mux_d_audio_clk_idx, 0) 784 mux_d_audio_clk_idx, 0)
865 785
@@ -1612,7 +1532,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1612 0, &clk_doubler_lock); 1532 0, &clk_doubler_lock);
1613 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1533 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1614 TEGRA_PERIPH_NO_RESET, clk_base, 1534 TEGRA_PERIPH_NO_RESET, clk_base,
1615 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1535 CLK_SET_RATE_PARENT, 113,
1616 periph_clk_enb_refcnt); 1536 periph_clk_enb_refcnt);
1617 clk_register_clkdev(clk, "audio0_2x", NULL); 1537 clk_register_clkdev(clk, "audio0_2x", NULL);
1618 clks[TEGRA114_CLK_AUDIO0_2X] = clk; 1538 clks[TEGRA114_CLK_AUDIO0_2X] = clk;
@@ -1625,7 +1545,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1625 0, &clk_doubler_lock); 1545 0, &clk_doubler_lock);
1626 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1546 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1627 TEGRA_PERIPH_NO_RESET, clk_base, 1547 TEGRA_PERIPH_NO_RESET, clk_base,
1628 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1548 CLK_SET_RATE_PARENT, 114,
1629 periph_clk_enb_refcnt); 1549 periph_clk_enb_refcnt);
1630 clk_register_clkdev(clk, "audio1_2x", NULL); 1550 clk_register_clkdev(clk, "audio1_2x", NULL);
1631 clks[TEGRA114_CLK_AUDIO1_2X] = clk; 1551 clks[TEGRA114_CLK_AUDIO1_2X] = clk;
@@ -1638,7 +1558,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1638 0, &clk_doubler_lock); 1558 0, &clk_doubler_lock);
1639 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1559 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1640 TEGRA_PERIPH_NO_RESET, clk_base, 1560 TEGRA_PERIPH_NO_RESET, clk_base,
1641 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1561 CLK_SET_RATE_PARENT, 115,
1642 periph_clk_enb_refcnt); 1562 periph_clk_enb_refcnt);
1643 clk_register_clkdev(clk, "audio2_2x", NULL); 1563 clk_register_clkdev(clk, "audio2_2x", NULL);
1644 clks[TEGRA114_CLK_AUDIO2_2X] = clk; 1564 clks[TEGRA114_CLK_AUDIO2_2X] = clk;
@@ -1651,7 +1571,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1651 0, &clk_doubler_lock); 1571 0, &clk_doubler_lock);
1652 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1572 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1653 TEGRA_PERIPH_NO_RESET, clk_base, 1573 TEGRA_PERIPH_NO_RESET, clk_base,
1654 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1574 CLK_SET_RATE_PARENT, 116,
1655 periph_clk_enb_refcnt); 1575 periph_clk_enb_refcnt);
1656 clk_register_clkdev(clk, "audio3_2x", NULL); 1576 clk_register_clkdev(clk, "audio3_2x", NULL);
1657 clks[TEGRA114_CLK_AUDIO3_2X] = clk; 1577 clks[TEGRA114_CLK_AUDIO3_2X] = clk;
@@ -1664,7 +1584,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1664 0, &clk_doubler_lock); 1584 0, &clk_doubler_lock);
1665 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1585 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1666 TEGRA_PERIPH_NO_RESET, clk_base, 1586 TEGRA_PERIPH_NO_RESET, clk_base,
1667 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1587 CLK_SET_RATE_PARENT, 117,
1668 periph_clk_enb_refcnt); 1588 periph_clk_enb_refcnt);
1669 clk_register_clkdev(clk, "audio4_2x", NULL); 1589 clk_register_clkdev(clk, "audio4_2x", NULL);
1670 clks[TEGRA114_CLK_AUDIO4_2X] = clk; 1590 clks[TEGRA114_CLK_AUDIO4_2X] = clk;
@@ -1678,7 +1598,7 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1678 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1598 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1679 TEGRA_PERIPH_NO_RESET, clk_base, 1599 TEGRA_PERIPH_NO_RESET, clk_base,
1680 CLK_SET_RATE_PARENT, 118, 1600 CLK_SET_RATE_PARENT, 118,
1681 &periph_v_regs, periph_clk_enb_refcnt); 1601 periph_clk_enb_refcnt);
1682 clk_register_clkdev(clk, "spdif_2x", NULL); 1602 clk_register_clkdev(clk, "spdif_2x", NULL);
1683 clks[TEGRA114_CLK_SPDIF_2X] = clk; 1603 clks[TEGRA114_CLK_SPDIF_2X] = clk;
1684} 1604}
@@ -1805,86 +1725,86 @@ static void __init tegra114_super_clk_init(void __iomem *clk_base)
1805} 1725}
1806 1726
1807static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1727static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1808 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0), 1728 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0),
1809 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1), 1729 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1),
1810 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2), 1730 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2),
1811 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3), 1731 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3),
1812 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4), 1732 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4),
1813 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT), 1733 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT),
1814 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN), 1734 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN),
1815 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM), 1735 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM),
1816 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX), 1736 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX),
1817 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX), 1737 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX),
1818 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA), 1738 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA),
1819 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X), 1739 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X),
1820 TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1), 1740 TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1),
1821 TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2), 1741 TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2),
1822 TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3), 1742 TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3),
1823 TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4), 1743 TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4),
1824 TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5), 1744 TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5),
1825 TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6), 1745 TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6),
1826 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1746 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED),
1827 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1747 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED),
1828 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR), 1748 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR),
1829 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, TEGRA114_CLK_SDMMC1), 1749 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, TEGRA114_CLK_SDMMC1),
1830 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, TEGRA114_CLK_SDMMC2), 1750 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, TEGRA114_CLK_SDMMC2),
1831 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, TEGRA114_CLK_SDMMC3), 1751 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, TEGRA114_CLK_SDMMC3),
1832 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, TEGRA114_CLK_SDMMC4), 1752 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, TEGRA114_CLK_SDMMC4),
1833 TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, TEGRA114_CLK_VDE), 1753 TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, TEGRA114_CLK_VDE),
1834 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED), 1754 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED),
1835 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA), 1755 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA),
1836 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE), 1756 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE),
1837 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR), 1757 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR),
1838 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, TEGRA114_CLK_NOR), 1758 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, TEGRA114_CLK_NOR),
1839 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI), 1759 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI),
1840 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA114_CLK_I2C1), 1760 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA114_CLK_I2C1),
1841 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA114_CLK_I2C2), 1761 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA114_CLK_I2C2),
1842 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA114_CLK_I2C3), 1762 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA114_CLK_I2C3),
1843 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA114_CLK_I2C4), 1763 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA114_CLK_I2C4),
1844 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA114_CLK_I2C5), 1764 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA114_CLK_I2C5),
1845 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, TEGRA114_CLK_UARTA), 1765 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, TEGRA114_CLK_UARTA),
1846 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, TEGRA114_CLK_UARTB), 1766 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, TEGRA114_CLK_UARTB),
1847 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, TEGRA114_CLK_UARTC), 1767 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, TEGRA114_CLK_UARTC),
1848 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, TEGRA114_CLK_UARTD), 1768 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, TEGRA114_CLK_UARTD),
1849 TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, TEGRA114_CLK_GR3D), 1769 TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, TEGRA114_CLK_GR3D),
1850 TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, TEGRA114_CLK_GR2D), 1770 TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, TEGRA114_CLK_GR2D),
1851 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), 1771 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1852 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, TEGRA114_CLK_VI), 1772 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, TEGRA114_CLK_VI),
1853 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, TEGRA114_CLK_EPP), 1773 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, TEGRA114_CLK_EPP),
1854 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC), 1774 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC),
1855 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, TEGRA114_CLK_TSEC), 1775 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, TEGRA114_CLK_TSEC),
1856 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, TEGRA114_CLK_HOST1X), 1776 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, TEGRA114_CLK_HOST1X),
1857 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, TEGRA114_CLK_HDMI), 1777 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA114_CLK_HDMI),
1858 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, TEGRA114_CLK_CILAB), 1778 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, TEGRA114_CLK_CILAB),
1859 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, TEGRA114_CLK_CILCD), 1779 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, TEGRA114_CLK_CILCD),
1860 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, TEGRA114_CLK_CILE), 1780 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, TEGRA114_CLK_CILE),
1861 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, TEGRA114_CLK_DSIALP), 1781 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, TEGRA114_CLK_DSIALP),
1862 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, TEGRA114_CLK_DSIBLP), 1782 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, TEGRA114_CLK_DSIBLP),
1863 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR), 1783 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR),
1864 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, TEGRA114_CLK_ACTMON), 1784 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, TEGRA114_CLK_ACTMON),
1865 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, TEGRA114_CLK_EXTERN1), 1785 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, TEGRA114_CLK_EXTERN1),
1866 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, TEGRA114_CLK_EXTERN2), 1786 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, TEGRA114_CLK_EXTERN2),
1867 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, TEGRA114_CLK_EXTERN3), 1787 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, TEGRA114_CLK_EXTERN3),
1868 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW), 1788 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW),
1869 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE), 1789 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE),
1870 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED), 1790 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED),
1871 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF), 1791 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF),
1872 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC), 1792 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC),
1873 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM), 1793 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM),
1874 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC), 1794 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC),
1875 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC), 1795 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC),
1876 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC), 1796 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC),
1877 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC), 1797 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC),
1878 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC), 1798 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC),
1879 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO), 1799 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO),
1880 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0), 1800 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0),
1881 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1), 1801 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1),
1882 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2), 1802 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2),
1883}; 1803};
1884 1804
1885static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1805static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1886 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, TEGRA114_CLK_DISP1), 1806 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, TEGRA114_CLK_DISP1),
1887 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, TEGRA114_CLK_DISP2), 1807 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, TEGRA114_CLK_DISP2),
1888}; 1808};
1889 1809
1890static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1810static __init void tegra114_periph_clk_init(void __iomem *clk_base)
@@ -1896,16 +1816,14 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1896 1816
1897 /* apbdma */ 1817 /* apbdma */
1898 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1818 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1899 0, 34, &periph_h_regs, 1819 0, 34, periph_clk_enb_refcnt);
1900 periph_clk_enb_refcnt);
1901 clks[TEGRA114_CLK_APBDMA] = clk; 1820 clks[TEGRA114_CLK_APBDMA] = clk;
1902 1821
1903 /* rtc */ 1822 /* rtc */
1904 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1823 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1905 TEGRA_PERIPH_ON_APB | 1824 TEGRA_PERIPH_ON_APB |
1906 TEGRA_PERIPH_NO_RESET, clk_base, 1825 TEGRA_PERIPH_NO_RESET, clk_base,
1907 0, 4, &periph_l_regs, 1826 0, 4, periph_clk_enb_refcnt);
1908 periph_clk_enb_refcnt);
1909 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1827 clk_register_clkdev(clk, NULL, "rtc-tegra");
1910 clks[TEGRA114_CLK_RTC] = clk; 1828 clks[TEGRA114_CLK_RTC] = clk;
1911 1829
@@ -1913,123 +1831,112 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1913 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1831 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1914 TEGRA_PERIPH_ON_APB | 1832 TEGRA_PERIPH_ON_APB |
1915 TEGRA_PERIPH_NO_RESET, clk_base, 1833 TEGRA_PERIPH_NO_RESET, clk_base,
1916 0, 36, &periph_h_regs, 1834 0, 36, periph_clk_enb_refcnt);
1917 periph_clk_enb_refcnt);
1918 clks[TEGRA114_CLK_KBC] = clk; 1835 clks[TEGRA114_CLK_KBC] = clk;
1919 1836
1920 /* timer */ 1837 /* timer */
1921 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1838 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1922 0, 5, &periph_l_regs, 1839 0, 5, periph_clk_enb_refcnt);
1923 periph_clk_enb_refcnt);
1924 clk_register_clkdev(clk, NULL, "timer"); 1840 clk_register_clkdev(clk, NULL, "timer");
1925 clks[TEGRA114_CLK_TIMER] = clk; 1841 clks[TEGRA114_CLK_TIMER] = clk;
1926 1842
1927 /* kfuse */ 1843 /* kfuse */
1928 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1844 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1929 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1845 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1930 &periph_h_regs, periph_clk_enb_refcnt); 1846 periph_clk_enb_refcnt);
1931 clks[TEGRA114_CLK_KFUSE] = clk; 1847 clks[TEGRA114_CLK_KFUSE] = clk;
1932 1848
1933 /* fuse */ 1849 /* fuse */
1934 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1850 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1935 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1851 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1936 &periph_h_regs, periph_clk_enb_refcnt); 1852 periph_clk_enb_refcnt);
1937 clks[TEGRA114_CLK_FUSE] = clk; 1853 clks[TEGRA114_CLK_FUSE] = clk;
1938 1854
1939 /* fuse_burn */ 1855 /* fuse_burn */
1940 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1856 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1941 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1857 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1942 &periph_h_regs, periph_clk_enb_refcnt); 1858 periph_clk_enb_refcnt);
1943 clks[TEGRA114_CLK_FUSE_BURN] = clk; 1859 clks[TEGRA114_CLK_FUSE_BURN] = clk;
1944 1860
1945 /* apbif */ 1861 /* apbif */
1946 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1862 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1947 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1863 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1948 &periph_v_regs, periph_clk_enb_refcnt); 1864 periph_clk_enb_refcnt);
1949 clks[TEGRA114_CLK_APBIF] = clk; 1865 clks[TEGRA114_CLK_APBIF] = clk;
1950 1866
1951 /* hda2hdmi */ 1867 /* hda2hdmi */
1952 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1868 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1953 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1869 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1954 &periph_w_regs, periph_clk_enb_refcnt); 1870 periph_clk_enb_refcnt);
1955 clks[TEGRA114_CLK_HDA2HDMI] = clk; 1871 clks[TEGRA114_CLK_HDA2HDMI] = clk;
1956 1872
1957 /* vcp */ 1873 /* vcp */
1958 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1874 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1959 29, &periph_l_regs, 1875 29, periph_clk_enb_refcnt);
1960 periph_clk_enb_refcnt);
1961 clks[TEGRA114_CLK_VCP] = clk; 1876 clks[TEGRA114_CLK_VCP] = clk;
1962 1877
1963 /* bsea */ 1878 /* bsea */
1964 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1879 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1965 0, 62, &periph_h_regs, 1880 0, 62, periph_clk_enb_refcnt);
1966 periph_clk_enb_refcnt);
1967 clks[TEGRA114_CLK_BSEA] = clk; 1881 clks[TEGRA114_CLK_BSEA] = clk;
1968 1882
1969 /* bsev */ 1883 /* bsev */
1970 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1884 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1971 0, 63, &periph_h_regs, 1885 0, 63, periph_clk_enb_refcnt);
1972 periph_clk_enb_refcnt);
1973 clks[TEGRA114_CLK_BSEV] = clk; 1886 clks[TEGRA114_CLK_BSEV] = clk;
1974 1887
1975 /* mipi-cal */ 1888 /* mipi-cal */
1976 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1889 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1977 0, 56, &periph_h_regs, 1890 0, 56, periph_clk_enb_refcnt);
1978 periph_clk_enb_refcnt);
1979 clks[TEGRA114_CLK_MIPI_CAL] = clk; 1891 clks[TEGRA114_CLK_MIPI_CAL] = clk;
1980 1892
1981 /* usbd */ 1893 /* usbd */
1982 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1894 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
1983 0, 22, &periph_l_regs, 1895 0, 22, periph_clk_enb_refcnt);
1984 periph_clk_enb_refcnt);
1985 clks[TEGRA114_CLK_USBD] = clk; 1896 clks[TEGRA114_CLK_USBD] = clk;
1986 1897
1987 /* usb2 */ 1898 /* usb2 */
1988 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1899 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
1989 0, 58, &periph_h_regs, 1900 0, 58, periph_clk_enb_refcnt);
1990 periph_clk_enb_refcnt);
1991 clks[TEGRA114_CLK_USB2] = clk; 1901 clks[TEGRA114_CLK_USB2] = clk;
1992 1902
1993 /* usb3 */ 1903 /* usb3 */
1994 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1904 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
1995 0, 59, &periph_h_regs, 1905 0, 59, periph_clk_enb_refcnt);
1996 periph_clk_enb_refcnt);
1997 clks[TEGRA114_CLK_USB3] = clk; 1906 clks[TEGRA114_CLK_USB3] = clk;
1998 1907
1999 /* csi */ 1908 /* csi */
2000 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1909 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
2001 0, 52, &periph_h_regs, 1910 0, 52, periph_clk_enb_refcnt);
2002 periph_clk_enb_refcnt);
2003 clks[TEGRA114_CLK_CSI] = clk; 1911 clks[TEGRA114_CLK_CSI] = clk;
2004 1912
2005 /* isp */ 1913 /* isp */
2006 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 1914 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
2007 23, &periph_l_regs, 1915 23, periph_clk_enb_refcnt);
2008 periph_clk_enb_refcnt);
2009 clks[TEGRA114_CLK_ISP] = clk; 1916 clks[TEGRA114_CLK_ISP] = clk;
2010 1917
2011 /* csus */ 1918 /* csus */
2012 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1919 clk = tegra_clk_register_periph_gate("csus", "clk_m",
2013 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 1920 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
2014 &periph_u_regs, periph_clk_enb_refcnt); 1921 periph_clk_enb_refcnt);
2015 clks[TEGRA114_CLK_CSUS] = clk; 1922 clks[TEGRA114_CLK_CSUS] = clk;
2016 1923
2017 /* dds */ 1924 /* dds */
2018 clk = tegra_clk_register_periph_gate("dds", "clk_m", 1925 clk = tegra_clk_register_periph_gate("dds", "clk_m",
2019 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 1926 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
2020 &periph_w_regs, periph_clk_enb_refcnt); 1927 periph_clk_enb_refcnt);
2021 clks[TEGRA114_CLK_DDS] = clk; 1928 clks[TEGRA114_CLK_DDS] = clk;
2022 1929
2023 /* dp2 */ 1930 /* dp2 */
2024 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 1931 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
2025 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 1932 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
2026 &periph_w_regs, periph_clk_enb_refcnt); 1933 periph_clk_enb_refcnt);
2027 clks[TEGRA114_CLK_DP2] = clk; 1934 clks[TEGRA114_CLK_DP2] = clk;
2028 1935
2029 /* dtv */ 1936 /* dtv */
2030 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1937 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
2031 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 1938 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
2032 &periph_u_regs, periph_clk_enb_refcnt); 1939 periph_clk_enb_refcnt);
2033 clks[TEGRA114_CLK_DTV] = clk; 1940 clks[TEGRA114_CLK_DTV] = clk;
2034 1941
2035 /* dsia */ 1942 /* dsia */
@@ -2039,8 +1946,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2039 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1946 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2040 clks[TEGRA114_CLK_DSIA_MUX] = clk; 1947 clks[TEGRA114_CLK_DSIA_MUX] = clk;
2041 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 1948 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
2042 0, 48, &periph_h_regs, 1949 0, 48, periph_clk_enb_refcnt);
2043 periph_clk_enb_refcnt);
2044 clks[TEGRA114_CLK_DSIA] = clk; 1950 clks[TEGRA114_CLK_DSIA] = clk;
2045 1951
2046 /* dsib */ 1952 /* dsib */
@@ -2050,8 +1956,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2050 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1956 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2051 clks[TEGRA114_CLK_DSIB_MUX] = clk; 1957 clks[TEGRA114_CLK_DSIB_MUX] = clk;
2052 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 1958 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
2053 0, 82, &periph_u_regs, 1959 0, 82, periph_clk_enb_refcnt);
2054 periph_clk_enb_refcnt);
2055 clks[TEGRA114_CLK_DSIB] = clk; 1960 clks[TEGRA114_CLK_DSIB] = clk;
2056 1961
2057 /* xusb_hs_src */ 1962 /* xusb_hs_src */
@@ -2065,20 +1970,17 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2065 1970
2066 /* xusb_host */ 1971 /* xusb_host */
2067 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 1972 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
2068 clk_base, 0, 89, &periph_u_regs, 1973 clk_base, 0, 89, periph_clk_enb_refcnt);
2069 periph_clk_enb_refcnt);
2070 clks[TEGRA114_CLK_XUSB_HOST] = clk; 1974 clks[TEGRA114_CLK_XUSB_HOST] = clk;
2071 1975
2072 /* xusb_ss */ 1976 /* xusb_ss */
2073 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 1977 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
2074 clk_base, 0, 156, &periph_w_regs, 1978 clk_base, 0, 156, periph_clk_enb_refcnt);
2075 periph_clk_enb_refcnt);
2076 clks[TEGRA114_CLK_XUSB_HOST] = clk; 1979 clks[TEGRA114_CLK_XUSB_HOST] = clk;
2077 1980
2078 /* xusb_dev */ 1981 /* xusb_dev */
2079 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 1982 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
2080 clk_base, 0, 95, &periph_u_regs, 1983 clk_base, 0, 95, periph_clk_enb_refcnt);
2081 periph_clk_enb_refcnt);
2082 clks[TEGRA114_CLK_XUSB_DEV] = clk; 1984 clks[TEGRA114_CLK_XUSB_DEV] = clk;
2083 1985
2084 /* emc */ 1986 /* emc */
@@ -2088,20 +1990,21 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2088 clk_base + CLK_SOURCE_EMC, 1990 clk_base + CLK_SOURCE_EMC,
2089 29, 3, 0, NULL); 1991 29, 3, 0, NULL);
2090 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 1992 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
2091 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 1993 CLK_IGNORE_UNUSED, 57, periph_clk_enb_refcnt);
2092 periph_clk_enb_refcnt);
2093 clks[TEGRA114_CLK_EMC] = clk; 1994 clks[TEGRA114_CLK_EMC] = clk;
2094 1995
2095 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1996 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
2096 data = &tegra_periph_clk_list[i]; 1997 data = &tegra_periph_clk_list[i];
2097 clk = tegra_clk_register_periph(data->name, data->parent_names, 1998
2098 data->num_parents, &data->periph, 1999 clk = tegra_clk_register_periph(data->name,
2099 clk_base, data->offset, data->flags); 2000 data->parent_names, data->num_parents, &data->periph,
2001 clk_base, data->offset, data->flags);
2100 clks[data->clk_id] = clk; 2002 clks[data->clk_id] = clk;
2101 } 2003 }
2102 2004
2103 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 2005 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
2104 data = &tegra_periph_nodiv_clk_list[i]; 2006 data = &tegra_periph_nodiv_clk_list[i];
2007
2105 clk = tegra_clk_register_periph_nodiv(data->name, 2008 clk = tegra_clk_register_periph_nodiv(data->name,
2106 data->parent_names, data->num_parents, 2009 data->parent_names, data->num_parents,
2107 &data->periph, clk_base, data->offset); 2010 &data->periph, clk_base, data->offset);
@@ -2351,6 +2254,9 @@ static void __init tegra114_clock_init(struct device_node *np)
2351 if (tegra114_osc_clk_init(clk_base) < 0) 2254 if (tegra114_osc_clk_init(clk_base) < 0)
2352 return; 2255 return;
2353 2256
2257 if (tegra_clk_set_periph_banks(TEGRA114_CLK_PERIPH_BANKS) < 0)
2258 return;
2259
2354 tegra114_fixed_clk_init(clk_base); 2260 tegra114_fixed_clk_init(clk_base);
2355 tegra114_pll_init(clk_base, pmc_base); 2261 tegra114_pll_init(clk_base, pmc_base);
2356 tegra114_periph_clk_init(clk_base); 2262 tegra114_periph_clk_init(clk_base);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 056f649d0d89..929a46278d83 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -25,26 +25,6 @@
25 25
26#include "clk.h" 26#include "clk.h"
27 27
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00c
31#define RST_DEVICES_SET_L 0x300
32#define RST_DEVICES_CLR_L 0x304
33#define RST_DEVICES_SET_H 0x308
34#define RST_DEVICES_CLR_H 0x30c
35#define RST_DEVICES_SET_U 0x310
36#define RST_DEVICES_CLR_U 0x314
37#define RST_DEVICES_NUM 3
38
39#define CLK_OUT_ENB_L 0x010
40#define CLK_OUT_ENB_H 0x014
41#define CLK_OUT_ENB_U 0x018
42#define CLK_OUT_ENB_SET_L 0x320
43#define CLK_OUT_ENB_CLR_L 0x324
44#define CLK_OUT_ENB_SET_H 0x328
45#define CLK_OUT_ENB_CLR_H 0x32c
46#define CLK_OUT_ENB_SET_U 0x330
47#define CLK_OUT_ENB_CLR_U 0x334
48#define CLK_OUT_ENB_NUM 3 28#define CLK_OUT_ENB_NUM 3
49 29
50#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
@@ -67,6 +47,8 @@
67#define OSC_FREQ_DET_BUSY (1<<31) 47#define OSC_FREQ_DET_BUSY (1<<31)
68#define OSC_FREQ_DET_CNT_MASK 0xFFFF 48#define OSC_FREQ_DET_CNT_MASK 0xFFFF
69 49
50#define TEGRA20_CLK_PERIPH_BANKS 3
51
70#define PLLS_BASE 0xf0 52#define PLLS_BASE 0xf0
71#define PLLS_MISC 0xf4 53#define PLLS_MISC 0xf4
72#define PLLC_BASE 0x80 54#define PLLC_BASE 0x80
@@ -197,31 +179,31 @@ static DEFINE_SPINLOCK(pll_div_lock);
197static DEFINE_SPINLOCK(sysrate_lock); 179static DEFINE_SPINLOCK(sysrate_lock);
198 180
199#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 181#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
200 _clk_num, _regs, _gate_flags, _clk_id) \ 182 _clk_num, _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 183 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
202 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 184 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
203 _regs, _clk_num, periph_clk_enb_refcnt, \ 185 _clk_num, periph_clk_enb_refcnt, \
204 _gate_flags, _clk_id) 186 _gate_flags, _clk_id)
205 187
206#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 188#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
207 _clk_num, _regs, _gate_flags, _clk_id) \ 189 _clk_num, _gate_flags, _clk_id) \
208 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 190 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
209 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 191 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, \
210 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 192 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
211 _clk_id) 193 _clk_id)
212 194
213#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 195#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
214 _clk_num, _regs, _gate_flags, _clk_id) \ 196 _clk_num, _gate_flags, _clk_id) \
215 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 197 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
216 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \ 198 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
217 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 199 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
218 _clk_id) 200 _clk_id)
219 201
220#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 202#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
221 _mux_shift, _mux_width, _clk_num, _regs, \ 203 _mux_shift, _mux_width, _clk_num, \
222 _gate_flags, _clk_id) \ 204 _gate_flags, _clk_id) \
223 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 205 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
224 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 206 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
225 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 207 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
226 _clk_id) 208 _clk_id)
227 209
@@ -490,34 +472,6 @@ static struct tegra_clk_pll_params pll_e_params = {
490 .lock_delay = 0, 472 .lock_delay = 0,
491}; 473};
492 474
493/* Peripheral clock registers */
494static struct tegra_clk_periph_regs periph_l_regs = {
495 .enb_reg = CLK_OUT_ENB_L,
496 .enb_set_reg = CLK_OUT_ENB_SET_L,
497 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
498 .rst_reg = RST_DEVICES_L,
499 .rst_set_reg = RST_DEVICES_SET_L,
500 .rst_clr_reg = RST_DEVICES_CLR_L,
501};
502
503static struct tegra_clk_periph_regs periph_h_regs = {
504 .enb_reg = CLK_OUT_ENB_H,
505 .enb_set_reg = CLK_OUT_ENB_SET_H,
506 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
507 .rst_reg = RST_DEVICES_H,
508 .rst_set_reg = RST_DEVICES_SET_H,
509 .rst_clr_reg = RST_DEVICES_CLR_H,
510};
511
512static struct tegra_clk_periph_regs periph_u_regs = {
513 .enb_reg = CLK_OUT_ENB_U,
514 .enb_set_reg = CLK_OUT_ENB_SET_U,
515 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
516 .rst_reg = RST_DEVICES_U,
517 .rst_set_reg = RST_DEVICES_SET_U,
518 .rst_clr_reg = RST_DEVICES_CLR_U,
519};
520
521static unsigned long tegra20_clk_measure_input_freq(void) 475static unsigned long tegra20_clk_measure_input_freq(void)
522{ 476{
523 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 477 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
@@ -792,7 +746,7 @@ static void __init tegra20_audio_clk_init(void)
792 CLK_SET_RATE_PARENT, 2, 1); 746 CLK_SET_RATE_PARENT, 2, 1);
793 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 747 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
794 TEGRA_PERIPH_NO_RESET, clk_base, 748 TEGRA_PERIPH_NO_RESET, clk_base,
795 CLK_SET_RATE_PARENT, 89, &periph_u_regs, 749 CLK_SET_RATE_PARENT, 89,
796 periph_clk_enb_refcnt); 750 periph_clk_enb_refcnt);
797 clk_register_clkdev(clk, "audio_2x", NULL); 751 clk_register_clkdev(clk, "audio_2x", NULL);
798 clks[audio_2x] = clk; 752 clks[audio_2x] = clk;
@@ -815,56 +769,56 @@ static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
815static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 769static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
816 770
817static struct tegra_periph_init_data tegra_periph_clk_list[] = { 771static struct tegra_periph_init_data tegra_periph_clk_list[] = {
818 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 772 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1),
819 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 773 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2),
820 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 774 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out),
821 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 775 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in),
822 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 776 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1),
823 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 777 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2),
824 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 778 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3),
825 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 779 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4),
826 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi), 780 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, spi),
827 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio), 781 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, xio),
828 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc), 782 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, twc),
829 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide), 783 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, ide),
830 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash), 784 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, 0, ndflash),
831 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 785 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir),
832 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite), 786 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, 0, csite),
833 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la), 787 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, 0, la),
834 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 788 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr),
835 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 789 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi),
836 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 790 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde),
837 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 791 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi),
838 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 792 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp),
839 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 793 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe),
840 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 794 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x),
841 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 795 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d),
842 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 796 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d),
843 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 797 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor),
844 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 798 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1),
845 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 799 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2),
846 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 800 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3),
847 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 801 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4),
848 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 802 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve),
849 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 803 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo),
850 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 804 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac),
851 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 805 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor),
852 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 806 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1),
853 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 807 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2),
854 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 808 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3),
855 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc), 809 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, dvc),
856 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 810 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi),
857 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm), 811 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
858}; 812};
859 813
860static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 814static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
861 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta), 815 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, uarta),
862 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb), 816 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, uartb),
863 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc), 817 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, uartc),
864 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd), 818 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, uartd),
865 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte), 819 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, uarte),
866 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1), 820 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, disp1),
867 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2), 821 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, disp2),
868}; 822};
869 823
870static void __init tegra20_periph_clk_init(void) 824static void __init tegra20_periph_clk_init(void)
@@ -876,67 +830,58 @@ static void __init tegra20_periph_clk_init(void)
876 /* ac97 */ 830 /* ac97 */
877 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 831 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
878 TEGRA_PERIPH_ON_APB, 832 TEGRA_PERIPH_ON_APB,
879 clk_base, 0, 3, &periph_l_regs, 833 clk_base, 0, 3, periph_clk_enb_refcnt);
880 periph_clk_enb_refcnt);
881 clk_register_clkdev(clk, NULL, "tegra20-ac97"); 834 clk_register_clkdev(clk, NULL, "tegra20-ac97");
882 clks[ac97] = clk; 835 clks[ac97] = clk;
883 836
884 /* apbdma */ 837 /* apbdma */
885 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 838 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
886 0, 34, &periph_h_regs, 839 0, 34, periph_clk_enb_refcnt);
887 periph_clk_enb_refcnt);
888 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 840 clk_register_clkdev(clk, NULL, "tegra-apbdma");
889 clks[apbdma] = clk; 841 clks[apbdma] = clk;
890 842
891 /* rtc */ 843 /* rtc */
892 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 844 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
893 TEGRA_PERIPH_NO_RESET, 845 TEGRA_PERIPH_NO_RESET,
894 clk_base, 0, 4, &periph_l_regs, 846 clk_base, 0, 4, periph_clk_enb_refcnt);
895 periph_clk_enb_refcnt);
896 clk_register_clkdev(clk, NULL, "rtc-tegra"); 847 clk_register_clkdev(clk, NULL, "rtc-tegra");
897 clks[rtc] = clk; 848 clks[rtc] = clk;
898 849
899 /* timer */ 850 /* timer */
900 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 851 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
901 0, 5, &periph_l_regs, 852 0, 5, periph_clk_enb_refcnt);
902 periph_clk_enb_refcnt);
903 clk_register_clkdev(clk, NULL, "timer"); 853 clk_register_clkdev(clk, NULL, "timer");
904 clks[timer] = clk; 854 clks[timer] = clk;
905 855
906 /* kbc */ 856 /* kbc */
907 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 857 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
908 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 858 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
909 clk_base, 0, 36, &periph_h_regs, 859 clk_base, 0, 36, periph_clk_enb_refcnt);
910 periph_clk_enb_refcnt);
911 clk_register_clkdev(clk, NULL, "tegra-kbc"); 860 clk_register_clkdev(clk, NULL, "tegra-kbc");
912 clks[kbc] = clk; 861 clks[kbc] = clk;
913 862
914 /* csus */ 863 /* csus */
915 clk = tegra_clk_register_periph_gate("csus", "clk_m", 864 clk = tegra_clk_register_periph_gate("csus", "clk_m",
916 TEGRA_PERIPH_NO_RESET, 865 TEGRA_PERIPH_NO_RESET,
917 clk_base, 0, 92, &periph_u_regs, 866 clk_base, 0, 92, periph_clk_enb_refcnt);
918 periph_clk_enb_refcnt);
919 clk_register_clkdev(clk, "csus", "tengra_camera"); 867 clk_register_clkdev(clk, "csus", "tengra_camera");
920 clks[csus] = clk; 868 clks[csus] = clk;
921 869
922 /* vcp */ 870 /* vcp */
923 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, 871 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
924 clk_base, 0, 29, &periph_l_regs, 872 clk_base, 0, 29, periph_clk_enb_refcnt);
925 periph_clk_enb_refcnt);
926 clk_register_clkdev(clk, "vcp", "tegra-avp"); 873 clk_register_clkdev(clk, "vcp", "tegra-avp");
927 clks[vcp] = clk; 874 clks[vcp] = clk;
928 875
929 /* bsea */ 876 /* bsea */
930 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, 877 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
931 clk_base, 0, 62, &periph_h_regs, 878 clk_base, 0, 62, periph_clk_enb_refcnt);
932 periph_clk_enb_refcnt);
933 clk_register_clkdev(clk, "bsea", "tegra-avp"); 879 clk_register_clkdev(clk, "bsea", "tegra-avp");
934 clks[bsea] = clk; 880 clks[bsea] = clk;
935 881
936 /* bsev */ 882 /* bsev */
937 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, 883 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
938 clk_base, 0, 63, &periph_h_regs, 884 clk_base, 0, 63, periph_clk_enb_refcnt);
939 periph_clk_enb_refcnt);
940 clk_register_clkdev(clk, "bsev", "tegra-aes"); 885 clk_register_clkdev(clk, "bsev", "tegra-aes");
941 clks[bsev] = clk; 886 clks[bsev] = clk;
942 887
@@ -947,63 +892,61 @@ static void __init tegra20_periph_clk_init(void)
947 clk_base + CLK_SOURCE_EMC, 892 clk_base + CLK_SOURCE_EMC,
948 30, 2, 0, NULL); 893 30, 2, 0, NULL);
949 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 894 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
950 57, &periph_h_regs, periph_clk_enb_refcnt); 895 57, periph_clk_enb_refcnt);
951 clk_register_clkdev(clk, "emc", NULL); 896 clk_register_clkdev(clk, "emc", NULL);
952 clks[emc] = clk; 897 clks[emc] = clk;
953 898
954 /* usbd */ 899 /* usbd */
955 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 900 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
956 22, &periph_l_regs, periph_clk_enb_refcnt); 901 22, periph_clk_enb_refcnt);
957 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 902 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
958 clks[usbd] = clk; 903 clks[usbd] = clk;
959 904
960 /* usb2 */ 905 /* usb2 */
961 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 906 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
962 58, &periph_h_regs, periph_clk_enb_refcnt); 907 58, periph_clk_enb_refcnt);
963 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 908 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
964 clks[usb2] = clk; 909 clks[usb2] = clk;
965 910
966 /* usb3 */ 911 /* usb3 */
967 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 912 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
968 59, &periph_h_regs, periph_clk_enb_refcnt); 913 59, periph_clk_enb_refcnt);
969 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 914 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
970 clks[usb3] = clk; 915 clks[usb3] = clk;
971 916
972 /* dsi */ 917 /* dsi */
973 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 918 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
974 48, &periph_h_regs, periph_clk_enb_refcnt); 919 48, periph_clk_enb_refcnt);
975 clk_register_clkdev(clk, NULL, "dsi"); 920 clk_register_clkdev(clk, NULL, "dsi");
976 clks[dsi] = clk; 921 clks[dsi] = clk;
977 922
978 /* csi */ 923 /* csi */
979 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 924 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
980 0, 52, &periph_h_regs, 925 0, 52, periph_clk_enb_refcnt);
981 periph_clk_enb_refcnt);
982 clk_register_clkdev(clk, "csi", "tegra_camera"); 926 clk_register_clkdev(clk, "csi", "tegra_camera");
983 clks[csi] = clk; 927 clks[csi] = clk;
984 928
985 /* isp */ 929 /* isp */
986 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 930 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
987 &periph_l_regs, periph_clk_enb_refcnt); 931 periph_clk_enb_refcnt);
988 clk_register_clkdev(clk, "isp", "tegra_camera"); 932 clk_register_clkdev(clk, "isp", "tegra_camera");
989 clks[isp] = clk; 933 clks[isp] = clk;
990 934
991 /* pex */ 935 /* pex */
992 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 936 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
993 &periph_u_regs, periph_clk_enb_refcnt); 937 periph_clk_enb_refcnt);
994 clk_register_clkdev(clk, "pex", NULL); 938 clk_register_clkdev(clk, "pex", NULL);
995 clks[pex] = clk; 939 clks[pex] = clk;
996 940
997 /* afi */ 941 /* afi */
998 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 942 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
999 &periph_u_regs, periph_clk_enb_refcnt); 943 periph_clk_enb_refcnt);
1000 clk_register_clkdev(clk, "afi", NULL); 944 clk_register_clkdev(clk, "afi", NULL);
1001 clks[afi] = clk; 945 clks[afi] = clk;
1002 946
1003 /* pcie_xclk */ 947 /* pcie_xclk */
1004 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 948 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
1005 0, 74, &periph_u_regs, 949 0, 74, periph_clk_enb_refcnt);
1006 periph_clk_enb_refcnt);
1007 clk_register_clkdev(clk, "pcie_xclk", NULL); 950 clk_register_clkdev(clk, "pcie_xclk", NULL);
1008 clks[pcie_xclk] = clk; 951 clks[pcie_xclk] = clk;
1009 952
@@ -1011,8 +954,7 @@ static void __init tegra20_periph_clk_init(void)
1011 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 954 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
1012 26000000); 955 26000000);
1013 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 956 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
1014 clk_base, 0, 94, &periph_u_regs, 957 clk_base, 0, 94, periph_clk_enb_refcnt);
1015 periph_clk_enb_refcnt);
1016 clk_register_clkdev(clk, "cdev1", NULL); 958 clk_register_clkdev(clk, "cdev1", NULL);
1017 clks[cdev1] = clk; 959 clks[cdev1] = clk;
1018 960
@@ -1020,8 +962,7 @@ static void __init tegra20_periph_clk_init(void)
1020 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 962 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1021 26000000); 963 26000000);
1022 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 964 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1023 clk_base, 0, 93, &periph_u_regs, 965 clk_base, 0, 93, periph_clk_enb_refcnt);
1024 periph_clk_enb_refcnt);
1025 clk_register_clkdev(clk, "cdev2", NULL); 966 clk_register_clkdev(clk, "cdev2", NULL);
1026 clks[cdev2] = clk; 967 clks[cdev2] = clk;
1027 968
@@ -1312,6 +1253,9 @@ static void __init tegra20_clock_init(struct device_node *np)
1312 BUG(); 1253 BUG();
1313 } 1254 }
1314 1255
1256 if (tegra_clk_set_periph_banks(TEGRA20_CLK_PERIPH_BANKS) < 0)
1257 return;
1258
1315 tegra20_osc_clk_init(); 1259 tegra20_osc_clk_init();
1316 tegra20_pmc_clk_init(); 1260 tegra20_pmc_clk_init();
1317 tegra20_fixed_clk_init(); 1261 tegra20_fixed_clk_init();
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 147f5b9fed11..a66bdabb5c5c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -26,38 +26,6 @@
26 26
27#include "clk.h" 27#include "clk.h"
28 28
29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00c
32#define RST_DEVICES_V 0x358
33#define RST_DEVICES_W 0x35c
34#define RST_DEVICES_SET_L 0x300
35#define RST_DEVICES_CLR_L 0x304
36#define RST_DEVICES_SET_H 0x308
37#define RST_DEVICES_CLR_H 0x30c
38#define RST_DEVICES_SET_U 0x310
39#define RST_DEVICES_CLR_U 0x314
40#define RST_DEVICES_SET_V 0x430
41#define RST_DEVICES_CLR_V 0x434
42#define RST_DEVICES_SET_W 0x438
43#define RST_DEVICES_CLR_W 0x43c
44#define RST_DEVICES_NUM 5
45
46#define CLK_OUT_ENB_L 0x010
47#define CLK_OUT_ENB_H 0x014
48#define CLK_OUT_ENB_U 0x018
49#define CLK_OUT_ENB_V 0x360
50#define CLK_OUT_ENB_W 0x364
51#define CLK_OUT_ENB_SET_L 0x320
52#define CLK_OUT_ENB_CLR_L 0x324
53#define CLK_OUT_ENB_SET_H 0x328
54#define CLK_OUT_ENB_CLR_H 0x32c
55#define CLK_OUT_ENB_SET_U 0x330
56#define CLK_OUT_ENB_CLR_U 0x334
57#define CLK_OUT_ENB_SET_V 0x440
58#define CLK_OUT_ENB_CLR_V 0x444
59#define CLK_OUT_ENB_SET_W 0x448
60#define CLK_OUT_ENB_CLR_W 0x44c
61#define CLK_OUT_ENB_NUM 5 29#define CLK_OUT_ENB_NUM 5
62 30
63#define OSC_CTRL 0x50 31#define OSC_CTRL 0x50
@@ -92,6 +60,8 @@
92 60
93#define SYSTEM_CLK_RATE 0x030 61#define SYSTEM_CLK_RATE 0x030
94 62
63#define TEGRA30_CLK_PERIPH_BANKS 5
64
95#define PLLC_BASE 0x80 65#define PLLC_BASE 0x80
96#define PLLC_MISC 0x8c 66#define PLLC_MISC 0x8c
97#define PLLM_BASE 0x90 67#define PLLM_BASE 0x90
@@ -280,43 +250,43 @@ static DEFINE_SPINLOCK(pll_d_lock);
280static DEFINE_SPINLOCK(sysrate_lock); 250static DEFINE_SPINLOCK(sysrate_lock);
281 251
282#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 252#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
283 _clk_num, _regs, _gate_flags, _clk_id) \ 253 _clk_num, _gate_flags, _clk_id) \
284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 254 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
285 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs, \ 255 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
286 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id) 256 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
287 257
288#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 258#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
289 _clk_num, _regs, _gate_flags, _clk_id) \ 259 _clk_num, _gate_flags, _clk_id) \
290 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 260 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
291 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 261 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
292 _regs, _clk_num, periph_clk_enb_refcnt, \ 262 _clk_num, periph_clk_enb_refcnt, \
293 _gate_flags, _clk_id) 263 _gate_flags, _clk_id)
294 264
295#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 265#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
296 _clk_num, _regs, _gate_flags, _clk_id) \ 266 _clk_num, _gate_flags, _clk_id) \
297 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 267 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
298 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs,\ 268 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
299 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id) 269 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
300 270
301#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 271#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
302 _clk_num, _regs, _gate_flags, _clk_id) \ 272 _clk_num, _gate_flags, _clk_id) \
303 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 273 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
304 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 274 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
305 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 275 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
306 periph_clk_enb_refcnt, _gate_flags, _clk_id) 276 periph_clk_enb_refcnt, _gate_flags, _clk_id)
307 277
308#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 278#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
309 _clk_num, _regs, _clk_id) \ 279 _clk_num, _clk_id) \
310 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 280 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
311 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ 281 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
312 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 282 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
313 periph_clk_enb_refcnt, 0, _clk_id) 283 periph_clk_enb_refcnt, 0, _clk_id)
314 284
315#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 285#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
316 _mux_shift, _mux_width, _clk_num, _regs, \ 286 _mux_shift, _mux_width, _clk_num, \
317 _gate_flags, _clk_id) \ 287 _gate_flags, _clk_id) \
318 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 288 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
319 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 289 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
320 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 290 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
321 _clk_id) 291 _clk_id)
322 292
@@ -695,52 +665,6 @@ static struct tegra_clk_pll_params pll_e_params = {
695 .lock_delay = 300, 665 .lock_delay = 300,
696}; 666};
697 667
698/* Peripheral clock registers */
699static struct tegra_clk_periph_regs periph_l_regs = {
700 .enb_reg = CLK_OUT_ENB_L,
701 .enb_set_reg = CLK_OUT_ENB_SET_L,
702 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
703 .rst_reg = RST_DEVICES_L,
704 .rst_set_reg = RST_DEVICES_SET_L,
705 .rst_clr_reg = RST_DEVICES_CLR_L,
706};
707
708static struct tegra_clk_periph_regs periph_h_regs = {
709 .enb_reg = CLK_OUT_ENB_H,
710 .enb_set_reg = CLK_OUT_ENB_SET_H,
711 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
712 .rst_reg = RST_DEVICES_H,
713 .rst_set_reg = RST_DEVICES_SET_H,
714 .rst_clr_reg = RST_DEVICES_CLR_H,
715};
716
717static struct tegra_clk_periph_regs periph_u_regs = {
718 .enb_reg = CLK_OUT_ENB_U,
719 .enb_set_reg = CLK_OUT_ENB_SET_U,
720 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
721 .rst_reg = RST_DEVICES_U,
722 .rst_set_reg = RST_DEVICES_SET_U,
723 .rst_clr_reg = RST_DEVICES_CLR_U,
724};
725
726static struct tegra_clk_periph_regs periph_v_regs = {
727 .enb_reg = CLK_OUT_ENB_V,
728 .enb_set_reg = CLK_OUT_ENB_SET_V,
729 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
730 .rst_reg = RST_DEVICES_V,
731 .rst_set_reg = RST_DEVICES_SET_V,
732 .rst_clr_reg = RST_DEVICES_CLR_V,
733};
734
735static struct tegra_clk_periph_regs periph_w_regs = {
736 .enb_reg = CLK_OUT_ENB_W,
737 .enb_set_reg = CLK_OUT_ENB_SET_W,
738 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
739 .rst_reg = RST_DEVICES_W,
740 .rst_set_reg = RST_DEVICES_SET_W,
741 .rst_clr_reg = RST_DEVICES_CLR_W,
742};
743
744static void tegra30_clk_measure_input_freq(void) 668static void tegra30_clk_measure_input_freq(void)
745{ 669{
746 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 670 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
@@ -1160,7 +1084,7 @@ static void __init tegra30_audio_clk_init(void)
1160 &clk_doubler_lock); 1084 &clk_doubler_lock);
1161 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1085 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1162 TEGRA_PERIPH_NO_RESET, clk_base, 1086 TEGRA_PERIPH_NO_RESET, clk_base,
1163 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1087 CLK_SET_RATE_PARENT, 113,
1164 periph_clk_enb_refcnt); 1088 periph_clk_enb_refcnt);
1165 clk_register_clkdev(clk, "audio0_2x", NULL); 1089 clk_register_clkdev(clk, "audio0_2x", NULL);
1166 clks[audio0_2x] = clk; 1090 clks[audio0_2x] = clk;
@@ -1173,7 +1097,7 @@ static void __init tegra30_audio_clk_init(void)
1173 &clk_doubler_lock); 1097 &clk_doubler_lock);
1174 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1098 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1175 TEGRA_PERIPH_NO_RESET, clk_base, 1099 TEGRA_PERIPH_NO_RESET, clk_base,
1176 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1100 CLK_SET_RATE_PARENT, 114,
1177 periph_clk_enb_refcnt); 1101 periph_clk_enb_refcnt);
1178 clk_register_clkdev(clk, "audio1_2x", NULL); 1102 clk_register_clkdev(clk, "audio1_2x", NULL);
1179 clks[audio1_2x] = clk; 1103 clks[audio1_2x] = clk;
@@ -1186,7 +1110,7 @@ static void __init tegra30_audio_clk_init(void)
1186 &clk_doubler_lock); 1110 &clk_doubler_lock);
1187 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1111 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1188 TEGRA_PERIPH_NO_RESET, clk_base, 1112 TEGRA_PERIPH_NO_RESET, clk_base,
1189 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1113 CLK_SET_RATE_PARENT, 115,
1190 periph_clk_enb_refcnt); 1114 periph_clk_enb_refcnt);
1191 clk_register_clkdev(clk, "audio2_2x", NULL); 1115 clk_register_clkdev(clk, "audio2_2x", NULL);
1192 clks[audio2_2x] = clk; 1116 clks[audio2_2x] = clk;
@@ -1199,7 +1123,7 @@ static void __init tegra30_audio_clk_init(void)
1199 &clk_doubler_lock); 1123 &clk_doubler_lock);
1200 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1124 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1201 TEGRA_PERIPH_NO_RESET, clk_base, 1125 TEGRA_PERIPH_NO_RESET, clk_base,
1202 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1126 CLK_SET_RATE_PARENT, 116,
1203 periph_clk_enb_refcnt); 1127 periph_clk_enb_refcnt);
1204 clk_register_clkdev(clk, "audio3_2x", NULL); 1128 clk_register_clkdev(clk, "audio3_2x", NULL);
1205 clks[audio3_2x] = clk; 1129 clks[audio3_2x] = clk;
@@ -1212,7 +1136,7 @@ static void __init tegra30_audio_clk_init(void)
1212 &clk_doubler_lock); 1136 &clk_doubler_lock);
1213 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1137 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1214 TEGRA_PERIPH_NO_RESET, clk_base, 1138 TEGRA_PERIPH_NO_RESET, clk_base,
1215 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1139 CLK_SET_RATE_PARENT, 117,
1216 periph_clk_enb_refcnt); 1140 periph_clk_enb_refcnt);
1217 clk_register_clkdev(clk, "audio4_2x", NULL); 1141 clk_register_clkdev(clk, "audio4_2x", NULL);
1218 clks[audio4_2x] = clk; 1142 clks[audio4_2x] = clk;
@@ -1225,7 +1149,7 @@ static void __init tegra30_audio_clk_init(void)
1225 &clk_doubler_lock); 1149 &clk_doubler_lock);
1226 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1150 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1227 TEGRA_PERIPH_NO_RESET, clk_base, 1151 TEGRA_PERIPH_NO_RESET, clk_base,
1228 CLK_SET_RATE_PARENT, 118, &periph_v_regs, 1152 CLK_SET_RATE_PARENT, 118,
1229 periph_clk_enb_refcnt); 1153 periph_clk_enb_refcnt);
1230 clk_register_clkdev(clk, "spdif_2x", NULL); 1154 clk_register_clkdev(clk, "spdif_2x", NULL);
1231 clks[spdif_2x] = clk; 1155 clks[spdif_2x] = clk;
@@ -1444,77 +1368,77 @@ static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1444 "pll_d2_out0" }; 1368 "pll_d2_out0" };
1445 1369
1446static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1370static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1447 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1371 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, i2s0),
1448 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1372 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1),
1449 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1373 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2),
1450 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1374 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, i2s3),
1451 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1375 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, i2s4),
1452 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1376 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out),
1453 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1377 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in),
1454 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1378 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, d_audio),
1455 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1379 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, dam0),
1456 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1), 1380 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, dam1),
1457 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2), 1381 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, dam2),
1458 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda), 1382 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, 0, hda),
1459 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x), 1383 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, 0, hda2codec_2x),
1460 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1384 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1),
1461 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1385 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2),
1462 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1386 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3),
1463 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1387 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4),
1464 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1388 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, sbc5),
1465 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1389 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, sbc6),
1466 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob), 1390 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, sata_oob),
1467 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata), 1391 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, sata),
1468 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash), 1392 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, ndflash),
1469 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1393 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, ndspeed),
1470 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1394 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir),
1471 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite), 1395 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, csite),
1472 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1396 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, la),
1473 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1397 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr),
1474 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1398 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi),
1475 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1399 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tsensor),
1476 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1400 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, i2cslow),
1477 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1401 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde),
1478 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1402 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi),
1479 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1403 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp),
1480 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 1404 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe),
1481 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1405 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x),
1482 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1406 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1483 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1407 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1484 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 1408 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d),
1485 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se), 1409 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, se),
1486 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect), 1410 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, mselect),
1487 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1411 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor),
1488 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1412 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1),
1489 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1413 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2),
1490 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1414 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3),
1491 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1415 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4),
1492 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 1416 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve),
1493 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 1417 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo),
1494 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 1418 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac),
1495 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1419 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, 0, actmon),
1496 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1420 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor),
1497 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 1421 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1),
1498 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 1422 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2),
1499 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 1423 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3),
1500 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4), 1424 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA_PERIPH_ON_APB, i2c4),
1501 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5), 1425 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA_PERIPH_ON_APB, i2c5),
1502 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1426 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, uarta),
1503 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1427 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, uartb),
1504 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1428 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, uartc),
1505 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1429 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, uartd),
1506 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte), 1430 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, uarte),
1507 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1431 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi),
1508 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1432 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, extern1),
1509 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1433 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, extern2),
1510 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1434 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, extern3),
1511 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm), 1435 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, periph_clk_enb_refcnt, 0, pwm),
1512}; 1436};
1513 1437
1514static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1438static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1515 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1439 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, 0, disp1),
1516 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2), 1440 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, 0, disp2),
1517 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib), 1441 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, dsib),
1518}; 1442};
1519 1443
1520static void __init tegra30_periph_clk_init(void) 1444static void __init tegra30_periph_clk_init(void)
@@ -1525,166 +1449,154 @@ static void __init tegra30_periph_clk_init(void)
1525 1449
1526 /* apbdma */ 1450 /* apbdma */
1527 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1451 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1528 &periph_h_regs, periph_clk_enb_refcnt); 1452 periph_clk_enb_refcnt);
1529 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1453 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1530 clks[apbdma] = clk; 1454 clks[apbdma] = clk;
1531 1455
1532 /* rtc */ 1456 /* rtc */
1533 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1457 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1534 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1458 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1535 clk_base, 0, 4, &periph_l_regs, 1459 clk_base, 0, 4, periph_clk_enb_refcnt);
1536 periph_clk_enb_refcnt);
1537 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1460 clk_register_clkdev(clk, NULL, "rtc-tegra");
1538 clks[rtc] = clk; 1461 clks[rtc] = clk;
1539 1462
1540 /* timer */ 1463 /* timer */
1541 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1464 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1542 5, &periph_l_regs, periph_clk_enb_refcnt); 1465 5, periph_clk_enb_refcnt);
1543 clk_register_clkdev(clk, NULL, "timer"); 1466 clk_register_clkdev(clk, NULL, "timer");
1544 clks[timer] = clk; 1467 clks[timer] = clk;
1545 1468
1546 /* kbc */ 1469 /* kbc */
1547 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1470 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1548 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1471 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1549 clk_base, 0, 36, &periph_h_regs, 1472 clk_base, 0, 36, periph_clk_enb_refcnt);
1550 periph_clk_enb_refcnt);
1551 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1473 clk_register_clkdev(clk, NULL, "tegra-kbc");
1552 clks[kbc] = clk; 1474 clks[kbc] = clk;
1553 1475
1554 /* csus */ 1476 /* csus */
1555 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1477 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1556 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1478 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1557 clk_base, 0, 92, &periph_u_regs, 1479 clk_base, 0, 92, periph_clk_enb_refcnt);
1558 periph_clk_enb_refcnt);
1559 clk_register_clkdev(clk, "csus", "tengra_camera"); 1480 clk_register_clkdev(clk, "csus", "tengra_camera");
1560 clks[csus] = clk; 1481 clks[csus] = clk;
1561 1482
1562 /* vcp */ 1483 /* vcp */
1563 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1484 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1564 &periph_l_regs, periph_clk_enb_refcnt); 1485 periph_clk_enb_refcnt);
1565 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1486 clk_register_clkdev(clk, "vcp", "tegra-avp");
1566 clks[vcp] = clk; 1487 clks[vcp] = clk;
1567 1488
1568 /* bsea */ 1489 /* bsea */
1569 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1490 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1570 62, &periph_h_regs, periph_clk_enb_refcnt); 1491 62, periph_clk_enb_refcnt);
1571 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1492 clk_register_clkdev(clk, "bsea", "tegra-avp");
1572 clks[bsea] = clk; 1493 clks[bsea] = clk;
1573 1494
1574 /* bsev */ 1495 /* bsev */
1575 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1496 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1576 63, &periph_h_regs, periph_clk_enb_refcnt); 1497 63, periph_clk_enb_refcnt);
1577 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1498 clk_register_clkdev(clk, "bsev", "tegra-aes");
1578 clks[bsev] = clk; 1499 clks[bsev] = clk;
1579 1500
1580 /* usbd */ 1501 /* usbd */
1581 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1502 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1582 22, &periph_l_regs, periph_clk_enb_refcnt); 1503 22, periph_clk_enb_refcnt);
1583 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1504 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1584 clks[usbd] = clk; 1505 clks[usbd] = clk;
1585 1506
1586 /* usb2 */ 1507 /* usb2 */
1587 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1508 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1588 58, &periph_h_regs, periph_clk_enb_refcnt); 1509 58, periph_clk_enb_refcnt);
1589 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1510 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1590 clks[usb2] = clk; 1511 clks[usb2] = clk;
1591 1512
1592 /* usb3 */ 1513 /* usb3 */
1593 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1514 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1594 59, &periph_h_regs, periph_clk_enb_refcnt); 1515 59, periph_clk_enb_refcnt);
1595 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1516 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1596 clks[usb3] = clk; 1517 clks[usb3] = clk;
1597 1518
1598 /* dsia */ 1519 /* dsia */
1599 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1520 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1600 0, 48, &periph_h_regs, 1521 0, 48, periph_clk_enb_refcnt);
1601 periph_clk_enb_refcnt);
1602 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1522 clk_register_clkdev(clk, "dsia", "tegradc.0");
1603 clks[dsia] = clk; 1523 clks[dsia] = clk;
1604 1524
1605 /* csi */ 1525 /* csi */
1606 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1526 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1607 0, 52, &periph_h_regs, 1527 0, 52, periph_clk_enb_refcnt);
1608 periph_clk_enb_refcnt);
1609 clk_register_clkdev(clk, "csi", "tegra_camera"); 1528 clk_register_clkdev(clk, "csi", "tegra_camera");
1610 clks[csi] = clk; 1529 clks[csi] = clk;
1611 1530
1612 /* isp */ 1531 /* isp */
1613 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1532 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1614 &periph_l_regs, periph_clk_enb_refcnt); 1533 periph_clk_enb_refcnt);
1615 clk_register_clkdev(clk, "isp", "tegra_camera"); 1534 clk_register_clkdev(clk, "isp", "tegra_camera");
1616 clks[isp] = clk; 1535 clks[isp] = clk;
1617 1536
1618 /* pcie */ 1537 /* pcie */
1619 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1538 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1620 70, &periph_u_regs, periph_clk_enb_refcnt); 1539 70, periph_clk_enb_refcnt);
1621 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1540 clk_register_clkdev(clk, "pcie", "tegra-pcie");
1622 clks[pcie] = clk; 1541 clks[pcie] = clk;
1623 1542
1624 /* afi */ 1543 /* afi */
1625 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1544 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1626 &periph_u_regs, periph_clk_enb_refcnt); 1545 periph_clk_enb_refcnt);
1627 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1546 clk_register_clkdev(clk, "afi", "tegra-pcie");
1628 clks[afi] = clk; 1547 clks[afi] = clk;
1629 1548
1630 /* pciex */ 1549 /* pciex */
1631 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, 1550 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1632 74, &periph_u_regs, periph_clk_enb_refcnt); 1551 74, periph_clk_enb_refcnt);
1633 clk_register_clkdev(clk, "pciex", "tegra-pcie"); 1552 clk_register_clkdev(clk, "pciex", "tegra-pcie");
1634 clks[pciex] = clk; 1553 clks[pciex] = clk;
1635 1554
1636 /* kfuse */ 1555 /* kfuse */
1637 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1556 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1638 TEGRA_PERIPH_ON_APB, 1557 TEGRA_PERIPH_ON_APB,
1639 clk_base, 0, 40, &periph_h_regs, 1558 clk_base, 0, 40, periph_clk_enb_refcnt);
1640 periph_clk_enb_refcnt);
1641 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1559 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1642 clks[kfuse] = clk; 1560 clks[kfuse] = clk;
1643 1561
1644 /* fuse */ 1562 /* fuse */
1645 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1563 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1646 TEGRA_PERIPH_ON_APB, 1564 TEGRA_PERIPH_ON_APB,
1647 clk_base, 0, 39, &periph_h_regs, 1565 clk_base, 0, 39, periph_clk_enb_refcnt);
1648 periph_clk_enb_refcnt);
1649 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1566 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1650 clks[fuse] = clk; 1567 clks[fuse] = clk;
1651 1568
1652 /* fuse_burn */ 1569 /* fuse_burn */
1653 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1570 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1654 TEGRA_PERIPH_ON_APB, 1571 TEGRA_PERIPH_ON_APB,
1655 clk_base, 0, 39, &periph_h_regs, 1572 clk_base, 0, 39, periph_clk_enb_refcnt);
1656 periph_clk_enb_refcnt);
1657 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1573 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1658 clks[fuse_burn] = clk; 1574 clks[fuse_burn] = clk;
1659 1575
1660 /* apbif */ 1576 /* apbif */
1661 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1577 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1662 clk_base, 0, 107, &periph_v_regs, 1578 clk_base, 0, 107, periph_clk_enb_refcnt);
1663 periph_clk_enb_refcnt);
1664 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1579 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1665 clks[apbif] = clk; 1580 clks[apbif] = clk;
1666 1581
1667 /* hda2hdmi */ 1582 /* hda2hdmi */
1668 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1583 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1669 TEGRA_PERIPH_ON_APB, 1584 TEGRA_PERIPH_ON_APB,
1670 clk_base, 0, 128, &periph_w_regs, 1585 clk_base, 0, 128, periph_clk_enb_refcnt);
1671 periph_clk_enb_refcnt);
1672 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1586 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1673 clks[hda2hdmi] = clk; 1587 clks[hda2hdmi] = clk;
1674 1588
1675 /* sata_cold */ 1589 /* sata_cold */
1676 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1590 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1677 TEGRA_PERIPH_ON_APB, 1591 TEGRA_PERIPH_ON_APB,
1678 clk_base, 0, 129, &periph_w_regs, 1592 clk_base, 0, 129, periph_clk_enb_refcnt);
1679 periph_clk_enb_refcnt);
1680 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1593 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1681 clks[sata_cold] = clk; 1594 clks[sata_cold] = clk;
1682 1595
1683 /* dtv */ 1596 /* dtv */
1684 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1597 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1685 TEGRA_PERIPH_ON_APB, 1598 TEGRA_PERIPH_ON_APB,
1686 clk_base, 0, 79, &periph_u_regs, 1599 clk_base, 0, 79, periph_clk_enb_refcnt);
1687 periph_clk_enb_refcnt);
1688 clk_register_clkdev(clk, NULL, "dtv"); 1600 clk_register_clkdev(clk, NULL, "dtv");
1689 clks[dtv] = clk; 1601 clks[dtv] = clk;
1690 1602
@@ -1695,7 +1607,7 @@ static void __init tegra30_periph_clk_init(void)
1695 clk_base + CLK_SOURCE_EMC, 1607 clk_base + CLK_SOURCE_EMC,
1696 30, 2, 0, NULL); 1608 30, 2, 0, NULL);
1697 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1609 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1698 57, &periph_h_regs, periph_clk_enb_refcnt); 1610 57, periph_clk_enb_refcnt);
1699 clk_register_clkdev(clk, "emc", NULL); 1611 clk_register_clkdev(clk, "emc", NULL);
1700 clks[emc] = clk; 1612 clks[emc] = clk;
1701 1613
@@ -2007,6 +1919,9 @@ static void __init tegra30_clock_init(struct device_node *np)
2007 BUG(); 1919 BUG();
2008 } 1920 }
2009 1921
1922 if (tegra_clk_set_periph_banks(TEGRA30_CLK_PERIPH_BANKS) < 0)
1923 return;
1924
2010 tegra30_osc_clk_init(); 1925 tegra30_osc_clk_init();
2011 tegra30_fixed_clk_init(); 1926 tegra30_fixed_clk_init();
2012 tegra30_pll_init(); 1927 tegra30_pll_init();
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 86581ac1fd69..07f76df2583b 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -21,10 +21,114 @@
21 21
22#include "clk.h" 22#include "clk.h"
23 23
24#define CLK_OUT_ENB_L 0x010
25#define CLK_OUT_ENB_H 0x014
26#define CLK_OUT_ENB_U 0x018
27#define CLK_OUT_ENB_V 0x360
28#define CLK_OUT_ENB_W 0x364
29#define CLK_OUT_ENB_X 0x280
30#define CLK_OUT_ENB_SET_L 0x320
31#define CLK_OUT_ENB_CLR_L 0x324
32#define CLK_OUT_ENB_SET_H 0x328
33#define CLK_OUT_ENB_CLR_H 0x32c
34#define CLK_OUT_ENB_SET_U 0x330
35#define CLK_OUT_ENB_CLR_U 0x334
36#define CLK_OUT_ENB_SET_V 0x440
37#define CLK_OUT_ENB_CLR_V 0x444
38#define CLK_OUT_ENB_SET_W 0x448
39#define CLK_OUT_ENB_CLR_W 0x44c
40#define CLK_OUT_ENB_SET_X 0x284
41#define CLK_OUT_ENB_CLR_X 0x288
42
43#define RST_DEVICES_L 0x004
44#define RST_DEVICES_H 0x008
45#define RST_DEVICES_U 0x00C
46#define RST_DFLL_DVCO 0x2F4
47#define RST_DEVICES_V 0x358
48#define RST_DEVICES_W 0x35C
49#define RST_DEVICES_X 0x28C
50#define RST_DEVICES_SET_L 0x300
51#define RST_DEVICES_CLR_L 0x304
52#define RST_DEVICES_SET_H 0x308
53#define RST_DEVICES_CLR_H 0x30c
54#define RST_DEVICES_SET_U 0x310
55#define RST_DEVICES_CLR_U 0x314
56#define RST_DEVICES_SET_V 0x430
57#define RST_DEVICES_CLR_V 0x434
58#define RST_DEVICES_SET_W 0x438
59#define RST_DEVICES_CLR_W 0x43c
60
24/* Global data of Tegra CPU CAR ops */ 61/* Global data of Tegra CPU CAR ops */
25static struct tegra_cpu_car_ops dummy_car_ops; 62static struct tegra_cpu_car_ops dummy_car_ops;
26struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; 63struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
27 64
65static int periph_banks;
66
67static struct tegra_clk_periph_regs periph_regs[] = {
68 [0] = {
69 .enb_reg = CLK_OUT_ENB_L,
70 .enb_set_reg = CLK_OUT_ENB_SET_L,
71 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
72 .rst_reg = RST_DEVICES_L,
73 .rst_set_reg = RST_DEVICES_SET_L,
74 .rst_clr_reg = RST_DEVICES_CLR_L,
75 },
76 [1] = {
77 .enb_reg = CLK_OUT_ENB_H,
78 .enb_set_reg = CLK_OUT_ENB_SET_H,
79 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
80 .rst_reg = RST_DEVICES_H,
81 .rst_set_reg = RST_DEVICES_SET_H,
82 .rst_clr_reg = RST_DEVICES_CLR_H,
83 },
84 [2] = {
85 .enb_reg = CLK_OUT_ENB_U,
86 .enb_set_reg = CLK_OUT_ENB_SET_U,
87 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
88 .rst_reg = RST_DEVICES_U,
89 .rst_set_reg = RST_DEVICES_SET_U,
90 .rst_clr_reg = RST_DEVICES_CLR_U,
91 },
92 [3] = {
93 .enb_reg = CLK_OUT_ENB_V,
94 .enb_set_reg = CLK_OUT_ENB_SET_V,
95 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
96 .rst_reg = RST_DEVICES_V,
97 .rst_set_reg = RST_DEVICES_SET_V,
98 .rst_clr_reg = RST_DEVICES_CLR_V,
99 },
100 [4] = {
101 .enb_reg = CLK_OUT_ENB_W,
102 .enb_set_reg = CLK_OUT_ENB_SET_W,
103 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
104 .rst_reg = RST_DEVICES_W,
105 .rst_set_reg = RST_DEVICES_SET_W,
106 .rst_clr_reg = RST_DEVICES_CLR_W,
107 },
108};
109
110struct tegra_clk_periph_regs *get_reg_bank(int clkid)
111{
112 int reg_bank = clkid / 32;
113
114 if (reg_bank < periph_banks)
115 return &periph_regs[reg_bank];
116 else {
117 WARN_ON(1);
118 return NULL;
119 }
120}
121
122int __init tegra_clk_set_periph_banks(int num)
123{
124 if (num > ARRAY_SIZE(periph_regs))
125 return -EINVAL;
126
127 periph_banks = num;
128
129 return 0;
130}
131
28void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 132void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
29 struct clk *clks[], int clk_max) 133 struct clk *clks[], int clk_max)
30{ 134{
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 07cfacd91686..730d37b39488 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -400,8 +400,7 @@ void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
400extern const struct clk_ops tegra_clk_periph_gate_ops; 400extern const struct clk_ops tegra_clk_periph_gate_ops;
401struct clk *tegra_clk_register_periph_gate(const char *name, 401struct clk *tegra_clk_register_periph_gate(const char *name,
402 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 402 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
403 unsigned long flags, int clk_num, 403 unsigned long flags, int clk_num, int *enable_refcnt);
404 struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
405 404
406/** 405/**
407 * struct clk-periph - peripheral clock 406 * struct clk-periph - peripheral clock
@@ -443,7 +442,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
443 442
444#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 443#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
445 _div_shift, _div_width, _div_frac_width, \ 444 _div_shift, _div_width, _div_frac_width, \
446 _div_flags, _clk_num, _enb_refcnt, _regs, \ 445 _div_flags, _clk_num, _enb_refcnt, \
447 _gate_flags, _table) \ 446 _gate_flags, _table) \
448 { \ 447 { \
449 .mux = { \ 448 .mux = { \
@@ -462,7 +461,6 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
462 .flags = _gate_flags, \ 461 .flags = _gate_flags, \
463 .clk_num = _clk_num, \ 462 .clk_num = _clk_num, \
464 .enable_refcnt = _enb_refcnt, \ 463 .enable_refcnt = _enb_refcnt, \
465 .regs = _regs, \
466 }, \ 464 }, \
467 .mux_ops = &clk_mux_ops, \ 465 .mux_ops = &clk_mux_ops, \
468 .div_ops = &tegra_clk_frac_div_ops, \ 466 .div_ops = &tegra_clk_frac_div_ops, \
@@ -483,7 +481,7 @@ struct tegra_periph_init_data {
483 481
484#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 482#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
485 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 483 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
486 _div_width, _div_frac_width, _div_flags, _regs, \ 484 _div_width, _div_frac_width, _div_flags, \
487 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\ 485 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
488 _flags) \ 486 _flags) \
489 { \ 487 { \
@@ -495,7 +493,7 @@ struct tegra_periph_init_data {
495 _mux_flags, _div_shift, \ 493 _mux_flags, _div_shift, \
496 _div_width, _div_frac_width, \ 494 _div_width, _div_frac_width, \
497 _div_flags, _clk_num, \ 495 _div_flags, _clk_num, \
498 _enb_refcnt, _regs, \ 496 _enb_refcnt, \
499 _gate_flags, _table), \ 497 _gate_flags, _table), \
500 .offset = _offset, \ 498 .offset = _offset, \
501 .con_id = _con_id, \ 499 .con_id = _con_id, \
@@ -505,12 +503,12 @@ struct tegra_periph_init_data {
505 503
506#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 504#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
507 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 505 _mux_shift, _mux_width, _mux_flags, _div_shift, \
508 _div_width, _div_frac_width, _div_flags, _regs, \ 506 _div_width, _div_frac_width, _div_flags, \
509 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 507 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \
510 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 508 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
511 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 509 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
512 _div_shift, _div_width, _div_frac_width, _div_flags, \ 510 _div_shift, _div_width, _div_frac_width, _div_flags, \
513 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 511 _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
514 NULL, 0) 512 NULL, 0)
515 513
516/** 514/**
@@ -587,6 +585,9 @@ void tegra_init_from_table(struct tegra_clk_init_table *tbl,
587void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 585void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
588 struct clk *clks[], int clk_max); 586 struct clk *clks[], int clk_max);
589 587
588struct tegra_clk_periph_regs *get_reg_bank(int clkid);
589int tegra_clk_set_periph_banks(int num);
590
590void tegra114_clock_tune_cpu_trimmers_high(void); 591void tegra114_clock_tune_cpu_trimmers_high(void);
591void tegra114_clock_tune_cpu_trimmers_low(void); 592void tegra114_clock_tune_cpu_trimmers_low(void);
592void tegra114_clock_tune_cpu_trimmers_init(void); 593void tegra114_clock_tune_cpu_trimmers_init(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 02:34:18 -0500