1 files changed, 24 insertions, 13 deletions

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e2c6ca0431d6..dbe7c8003c5c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
         /* PLLU */
         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
                             0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
-                            TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
+                            TEGRA_PLL_SET_LFCON,
                             pll_u_freq_table,
                             NULL);
         clk_register_clkdev(clk, "pll_u", NULL);
@@ -1026,7 +1026,8 @@ static void __init tegra30_pll_init(void)
 
         /* PLLE */
         clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
-                               ARRAY_SIZE(pll_e_parents), 0,
+                               ARRAY_SIZE(pll_e_parents),
+                               CLK_SET_RATE_NO_REPARENT,
                                clk_base + PLLE_AUX, 2, 1, 0, NULL);
         clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
                              CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
@@ -1086,7 +1087,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* audio0 */
         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
@@ -1096,7 +1098,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* audio1 */
         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
@@ -1106,7 +1109,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* audio2 */
         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
@@ -1116,7 +1120,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* audio3 */
         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
@@ -1126,7 +1131,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* audio4 */
         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
@@ -1136,7 +1142,8 @@ static void __init tegra30_audio_clk_init(void)
 
         /* spdif */
         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
-                                ARRAY_SIZE(mux_audio_sync_clk), 0,
+                                ARRAY_SIZE(mux_audio_sync_clk),
+                                CLK_SET_RATE_NO_REPARENT,
                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
@@ -1229,7 +1236,8 @@ static void __init tegra30_pmc_clk_init(void)
 
         /* clk_out_1 */
         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
-                               ARRAY_SIZE(clk_out1_parents), 0,
+                               ARRAY_SIZE(clk_out1_parents),
+                               CLK_SET_RATE_NO_REPARENT,
                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
                                &clk_out_lock);
         clks[clk_out_1_mux] = clk;
@@ -1241,7 +1249,8 @@ static void __init tegra30_pmc_clk_init(void)
 
         /* clk_out_2 */
         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
-                               ARRAY_SIZE(clk_out2_parents), 0,
+                               ARRAY_SIZE(clk_out2_parents),
+                               CLK_SET_RATE_NO_REPARENT,
                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
                                &clk_out_lock);
         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1252,7 +1261,8 @@ static void __init tegra30_pmc_clk_init(void)
 
         /* clk_out_3 */
         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
-                               ARRAY_SIZE(clk_out3_parents), 0,
+                               ARRAY_SIZE(clk_out3_parents),
+                               CLK_SET_RATE_NO_REPARENT,
                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
                                &clk_out_lock);
         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1679,7 +1689,8 @@ static void __init tegra30_periph_clk_init(void)
 
         /* emc */
         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-                               ARRAY_SIZE(mux_pllmcp_clkm), 0,
+                               ARRAY_SIZE(mux_pllmcp_clkm),
+                               CLK_SET_RATE_NO_REPARENT,
                                clk_base + CLK_SOURCE_EMC,
                                30, 2, 0, NULL);
         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
@@ -1901,7 +1912,7 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
 #endif
 };
 
-static __initdata struct tegra_clk_init_table init_table[] = {
+static struct tegra_clk_init_table init_table[] __initdata = {
         {uarta, pll_p, 408000000, 0},
         {uartb, pll_p, 408000000, 0},
         {uartc, pll_p, 408000000, 0},