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path: root/drivers/clk/tegra/clk-tegra30.c
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Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
-rw-r--r--drivers/clk/tegra/clk-tegra30.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba99e3844106..e2c6ca0431d6 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -252,6 +252,9 @@
252#define CLK_RESET_CCLK_RUN_POLICY 2 252#define CLK_RESET_CCLK_RUN_POLICY 2
253#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 253#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
254 254
255/* PLLM override registers */
256#define PMC_PLLM_WB0_OVERRIDE 0x1dc
257
255#ifdef CONFIG_PM_SLEEP 258#ifdef CONFIG_PM_SLEEP
256static struct cpu_clk_suspend_context { 259static struct cpu_clk_suspend_context {
257 u32 pllx_misc; 260 u32 pllx_misc;
@@ -563,6 +566,18 @@ static struct tegra_clk_pll_params pll_c_params = {
563 .lock_delay = 300, 566 .lock_delay = 300,
564}; 567};
565 568
569static struct div_nmp pllm_nmp = {
570 .divn_shift = 8,
571 .divn_width = 10,
572 .override_divn_shift = 5,
573 .divm_shift = 0,
574 .divm_width = 5,
575 .override_divm_shift = 0,
576 .divp_shift = 20,
577 .divp_width = 3,
578 .override_divp_shift = 15,
579};
580
566static struct tegra_clk_pll_params pll_m_params = { 581static struct tegra_clk_pll_params pll_m_params = {
567 .input_min = 2000000, 582 .input_min = 2000000,
568 .input_max = 31000000, 583 .input_max = 31000000,
@@ -575,6 +590,9 @@ static struct tegra_clk_pll_params pll_m_params = {
575 .lock_mask = PLL_BASE_LOCK, 590 .lock_mask = PLL_BASE_LOCK,
576 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 591 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
577 .lock_delay = 300, 592 .lock_delay = 300,
593 .div_nmp = &pllm_nmp,
594 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
595 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
578}; 596};
579 597
580static struct tegra_clk_pll_params pll_p_params = { 598static struct tegra_clk_pll_params pll_p_params = {
@@ -1223,7 +1241,7 @@ static void __init tegra30_pmc_clk_init(void)
1223 1241
1224 /* clk_out_2 */ 1242 /* clk_out_2 */
1225 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1243 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1226 ARRAY_SIZE(clk_out1_parents), 0, 1244 ARRAY_SIZE(clk_out2_parents), 0,
1227 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1245 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1228 &clk_out_lock); 1246 &clk_out_lock);
1229 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1247 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1234,7 +1252,7 @@ static void __init tegra30_pmc_clk_init(void)
1234 1252
1235 /* clk_out_3 */ 1253 /* clk_out_3 */
1236 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1254 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1237 ARRAY_SIZE(clk_out1_parents), 0, 1255 ARRAY_SIZE(clk_out3_parents), 0,
1238 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1256 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1239 &clk_out_lock); 1257 &clk_out_lock);
1240 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1258 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1954,7 +1972,7 @@ static const struct of_device_id pmc_match[] __initconst = {
1954 {}, 1972 {},
1955}; 1973};
1956 1974
1957void __init tegra30_clock_init(struct device_node *np) 1975static void __init tegra30_clock_init(struct device_node *np)
1958{ 1976{
1959 struct device_node *node; 1977 struct device_node *node;
1960 int i; 1978 int i;
@@ -2005,3 +2023,4 @@ void __init tegra30_clock_init(struct device_node *np)
2005 2023
2006 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2024 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
2007} 2025}
2026CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);