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path: root/drivers/clk/tegra/clk-tegra114.c
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Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c38
1 files changed, 25 insertions, 13 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 806d80366c54..9467da7dee49 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1566,7 +1566,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1566 1566
1567 /* audio0 */ 1567 /* audio0 */
1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1569 ARRAY_SIZE(mux_audio_sync_clk), 0, 1569 ARRAY_SIZE(mux_audio_sync_clk),
1570 CLK_SET_RATE_NO_REPARENT,
1570 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1571 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1571 NULL); 1572 NULL);
1572 clks[audio0_mux] = clk; 1573 clks[audio0_mux] = clk;
@@ -1578,7 +1579,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1578 1579
1579 /* audio1 */ 1580 /* audio1 */
1580 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1581 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1581 ARRAY_SIZE(mux_audio_sync_clk), 0, 1582 ARRAY_SIZE(mux_audio_sync_clk),
1583 CLK_SET_RATE_NO_REPARENT,
1582 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1584 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1583 NULL); 1585 NULL);
1584 clks[audio1_mux] = clk; 1586 clks[audio1_mux] = clk;
@@ -1590,7 +1592,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1590 1592
1591 /* audio2 */ 1593 /* audio2 */
1592 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1594 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1593 ARRAY_SIZE(mux_audio_sync_clk), 0, 1595 ARRAY_SIZE(mux_audio_sync_clk),
1596 CLK_SET_RATE_NO_REPARENT,
1594 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1597 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1595 NULL); 1598 NULL);
1596 clks[audio2_mux] = clk; 1599 clks[audio2_mux] = clk;
@@ -1602,7 +1605,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1602 1605
1603 /* audio3 */ 1606 /* audio3 */
1604 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1607 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1605 ARRAY_SIZE(mux_audio_sync_clk), 0, 1608 ARRAY_SIZE(mux_audio_sync_clk),
1609 CLK_SET_RATE_NO_REPARENT,
1606 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1610 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1607 NULL); 1611 NULL);
1608 clks[audio3_mux] = clk; 1612 clks[audio3_mux] = clk;
@@ -1614,7 +1618,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1614 1618
1615 /* audio4 */ 1619 /* audio4 */
1616 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1620 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1617 ARRAY_SIZE(mux_audio_sync_clk), 0, 1621 ARRAY_SIZE(mux_audio_sync_clk),
1622 CLK_SET_RATE_NO_REPARENT,
1618 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1623 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1619 NULL); 1624 NULL);
1620 clks[audio4_mux] = clk; 1625 clks[audio4_mux] = clk;
@@ -1626,7 +1631,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1626 1631
1627 /* spdif */ 1632 /* spdif */
1628 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1633 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1629 ARRAY_SIZE(mux_audio_sync_clk), 0, 1634 ARRAY_SIZE(mux_audio_sync_clk),
1635 CLK_SET_RATE_NO_REPARENT,
1630 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1636 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1631 NULL); 1637 NULL);
1632 clks[spdif_mux] = clk; 1638 clks[spdif_mux] = clk;
@@ -1721,7 +1727,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1721 1727
1722 /* clk_out_1 */ 1728 /* clk_out_1 */
1723 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1729 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1724 ARRAY_SIZE(clk_out1_parents), 0, 1730 ARRAY_SIZE(clk_out1_parents),
1731 CLK_SET_RATE_NO_REPARENT,
1725 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1732 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1726 &clk_out_lock); 1733 &clk_out_lock);
1727 clks[clk_out_1_mux] = clk; 1734 clks[clk_out_1_mux] = clk;
@@ -1733,7 +1740,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1733 1740
1734 /* clk_out_2 */ 1741 /* clk_out_2 */
1735 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1742 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1736 ARRAY_SIZE(clk_out2_parents), 0, 1743 ARRAY_SIZE(clk_out2_parents),
1744 CLK_SET_RATE_NO_REPARENT,
1737 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1745 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1738 &clk_out_lock); 1746 &clk_out_lock);
1739 clks[clk_out_2_mux] = clk; 1747 clks[clk_out_2_mux] = clk;
@@ -1745,7 +1753,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1745 1753
1746 /* clk_out_3 */ 1754 /* clk_out_3 */
1747 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1755 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1748 ARRAY_SIZE(clk_out3_parents), 0, 1756 ARRAY_SIZE(clk_out3_parents),
1757 CLK_SET_RATE_NO_REPARENT,
1749 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1758 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1750 &clk_out_lock); 1759 &clk_out_lock);
1751 clks[clk_out_3_mux] = clk; 1760 clks[clk_out_3_mux] = clk;
@@ -2063,7 +2072,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2063 2072
2064 /* dsia */ 2073 /* dsia */
2065 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2074 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2066 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2075 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2076 CLK_SET_RATE_NO_REPARENT,
2067 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2077 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2068 clks[dsia_mux] = clk; 2078 clks[dsia_mux] = clk;
2069 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2079 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -2073,7 +2083,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2073 2083
2074 /* dsib */ 2084 /* dsib */
2075 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2085 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2076 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2086 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2087 CLK_SET_RATE_NO_REPARENT,
2077 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2088 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2078 clks[dsib_mux] = clk; 2089 clks[dsib_mux] = clk;
2079 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2090 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -2110,7 +2121,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2110 2121
2111 /* emc */ 2122 /* emc */
2112 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2123 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2113 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2124 ARRAY_SIZE(mux_pllmcp_clkm),
2125 CLK_SET_RATE_NO_REPARENT,
2114 clk_base + CLK_SOURCE_EMC, 2126 clk_base + CLK_SOURCE_EMC,
2115 29, 3, 0, NULL); 2127 29, 3, 0, NULL);
2116 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2128 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
@@ -2194,7 +2206,7 @@ static const struct of_device_id pmc_match[] __initconst = {
2194 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 2206 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
2195 * breaks 2207 * breaks
2196 */ 2208 */
2197static __initdata struct tegra_clk_init_table init_table[] = { 2209static struct tegra_clk_init_table init_table[] __initdata = {
2198 {uarta, pll_p, 408000000, 0}, 2210 {uarta, pll_p, 408000000, 0},
2199 {uartb, pll_p, 408000000, 0}, 2211 {uartb, pll_p, 408000000, 0},
2200 {uartc, pll_p, 408000000, 0}, 2212 {uartc, pll_p, 408000000, 0},
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-11 17:17:36 -0400