9 files changed, 236 insertions, 52 deletions

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 762fd64dbd1f..6850cba35871 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,4 +6,6 @@ obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 
-obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
+obj-$(CONFIG_MFD_SUN6I_PRCM) += \
+        clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
+        clk-sun8i-apb0.o
diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 633ddc4389ef..5296fd6dd7b3 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -60,7 +60,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
         struct clk_gate *gate;
         const char *clk_name = node->name;
         const char *parents[SUN7I_A20_GMAC_PARENTS];
-        void *reg;
+        void __iomem *reg;
 
         if (of_property_read_string(node, "clock-output-names", &clk_name))
                 return;
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 3806d97e529b..2057c8ac648f 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -62,7 +62,7 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
                 p = FACTOR_GET(config->pshift, config->pwidth, reg);
 
         /* Calculate the rate */
-        rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
+        rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
 
         return rate;
 }
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 02e1a43ebac7..d2d0efa39379 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -15,6 +15,7 @@ struct clk_factors_config {
         u8 mwidth;
         u8 pshift;
         u8 pwidth;
+        u8 n_start;
 };
 
 struct clk_factors {
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 670f90d629d7..e10d0521ec76 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -9,23 +9,53 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 
 #define SUN6I_APB0_GATES_MAX_SIZE       32
 
+struct gates_data {
+        DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
+};
+
+static const struct gates_data sun6i_a31_apb0_gates __initconst = {
+        .mask = {0x7F},
+};
+
+static const struct gates_data sun8i_a23_apb0_gates __initconst = {
+        .mask = {0x5D},
+};
+
+static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
+        { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
+        { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
+        { /* sentinel */ }
+};
+
 static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 {
         struct device_node *np = pdev->dev.of_node;
         struct clk_onecell_data *clk_data;
+        const struct of_device_id *device;
+        const struct gates_data *data;
         const char *clk_parent;
         const char *clk_name;
         struct resource *r;
         void __iomem *reg;
-        int gate_id;
         int ngates;
         int i;
+        int j = 0;
+
+        if (!np)
+                return -ENODEV;
+
+        device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
+        if (!device)
+                return -ENODEV;
+        data = device->data;
 
         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         reg = devm_ioremap_resource(&pdev->dev, r);
@@ -36,54 +66,36 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
         if (!clk_parent)
                 return -EINVAL;
 
-        ngates = of_property_count_strings(np, "clock-output-names");
-        if (ngates < 0)
-                return ngates;
-
-        if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
-                return -EINVAL;
-
         clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
                                 GFP_KERNEL);
         if (!clk_data)
                 return -ENOMEM;
 
-        clk_data->clks = devm_kzalloc(&pdev->dev,
-                                      SUN6I_APB0_GATES_MAX_SIZE *
-                                      sizeof(struct clk *),
-                                      GFP_KERNEL);
+        /* Worst-case size approximation and memory allocation */
+        ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
+        clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
+                                      sizeof(struct clk *), GFP_KERNEL);
         if (!clk_data->clks)
                 return -ENOMEM;
 
-        for (i = 0; i < ngates; i++) {
+        for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
                 of_property_read_string_index(np, "clock-output-names",
-                                              i, &clk_name);
+                                              j, &clk_name);
 
-                gate_id = i;
-                of_property_read_u32_index(np, "clock-indices", i, &gate_id);
+                clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
+                                                      clk_parent, 0, reg, i,
+                                                      0, NULL);
+                WARN_ON(IS_ERR(clk_data->clks[i]));
+                clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
 
-                WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
-                if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
-                        continue;
-
-                clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
-                                                            clk_name,
-                                                            clk_parent, 0,
-                                                            reg, gate_id,
-                                                            0, NULL);
-                WARN_ON(IS_ERR(clk_data->clks[gate_id]));
+                j++;
         }
 
-        clk_data->clk_num = ngates;
+        clk_data->clk_num = ngates + 1;
 
         return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 }
 
-const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
-        { .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
-        { /* sentinel */ }
-};
-
 static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
         .driver = {
                 .name = "sun6i-a31-apb0-gates-clk",
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c
index 11f17c34c2ae..1fa23371c8c6 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0.c
@@ -57,7 +57,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
         return of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
 
-const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
+static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
         { .compatible = "allwinner,sun6i-a31-apb0-clk" },
         { /* sentinel */ }
 };
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index f73cc051f0dd..eca8ca025b6a 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -160,7 +160,7 @@ static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
-struct clk_ops ar100_ops = {
+static struct clk_ops ar100_ops = {
         .recalc_rate = ar100_recalc_rate,
         .determine_rate = ar100_determine_rate,
         .set_parent = ar100_set_parent,
@@ -213,7 +213,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
         return of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
 
-const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
+static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
         { .compatible = "allwinner,sun6i-a31-ar100-clk" },
         { /* sentinel */ }
 };
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
new file mode 100644
index 000000000000..1f5ba9b4b8cd
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Chen-Yu Tsai
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * Allwinner A23 APB0 clock driver
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Based on clk-sun6i-apb0.c
+ * Allwinner A31 APB0 clock driver
+ *
+ * Copyright (C) 2014 Free Electrons
+ * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        const char *clk_name = np->name;
+        const char *clk_parent;
+        struct resource *r;
+        void __iomem *reg;
+        struct clk *clk;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        reg = devm_ioremap_resource(&pdev->dev, r);
+        if (IS_ERR(reg))
+                return PTR_ERR(reg);
+
+        clk_parent = of_clk_get_parent_name(np, 0);
+        if (!clk_parent)
+                return -EINVAL;
+
+        of_property_read_string(np, "clock-output-names", &clk_name);
+
+        /* The A23 APB0 clock is a standard 2 bit wide divider clock */
+        clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
+                                   0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
+
+        return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
+        { .compatible = "allwinner,sun8i-a23-apb0-clk" },
+        { /* sentinel */ }
+};
+
+static struct platform_driver sun8i_a23_apb0_clk_driver = {
+        .driver = {
+                .name = "sun8i-a23-apb0-clk",
+                .owner = THIS_MODULE,
+                .of_match_table = sun8i_a23_apb0_clk_dt_ids,
+        },
+        .probe = sun8i_a23_apb0_clk_probe,
+};
+module_platform_driver(sun8i_a23_apb0_clk_driver);
+
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_DESCRIPTION("Allwinner A23 APB0 clock Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index fb2ce8440f0e..b654b7b1d137 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -164,6 +164,54 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 }
 
 /**
+ * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
+ * PLL1 rate is calculated as follows
+ * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
+ * parent_rate is always 24Mhz
+ */
+
+static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
+                                   u8 *n, u8 *k, u8 *m, u8 *p)
+{
+        u8 div;
+
+        /* Normalize value to a 6M multiple */
+        div = *freq / 6000000;
+        *freq = 6000000 * div;
+
+        /* we were called to round the frequency, we can now return */
+        if (n == NULL)
+                return;
+
+        /* m is always zero for pll1 */
+        *m = 0;
+
+        /* k is 1 only on these cases */
+        if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
+                *k = 1;
+        else
+                *k = 0;
+
+        /* p will be 2 for divs under 20 and odd divs under 32 */
+        if (div < 20 || (div < 32 && (div & 1)))
+                *p = 2;
+
+        /* p will be 1 for even divs under 32, divs under 40 and odd pairs
+         * of divs between 40-62 */
+        else if (div < 40 || (div < 64 && (div & 2)))
+                *p = 1;
+
+        /* any other entries have p = 0 */
+        else
+                *p = 0;
+
+        /* calculate a suitable n based on k and p */
+        div <<= *p;
+        div /= (*k + 1);
+        *n = div / 4 - 1;
+}
+
+/**
  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
  * PLL5 rate is calculated as follows
  * rate = parent_rate * n * (k + 1)
@@ -422,6 +470,18 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
         .mwidth = 2,
 };
 
+static struct clk_factors_config sun8i_a23_pll1_config = {
+        .nshift = 8,
+        .nwidth = 5,
+        .kshift = 4,
+        .kwidth = 2,
+        .mshift = 0,
+        .mwidth = 2,
+        .pshift = 16,
+        .pwidth = 2,
+        .n_start = 1,
+};
+
 static struct clk_factors_config sun4i_pll5_config = {
         .nshift = 8,
         .nwidth = 5,
@@ -471,6 +531,12 @@ static const struct factors_data sun6i_a31_pll1_data __initconst = {
         .getter = sun6i_a31_get_pll1_factors,
 };
 
+static const struct factors_data sun8i_a23_pll1_data __initconst = {
+        .enable = 31,
+        .table = &sun8i_a23_pll1_config,
+        .getter = sun8i_a23_get_pll1_factors,
+};
+
 static const struct factors_data sun7i_a20_pll4_data __initconst = {
         .enable = 31,
         .table = &sun4i_pll5_config,
@@ -527,7 +593,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
         struct clk_hw *mux_hw = NULL;
         const char *clk_name = node->name;
         const char *parents[SUNXI_MAX_PARENTS];
-        void *reg;
+        void __iomem *reg;
         int i = 0;
 
         reg = of_iomap(node, 0);
@@ -632,7 +698,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
         struct clk *clk;
         const char *clk_name = node->name;
         const char *parents[SUNXI_MAX_PARENTS];
-        void *reg;
+        void __iomem *reg;
         int i = 0;
 
         reg = of_iomap(node, 0);
@@ -664,6 +730,7 @@ struct div_data {
         u8      shift;
         u8      pow;
         u8      width;
+        const struct clk_div_table *table;
 };
 
 static const struct div_data sun4i_axi_data __initconst = {
@@ -672,6 +739,23 @@ static const struct div_data sun4i_axi_data __initconst = {
         .width  = 2,
 };
 
+static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 3 },
+        { .val = 3, .div = 4 },
+        { .val = 4, .div = 4 },
+        { .val = 5, .div = 4 },
+        { .val = 6, .div = 4 },
+        { .val = 7, .div = 4 },
+        { } /* sentinel */
+};
+
+static const struct div_data sun8i_a23_axi_data __initconst = {
+        .width  = 3,
+        .table  = sun8i_a23_axi_table,
+};
+
 static const struct div_data sun4i_ahb_data __initconst = {
         .shift  = 4,
         .pow    = 1,
@@ -696,7 +780,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
         struct clk *clk;
         const char *clk_name = node->name;
         const char *clk_parent;
-        void *reg;
+        void __iomem *reg;
 
         reg = of_iomap(node, 0);
 
@@ -704,10 +788,10 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
 
         of_property_read_string(node, "clock-output-names", &clk_name);
 
-        clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
-                                   reg, data->shift, data->width,
-                                   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
-                                   &clk_lock);
+        clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
+                                         reg, data->shift, data->width,
+                                         data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
+                                         data->table, &clk_lock);
         if (clk) {
                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
                 clk_register_clkdev(clk, clk_name, NULL);
@@ -804,6 +888,10 @@ static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
         .mask = { 0x12f77fff, 0x16ff3f },
 };
 
+static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
+        .mask = {0x25386742, 0x2505111},
+};
+
 static const struct gates_data sun4i_apb0_gates_data __initconst = {
         .mask = {0x4EF},
 };
@@ -836,6 +924,10 @@ static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
         .mask = {0x3031},
 };
 
+static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
+        .mask = {0x3021},
+};
+
 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
         .mask = {0x3F000F},
 };
@@ -844,6 +936,10 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
         .mask = { 0xff80ff },
 };
 
+static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
+        .mask = {0x1F0007},
+};
+
 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
         .mask = {0x1C0},
         .reset_mask = 0x07,
@@ -866,11 +962,10 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
         struct gates_reset_data *reset_data;
         const char *clk_parent;
         const char *clk_name;
-        void *reg;
+        void __iomem *reg;
         int qty;
         int i = 0;
         int j = 0;
-        int ignore;
 
         reg = of_iomap(node, 0);
 
@@ -891,14 +986,12 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
                 of_property_read_string_index(node, "clock-output-names",
                                               j, &clk_name);
 
-                /* No driver claims this clock, but it should remain gated */
-                ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
-
                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
-                                                      clk_parent, ignore,
+                                                      clk_parent, 0,
                                                       reg + 4 * (i/32), i % 32,
                                                       0, &clk_lock);
                 WARN_ON(IS_ERR(clk_data->clks[i]));
+                clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
 
                 j++;
         }
@@ -991,7 +1084,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
         struct clk_gate *gate = NULL;
         struct clk_fixed_factor *fix_factor;
         struct clk_divider *divider;
-        void *reg;
+        void __iomem *reg;
         int i = 0;
         int flags, clkflags;
 
@@ -1102,6 +1195,7 @@ free_clkdata:
 static const struct of_device_id clk_factors_match[] __initconst = {
         {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+        {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
@@ -1113,6 +1207,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
 /* Matches for divider clocks */
 static const struct of_device_id clk_div_match[] __initconst = {
         {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
+        {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
         {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
@@ -1142,6 +1237,7 @@ static const struct of_device_id clk_gates_match[] __initconst = {
         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
+        {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
@@ -1151,7 +1247,9 @@ static const struct of_device_id clk_gates_match[] __initconst = {
         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
+        {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
+        {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
         {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
         {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
         {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
@@ -1202,6 +1300,7 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
 
 static const char *sun4i_a10_critical_clocks[] __initdata = {
         "pll5_ddr",
+        "ahb_sdram",
 };
 
 static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1214,6 +1313,7 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
 static const char *sun5i_critical_clocks[] __initdata = {
         "mbus",
         "pll5_ddr",
+        "ahb_sdram",
 };
 
 static void __init sun5i_init_clocks(struct device_node *node)
@@ -1236,3 +1336,4 @@ static void __init sun6i_init_clocks(struct device_node *node)
                           ARRAY_SIZE(sun6i_critical_clocks));
 }
 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
+CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);