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path: root/drivers/clk/spear/spear3xx_clock.c
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Diffstat (limited to 'drivers/clk/spear/spear3xx_clock.c')
-rw-r--r--drivers/clk/spear/spear3xx_clock.c119
1 files changed, 67 insertions, 52 deletions
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 417f93734612..4c89b143e246 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -278,23 +278,26 @@ static void __init spear320_clk_init(void)
278 clk_register_clkdev(clk, NULL, "a9400000.i2s"); 278 clk_register_clkdev(clk, NULL, "a9400000.i2s");
279 279
280 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, 280 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
281 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG, 281 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
282 I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock); 282 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
283 I2S_REF_PCLK_MASK, 0, &_lock);
283 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 284 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
284 285
285 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1, 286 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
287 CLK_SET_RATE_PARENT, 1,
286 4); 288 4);
287 clk_register_clkdev(clk, "i2s_sclk", NULL); 289 clk_register_clkdev(clk, "i2s_sclk", NULL);
288 290
289 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, 291 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
290 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 292 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
291 SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 293 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
292 &_lock); 294 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
293 clk_register_clkdev(clk, NULL, "a9300000.serial"); 295 clk_register_clkdev(clk, NULL, "a9300000.serial");
294 296
295 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, 297 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
296 ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG, 298 ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
297 SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock); 299 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
300 0, &_lock);
298 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 301 clk_register_clkdev(clk, NULL, "70000000.sdhci");
299 302
300 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, 303 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
@@ -306,38 +309,39 @@ static void __init spear320_clk_init(void)
306 clk_register_clkdev(clk, NULL, "smii"); 309 clk_register_clkdev(clk, NULL, "smii");
307 310
308 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, 311 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
309 ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG, 312 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
310 UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock); 313 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
314 0, &_lock);
311 clk_register_clkdev(clk, NULL, "a3000000.serial"); 315 clk_register_clkdev(clk, NULL, "a3000000.serial");
312 316
313 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 317 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
314 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 318 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
315 SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 319 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
316 &_lock); 320 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
317 clk_register_clkdev(clk, NULL, "a4000000.serial"); 321 clk_register_clkdev(clk, NULL, "a4000000.serial");
318 322
319 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 323 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
320 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 324 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
321 SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 325 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
322 &_lock); 326 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
323 clk_register_clkdev(clk, NULL, "a9100000.serial"); 327 clk_register_clkdev(clk, NULL, "a9100000.serial");
324 328
325 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, 329 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
326 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 330 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
327 SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 331 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
328 &_lock); 332 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
329 clk_register_clkdev(clk, NULL, "a9200000.serial"); 333 clk_register_clkdev(clk, NULL, "a9200000.serial");
330 334
331 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, 335 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
332 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 336 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
333 SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 337 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
334 &_lock); 338 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
335 clk_register_clkdev(clk, NULL, "60000000.serial"); 339 clk_register_clkdev(clk, NULL, "60000000.serial");
336 340
337 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, 341 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
338 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 342 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
339 SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 343 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
340 &_lock); 344 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
341 clk_register_clkdev(clk, NULL, "60100000.serial"); 345 clk_register_clkdev(clk, NULL, "60100000.serial");
342} 346}
343#else 347#else
@@ -386,7 +390,8 @@ void __init spear3xx_clk_init(void)
386 clk_register_clkdev(clk1, "pll2_clk", NULL); 390 clk_register_clkdev(clk1, "pll2_clk", NULL);
387 391
388 /* clock derived from pll1 clk */ 392 /* clock derived from pll1 clk */
389 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); 393 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
394 CLK_SET_RATE_PARENT, 1, 1);
390 clk_register_clkdev(clk, "cpu_clk", NULL); 395 clk_register_clkdev(clk, "cpu_clk", NULL);
391 396
392 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 397 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
@@ -401,12 +406,14 @@ void __init spear3xx_clk_init(void)
401 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 406 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
402 407
403 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 408 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
404 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, 409 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
405 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 410 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
411 &_lock);
406 clk_register_clkdev(clk, "uart0_mclk", NULL); 412 clk_register_clkdev(clk, "uart0_mclk", NULL);
407 413
408 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB, 414 clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
409 UART_CLK_ENB, 0, &_lock); 415 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
416 &_lock);
410 clk_register_clkdev(clk, NULL, "d0000000.serial"); 417 clk_register_clkdev(clk, NULL, "d0000000.serial");
411 418
412 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, 419 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
@@ -416,40 +423,44 @@ void __init spear3xx_clk_init(void)
416 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 423 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
417 424
418 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 425 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
419 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 426 ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
420 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 427 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
428 &_lock);
421 clk_register_clkdev(clk, "firda_mclk", NULL); 429 clk_register_clkdev(clk, "firda_mclk", NULL);
422 430
423 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 431 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
424 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 432 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
433 &_lock);
425 clk_register_clkdev(clk, NULL, "firda"); 434 clk_register_clkdev(clk, NULL, "firda");
426 435
427 /* gpt clocks */ 436 /* gpt clocks */
428 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, 437 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
429 ARRAY_SIZE(gpt_rtbl), &_lock); 438 ARRAY_SIZE(gpt_rtbl), &_lock);
430 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 439 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
431 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, 440 ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
432 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 441 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
433 clk_register_clkdev(clk, NULL, "gpt0"); 442 clk_register_clkdev(clk, NULL, "gpt0");
434 443
435 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, 444 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
436 ARRAY_SIZE(gpt_rtbl), &_lock); 445 ARRAY_SIZE(gpt_rtbl), &_lock);
437 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, 446 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
438 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, 447 ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
439 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 448 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
440 clk_register_clkdev(clk, "gpt1_mclk", NULL); 449 clk_register_clkdev(clk, "gpt1_mclk", NULL);
441 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 450 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
442 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 451 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
452 &_lock);
443 clk_register_clkdev(clk, NULL, "gpt1"); 453 clk_register_clkdev(clk, NULL, "gpt1");
444 454
445 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, 455 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
446 ARRAY_SIZE(gpt_rtbl), &_lock); 456 ARRAY_SIZE(gpt_rtbl), &_lock);
447 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 457 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
448 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 458 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
449 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 459 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
450 clk_register_clkdev(clk, "gpt2_mclk", NULL); 460 clk_register_clkdev(clk, "gpt2_mclk", NULL);
451 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 461 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
452 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 462 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
463 &_lock);
453 clk_register_clkdev(clk, NULL, "gpt2"); 464 clk_register_clkdev(clk, NULL, "gpt2");
454 465
455 /* general synths clocks */ 466 /* general synths clocks */
@@ -587,20 +598,24 @@ void __init spear3xx_clk_init(void)
587 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); 598 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
588 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 599 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
589 600
590 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0, 601 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
591 RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); 602 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
603 &_lock);
592 clk_register_clkdev(clk, "ras_syn0_gclk", NULL); 604 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
593 605
594 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0, 606 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
595 RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); 607 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
608 &_lock);
596 clk_register_clkdev(clk, "ras_syn1_gclk", NULL); 609 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
597 610
598 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0, 611 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
599 RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); 612 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
613 &_lock);
600 clk_register_clkdev(clk, "ras_syn2_gclk", NULL); 614 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
601 615
602 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0, 616 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
603 RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); 617 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
618 &_lock);
604 clk_register_clkdev(clk, "ras_syn3_gclk", NULL); 619 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
605 620
606 if (of_machine_is_compatible("st,spear300")) 621 if (of_machine_is_compatible("st,spear300"))