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path: root/drivers/clk/spear/spear1340_clock.c
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-rw-r--r--drivers/clk/spear/spear1340_clock.c964
1 files changed, 964 insertions, 0 deletions
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
new file mode 100644
index 000000000000..f130919d5bf8
--- /dev/null
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -0,0 +1,964 @@
1/*
2 * arch/arm/mach-spear13xx/spear1340_clock.c
3 *
4 * SPEAr1340 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of_platform.h>
19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
21#include "clk.h"
22
23/* Clock Configuration Registers */
24#define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29
30/* PLL related registers and bit values */
31#define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
32 /* PLL_CFG bit values */
33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38 #define SPEAR1340_PLL_CLK_MASK 2
39 #define SPEAR1340_PLL3_CLK_SHIFT 24
40 #define SPEAR1340_PLL2_CLK_SHIFT 22
41 #define SPEAR1340_PLL1_CLK_SHIFT 20
42
43#define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44#define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45#define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46#define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47#define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48#define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49#define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50#define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51#define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
52 /* PERIP_CLK_CFG bit values */
53 #define SPEAR1340_SPDIF_CLK_MASK 1
54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56 #define SPEAR1340_GPT3_CLK_SHIFT 13
57 #define SPEAR1340_GPT2_CLK_SHIFT 12
58 #define SPEAR1340_GPT_CLK_MASK 1
59 #define SPEAR1340_GPT1_CLK_SHIFT 9
60 #define SPEAR1340_GPT0_CLK_SHIFT 8
61 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_UART1_CLK_SHIFT 6
63 #define SPEAR1340_UART0_CLK_SHIFT 4
64 #define SPEAR1340_CLCD_CLK_MASK 2
65 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_C3_CLK_MASK 1
67 #define SPEAR1340_C3_CLK_SHIFT 1
68
69#define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74
75#define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76 /* I2S_CLK_CFG register mask */
77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88 #define SPEAR1340_I2S_REF_SEL_MASK 1
89 #define SPEAR1340_I2S_REF_SHIFT 2
90 #define SPEAR1340_I2S_SRC_CLK_MASK 2
91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92
93#define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94#define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95#define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96#define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97#define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98#define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99#define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100#define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101#define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102#define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103#define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104#define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105#define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106#define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107#define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
108 #define SPEAR1340_RTC_CLK_ENB 31
109 #define SPEAR1340_ADC_CLK_ENB 30
110 #define SPEAR1340_C3_CLK_ENB 29
111 #define SPEAR1340_CLCD_CLK_ENB 27
112 #define SPEAR1340_DMA_CLK_ENB 25
113 #define SPEAR1340_GPIO1_CLK_ENB 24
114 #define SPEAR1340_GPIO0_CLK_ENB 23
115 #define SPEAR1340_GPT1_CLK_ENB 22
116 #define SPEAR1340_GPT0_CLK_ENB 21
117 #define SPEAR1340_I2S_PLAY_CLK_ENB 20
118 #define SPEAR1340_I2S_REC_CLK_ENB 19
119 #define SPEAR1340_I2C0_CLK_ENB 18
120 #define SPEAR1340_SSP_CLK_ENB 17
121 #define SPEAR1340_UART0_CLK_ENB 15
122 #define SPEAR1340_PCIE_SATA_CLK_ENB 12
123 #define SPEAR1340_UOC_CLK_ENB 11
124 #define SPEAR1340_UHC1_CLK_ENB 10
125 #define SPEAR1340_UHC0_CLK_ENB 9
126 #define SPEAR1340_GMAC_CLK_ENB 8
127 #define SPEAR1340_CFXD_CLK_ENB 7
128 #define SPEAR1340_SDHCI_CLK_ENB 6
129 #define SPEAR1340_SMI_CLK_ENB 5
130 #define SPEAR1340_FSMC_CLK_ENB 4
131 #define SPEAR1340_SYSRAM0_CLK_ENB 3
132 #define SPEAR1340_SYSRAM1_CLK_ENB 2
133 #define SPEAR1340_SYSROM_CLK_ENB 1
134 #define SPEAR1340_BUS_CLK_ENB 0
135
136#define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
137 #define SPEAR1340_THSENS_CLK_ENB 8
138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139 #define SPEAR1340_ACP_CLK_ENB 6
140 #define SPEAR1340_GPT3_CLK_ENB 5
141 #define SPEAR1340_GPT2_CLK_ENB 4
142 #define SPEAR1340_KBD_CLK_ENB 3
143 #define SPEAR1340_CPU_DBG_CLK_ENB 2
144 #define SPEAR1340_DDR_CORE_CLK_ENB 1
145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146
147#define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
148 #define SPEAR1340_PLGPIO_CLK_ENB 18
149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154 #define SPEAR1340_CAM0_CLK_ENB 10
155 #define SPEAR1340_CAM1_CLK_ENB 9
156 #define SPEAR1340_CAM2_CLK_ENB 8
157 #define SPEAR1340_CAM3_CLK_ENB 7
158 #define SPEAR1340_MALI_CLK_ENB 6
159 #define SPEAR1340_CEC0_CLK_ENB 5
160 #define SPEAR1340_CEC1_CLK_ENB 4
161 #define SPEAR1340_PWM_CLK_ENB 3
162 #define SPEAR1340_I2C1_CLK_ENB 2
163 #define SPEAR1340_UART1_CLK_ENB 1
164
165static DEFINE_SPINLOCK(_lock);
166
167/* pll rate configuration table, in ascending order of rates */
168static struct pll_rate_tbl pll_rtbl[] = {
169 /* PCLK 24MHz */
170 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
172 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
173 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
174 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
175 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
177 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178};
179
180/* vco-pll4 rate configuration table, in ascending order of rates */
181static struct pll_rate_tbl pll4_rtbl[] = {
182 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
183 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
184 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
186};
187
188/*
189 * All below entries generate 166 MHz for
190 * different values of vco1div2
191 */
192static struct frac_rate_tbl amba_synth_rtbl[] = {
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198};
199
200/*
201 * Synthesizer Clock derived from vcodiv2. This clock is one of the
202 * possible clocks to feed cpu directly.
203 * We can program this synthesizer to make cpu run on different clock
204 * frequencies.
205 * Following table provides configuration values to let cpu run on 200,
206 * 250, 332, 400 or 500 MHz considering different possibilites of input
207 * (vco1div2) clock.
208 *
209 * --------------------------------------------------------------------
210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211 * --------------------------------------------------------------------
212 * 400 200 100 0x04000
213 * 400 250 125 0x03333
214 * 400 332 166 0x0268D
215 * 400 400 200 0x02000
216 * --------------------------------------------------------------------
217 * 500 200 100 0x05000
218 * 500 250 125 0x04000
219 * 500 332 166 0x03031
220 * 500 400 200 0x02800
221 * 500 500 250 0x02000
222 * --------------------------------------------------------------------
223 * 664 200 100 0x06a38
224 * 664 250 125 0x054FD
225 * 664 332 166 0x04000
226 * 664 400 200 0x0351E
227 * 664 500 250 0x02A7E
228 * --------------------------------------------------------------------
229 * 800 200 100 0x08000
230 * 800 250 125 0x06666
231 * 800 332 166 0x04D18
232 * 800 400 200 0x04000
233 * 800 500 250 0x03333
234 * --------------------------------------------------------------------
235 * sys rate configuration table is in descending order of divisor.
236 */
237static struct frac_rate_tbl sys_synth_rtbl[] = {
238 {.div = 0x08000},
239 {.div = 0x06a38},
240 {.div = 0x06666},
241 {.div = 0x054FD},
242 {.div = 0x05000},
243 {.div = 0x04D18},
244 {.div = 0x04000},
245 {.div = 0x0351E},
246 {.div = 0x03333},
247 {.div = 0x03031},
248 {.div = 0x02A7E},
249 {.div = 0x02800},
250 {.div = 0x0268D},
251 {.div = 0x02000},
252};
253
254/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263};
264
265/* gmac rate configuration table, in ascending order of rates */
266static struct aux_rate_tbl gmac_rtbl[] = {
267 /* For gmac phy input clk */
268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272};
273
274/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = {
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
289};
290
291/* i2s prescaler1 masks */
292static struct aux_clk_masks i2s_prs1_masks = {
293 .eq_sel_mask = AUX_EQ_SEL_MASK,
294 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
295 .eq1_mask = AUX_EQ1_SEL,
296 .eq2_mask = AUX_EQ2_SEL,
297 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
298 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
299 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
300 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
301};
302
303/* i2s sclk (bit clock) syynthesizers masks */
304static struct aux_clk_masks i2s_sclk_masks = {
305 .eq_sel_mask = AUX_EQ_SEL_MASK,
306 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
307 .eq1_mask = AUX_EQ1_SEL,
308 .eq2_mask = AUX_EQ2_SEL,
309 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
310 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
311 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
312 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
313 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
314};
315
316/* i2s prs1 aux rate configuration table, in ascending order of rates */
317static struct aux_rate_tbl i2s_prs1_rtbl[] = {
318 /* For parent clk = 49.152 MHz */
319 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
320 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
321 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
322 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
323
324 /*
325 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
326 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
327 */
328 {.xscale = 1, .yscale = 3, .eq = 0},
329
330 /* For parent clk = 49.152 MHz */
331 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
333};
334
335/* i2s sclk aux rate configuration table, in ascending order of rates */
336static struct aux_rate_tbl i2s_sclk_rtbl[] = {
337 /* For sclk = ref_clk * x/2/y */
338 {.xscale = 1, .yscale = 4, .eq = 0},
339 {.xscale = 1, .yscale = 2, .eq = 0},
340};
341
342/* adc rate configuration table, in ascending order of rates */
343/* possible adc range is 2.5 MHz to 20 MHz. */
344static struct aux_rate_tbl adc_rtbl[] = {
345 /* For ahb = 166.67 MHz */
346 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
347 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
348 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
349 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350};
351
352/* General synth rate configuration table, in ascending order of rates */
353static struct frac_rate_tbl gen_rtbl[] = {
354 /* For vco1div4 = 250 MHz */
355 {.div = 0x1624E}, /* 22.5792 MHz */
356 {.div = 0x14585}, /* 24.576 MHz */
357 {.div = 0x14000}, /* 25 MHz */
358 {.div = 0x0B127}, /* 45.1584 MHz */
359 {.div = 0x0A000}, /* 50 MHz */
360 {.div = 0x061A8}, /* 81.92 MHz */
361 {.div = 0x05000}, /* 100 MHz */
362 {.div = 0x02800}, /* 200 MHz */
363 {.div = 0x02620}, /* 210 MHz */
364 {.div = 0x02460}, /* 220 MHz */
365 {.div = 0x022C0}, /* 230 MHz */
366 {.div = 0x02160}, /* 240 MHz */
367 {.div = 0x02000}, /* 250 MHz */
368};
369
370/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "none", "pll1_clk", "none", "none",
373 "sys_synth_clk", "none", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_synth_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377 "uart0_synth_gate_clk", };
378static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379 "uart1_synth_gate_clk", };
380static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
381static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
382 "osc_25m_clk", };
383static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
384 "gmac_phy_synth_gate_clk", };
385static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
386static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
387static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
388 "i2s_src_pad_clk", };
389static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
390static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_synth2_clk",
391};
392static const char *spdif_in_parents[] = { "pll2_clk", "gen_synth3_clk", };
393
394static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
395 "pll3_clk", };
396static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
397 "pll2_clk", };
398
399void __init spear1340_clk_init(void)
400{
401 struct clk *clk, *clk1;
402
403 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
404 clk_register_clkdev(clk, "apb_pclk", NULL);
405
406 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
407 32000);
408 clk_register_clkdev(clk, "osc_32k_clk", NULL);
409
410 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
411 24000000);
412 clk_register_clkdev(clk, "osc_24m_clk", NULL);
413
414 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
415 25000000);
416 clk_register_clkdev(clk, "osc_25m_clk", NULL);
417
418 clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
419 CLK_IS_ROOT, 125000000);
420 clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
421
422 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
423 CLK_IS_ROOT, 12288000);
424 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
425
426 /* clock derived from 32 KHz osc clk */
427 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
428 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
429 &_lock);
430 clk_register_clkdev(clk, NULL, "fc900000.rtc");
431
432 /* clock derived from 24 or 25 MHz osc clk */
433 /* vco-pll */
434 clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
435 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
436 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
437 &_lock);
438 clk_register_clkdev(clk, "vco1_mux_clk", NULL);
439 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
440 0, SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
441 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
442 clk_register_clkdev(clk, "vco1_clk", NULL);
443 clk_register_clkdev(clk1, "pll1_clk", NULL);
444
445 clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
446 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
447 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
448 &_lock);
449 clk_register_clkdev(clk, "vco2_mux_clk", NULL);
450 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
451 0, SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
452 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
453 clk_register_clkdev(clk, "vco2_clk", NULL);
454 clk_register_clkdev(clk1, "pll2_clk", NULL);
455
456 clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
457 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
458 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
459 &_lock);
460 clk_register_clkdev(clk, "vco3_mux_clk", NULL);
461 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
462 0, SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
463 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
464 clk_register_clkdev(clk, "vco3_clk", NULL);
465 clk_register_clkdev(clk1, "pll3_clk", NULL);
466
467 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
468 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
469 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
470 clk_register_clkdev(clk, "vco4_clk", NULL);
471 clk_register_clkdev(clk1, "pll4_clk", NULL);
472
473 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
474 48000000);
475 clk_register_clkdev(clk, "pll5_clk", NULL);
476
477 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
478 25000000);
479 clk_register_clkdev(clk, "pll6_clk", NULL);
480
481 /* vco div n clocks */
482 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
483 2);
484 clk_register_clkdev(clk, "vco1div2_clk", NULL);
485
486 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
487 4);
488 clk_register_clkdev(clk, "vco1div4_clk", NULL);
489
490 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
491 2);
492 clk_register_clkdev(clk, "vco2div2_clk", NULL);
493
494 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
495 2);
496 clk_register_clkdev(clk, "vco3div2_clk", NULL);
497
498 /* peripherals */
499 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
500 128);
501 clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
502 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
503 &_lock);
504 clk_register_clkdev(clk, NULL, "spear_thermal");
505
506 /* clock derived from pll4 clk */
507 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
508 1);
509 clk_register_clkdev(clk, "ddr_clk", NULL);
510
511 /* clock derived from pll1 clk */
512 clk = clk_register_frac("sys_synth_clk", "vco1div2_clk", 0,
513 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
514 ARRAY_SIZE(sys_synth_rtbl), &_lock);
515 clk_register_clkdev(clk, "sys_synth_clk", NULL);
516
517 clk = clk_register_frac("amba_synth_clk", "vco1div2_clk", 0,
518 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
519 ARRAY_SIZE(amba_synth_rtbl), &_lock);
520 clk_register_clkdev(clk, "amba_synth_clk", NULL);
521
522 clk = clk_register_mux(NULL, "sys_mux_clk", sys_parents,
523 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
524 SPEAR1340_SCLK_SRC_SEL_SHIFT,
525 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
526 clk_register_clkdev(clk, "sys_clk", NULL);
527
528 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mux_clk", 0, 1,
529 2);
530 clk_register_clkdev(clk, "cpu_clk", NULL);
531
532 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
533 3);
534 clk_register_clkdev(clk, "cpu_div3_clk", NULL);
535
536 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
537 2);
538 clk_register_clkdev(clk, NULL, "ec800620.wdt");
539
540 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
541 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
542 SPEAR1340_HCLK_SRC_SEL_SHIFT,
543 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
544 clk_register_clkdev(clk, "ahb_clk", NULL);
545
546 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
547 2);
548 clk_register_clkdev(clk, "apb_clk", NULL);
549
550 /* gpt clocks */
551 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
552 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
553 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
554 &_lock);
555 clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
556 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
557 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
558 &_lock);
559 clk_register_clkdev(clk, NULL, "gpt0");
560
561 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
562 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
563 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
564 &_lock);
565 clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
566 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
567 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
568 &_lock);
569 clk_register_clkdev(clk, NULL, "gpt1");
570
571 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
572 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
573 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
574 &_lock);
575 clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
576 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
577 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
578 &_lock);
579 clk_register_clkdev(clk, NULL, "gpt2");
580
581 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
582 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
583 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
584 &_lock);
585 clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
586 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
587 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
588 &_lock);
589 clk_register_clkdev(clk, NULL, "gpt3");
590
591 /* others */
592 clk = clk_register_aux("uart0_synth_clk", "uart0_synth_gate_clk",
593 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
594 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
595 clk_register_clkdev(clk, "uart0_synth_clk", NULL);
596 clk_register_clkdev(clk1, "uart0_synth_gate_clk", NULL);
597
598 clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
599 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
600 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
601 &_lock);
602 clk_register_clkdev(clk, "uart0_mux_clk", NULL);
603
604 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
606 &_lock);
607 clk_register_clkdev(clk, NULL, "e0000000.serial");
608
609 clk = clk_register_aux("uart1_synth_clk", "uart1_synth_gate_clk",
610 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
611 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
612 clk_register_clkdev(clk, "uart1_synth_clk", NULL);
613 clk_register_clkdev(clk1, "uart1_synth_gate_clk", NULL);
614
615 clk = clk_register_mux(NULL, "uart1_mux_clk", uart1_parents,
616 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
617 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
618 &_lock);
619 clk_register_clkdev(clk, "uart1_mux_clk", NULL);
620
621 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
622 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
623 &_lock);
624 clk_register_clkdev(clk, NULL, "b4100000.serial");
625
626 clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
627 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
628 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
629 clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
630 clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
631
632 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
633 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
634 &_lock);
635 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
636
637 clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
638 "vco1div2_clk", 0, SPEAR1340_CFXD_CLK_SYNT, NULL,
639 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
640 clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
641 clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
642
643 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
644 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
645 &_lock);
646 clk_register_clkdev(clk, NULL, "b2800000.cf");
647 clk_register_clkdev(clk, NULL, "arasan_xd");
648
649 clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
650 "vco1div2_clk", 0, SPEAR1340_C3_CLK_SYNT, NULL,
651 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
652 clk_register_clkdev(clk, "c3_synth_clk", NULL);
653 clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
654
655 clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
656 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
657 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
658 &_lock);
659 clk_register_clkdev(clk, "c3_mux_clk", NULL);
660
661 clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
662 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
663 &_lock);
664 clk_register_clkdev(clk, NULL, "c3");
665
666 /* gmac */
667 clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
668 gmac_phy_input_parents,
669 ARRAY_SIZE(gmac_phy_input_parents), 0,
670 SPEAR1340_GMAC_CLK_CFG,
671 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
672 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
673 clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
674
675 clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
676 "gmac_phy_input_mux_clk", 0, SPEAR1340_GMAC_CLK_SYNT,
677 NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
678 clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
679 clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
680
681 clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
682 ARRAY_SIZE(gmac_phy_parents), 0,
683 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
684 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
685 clk_register_clkdev(clk, NULL, "stmmacphy.0");
686
687 /* clcd */
688 clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
689 ARRAY_SIZE(clcd_synth_parents), 0,
690 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
691 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
692 clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
693
694 clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
695 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
696 ARRAY_SIZE(clcd_rtbl), &_lock);
697 clk_register_clkdev(clk, "clcd_synth_clk", NULL);
698
699 clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
700 ARRAY_SIZE(clcd_pixel_parents), 0,
701 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
702 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
703 clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
704
705 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
706 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
707 &_lock);
708 clk_register_clkdev(clk, "clcd_clk", NULL);
709
710 /* i2s */
711 clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
712 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
713 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
714 0, &_lock);
715 clk_register_clkdev(clk, "i2s_src_clk", NULL);
716
717 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
718 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
719 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
720 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
721
722 clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
723 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
724 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
725 &_lock);
726 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
727
728 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
729 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
730 0, &_lock);
731 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
732
733 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
734 "i2s_ref_mux_clk", 0, SPEAR1340_I2S_CLK_CFG,
735 &i2s_sclk_masks, i2s_sclk_rtbl,
736 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
737 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
738 clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
739
740 /* clock derived from ahb clk */
741 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
742 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
743 &_lock);
744 clk_register_clkdev(clk, NULL, "e0280000.i2c");
745
746 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
748 &_lock);
749 clk_register_clkdev(clk, NULL, "b4000000.i2c");
750
751 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
752 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
753 &_lock);
754 clk_register_clkdev(clk, NULL, "ea800000.dma");
755 clk_register_clkdev(clk, NULL, "eb000000.dma");
756
757 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
758 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
759 &_lock);
760 clk_register_clkdev(clk, NULL, "e2000000.eth");
761
762 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
763 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
764 &_lock);
765 clk_register_clkdev(clk, NULL, "b0000000.flash");
766
767 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
768 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
769 &_lock);
770 clk_register_clkdev(clk, NULL, "ea000000.flash");
771
772 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
773 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
774 &_lock);
775 clk_register_clkdev(clk, "usbh.0_clk", NULL);
776
777 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
778 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
779 &_lock);
780 clk_register_clkdev(clk, "usbh.1_clk", NULL);
781
782 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
783 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
784 &_lock);
785 clk_register_clkdev(clk, NULL, "uoc");
786
787 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
788 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
789 0, &_lock);
790 clk_register_clkdev(clk, NULL, "dw_pcie");
791 clk_register_clkdev(clk, NULL, "ahci");
792
793 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
794 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
795 &_lock);
796 clk_register_clkdev(clk, "sysram0_clk", NULL);
797
798 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
799 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
800 &_lock);
801 clk_register_clkdev(clk, "sysram1_clk", NULL);
802
803 clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
804 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
805 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
806 clk_register_clkdev(clk, "adc_synth_clk", NULL);
807 clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
808
809 clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
810 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
811 &_lock);
812 clk_register_clkdev(clk, NULL, "adc_clk");
813
814 /* clock derived from apb clk */
815 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
817 &_lock);
818 clk_register_clkdev(clk, NULL, "e0100000.spi");
819
820 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
821 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
822 &_lock);
823 clk_register_clkdev(clk, NULL, "e0600000.gpio");
824
825 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
826 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
827 &_lock);
828 clk_register_clkdev(clk, NULL, "e0680000.gpio");
829
830 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
832 &_lock);
833 clk_register_clkdev(clk, NULL, "b2400000.i2s");
834
835 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
837 &_lock);
838 clk_register_clkdev(clk, NULL, "b2000000.i2s");
839
840 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
841 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
842 &_lock);
843 clk_register_clkdev(clk, NULL, "e0300000.kbd");
844
845 /* RAS clks */
846 clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
847 gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
848 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
849 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
850 clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
851
852 clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
853 gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
854 0, SPEAR1340_PLL_CFG, SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
855 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
856 clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
857
858 clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
859 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
860 &_lock);
861 clk_register_clkdev(clk, "gen_synth0_clk", NULL);
862
863 clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
864 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
865 &_lock);
866 clk_register_clkdev(clk, "gen_synth1_clk", NULL);
867
868 clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
869 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
870 &_lock);
871 clk_register_clkdev(clk, "gen_synth2_clk", NULL);
872
873 clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
874 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
875 &_lock);
876 clk_register_clkdev(clk, "gen_synth3_clk", NULL);
877
878 clk = clk_register_gate(NULL, "mali_clk", "gen_synth3_clk", 0,
879 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
880 &_lock);
881 clk_register_clkdev(clk, NULL, "mali");
882
883 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
884 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
885 &_lock);
886 clk_register_clkdev(clk, NULL, "spear_cec.0");
887
888 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
889 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
890 &_lock);
891 clk_register_clkdev(clk, NULL, "spear_cec.1");
892
893 clk = clk_register_mux(NULL, "spdif_out_mux_clk", spdif_out_parents,
894 ARRAY_SIZE(spdif_out_parents), 0,
895 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
896 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "spdif_out_mux_clk", NULL);
898
899 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mux_clk", 0,
900 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
901 0, &_lock);
902 clk_register_clkdev(clk, NULL, "spdif-out");
903
904 clk = clk_register_mux(NULL, "spdif_in_mux_clk", spdif_in_parents,
905 ARRAY_SIZE(spdif_in_parents), 0,
906 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
907 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
908 clk_register_clkdev(clk, "spdif_in_mux_clk", NULL);
909
910 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mux_clk", 0,
911 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
912 &_lock);
913 clk_register_clkdev(clk, NULL, "spdif-in");
914
915 clk = clk_register_gate(NULL, "acp_clk", "acp_mux_clk", 0,
916 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
917 &_lock);
918 clk_register_clkdev(clk, NULL, "acp_clk");
919
920 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mux_clk", 0,
921 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
922 &_lock);
923 clk_register_clkdev(clk, NULL, "plgpio");
924
925 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mux_clk", 0,
926 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
927 0, &_lock);
928 clk_register_clkdev(clk, NULL, "video_dec");
929
930 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mux_clk", 0,
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
932 0, &_lock);
933 clk_register_clkdev(clk, NULL, "video_enc");
934
935 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mux_clk", 0,
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
937 &_lock);
938 clk_register_clkdev(clk, NULL, "spear_vip");
939
940 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mux_clk", 0,
941 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
942 &_lock);
943 clk_register_clkdev(clk, NULL, "spear_camif.0");
944
945 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mux_clk", 0,
946 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
947 &_lock);
948 clk_register_clkdev(clk, NULL, "spear_camif.1");
949
950 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mux_clk", 0,
951 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
952 &_lock);
953 clk_register_clkdev(clk, NULL, "spear_camif.2");
954
955 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mux_clk", 0,
956 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
957 &_lock);
958 clk_register_clkdev(clk, NULL, "spear_camif.3");
959
960 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mux_clk", 0,
961 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
962 &_lock);
963 clk_register_clkdev(clk, NULL, "pwm");
964}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 11:34:43 -0400