diff options
Diffstat (limited to 'drivers/clk/socfpga/clk-pll.c')
-rw-r--r-- | drivers/clk/socfpga/clk-pll.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index 88dafb5e9627..de6da957a09d 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/clk-provider.h> | 20 | #include <linux/clk-provider.h> |
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/of.h> | 22 | #include <linux/of.h> |
23 | #include <linux/of_address.h> | ||
23 | 24 | ||
24 | #include "clk.h" | 25 | #include "clk.h" |
25 | 26 | ||
@@ -43,6 +44,8 @@ | |||
43 | 44 | ||
44 | #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) | 45 | #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) |
45 | 46 | ||
47 | void __iomem *clk_mgr_base_addr; | ||
48 | |||
46 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, | 49 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, |
47 | unsigned long parent_rate) | 50 | unsigned long parent_rate) |
48 | { | 51 | { |
@@ -87,6 +90,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, | |||
87 | const char *clk_name = node->name; | 90 | const char *clk_name = node->name; |
88 | const char *parent_name[SOCFPGA_MAX_PARENTS]; | 91 | const char *parent_name[SOCFPGA_MAX_PARENTS]; |
89 | struct clk_init_data init; | 92 | struct clk_init_data init; |
93 | struct device_node *clkmgr_np; | ||
90 | int rc; | 94 | int rc; |
91 | int i = 0; | 95 | int i = 0; |
92 | 96 | ||
@@ -96,6 +100,9 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, | |||
96 | if (WARN_ON(!pll_clk)) | 100 | if (WARN_ON(!pll_clk)) |
97 | return NULL; | 101 | return NULL; |
98 | 102 | ||
103 | clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); | ||
104 | clk_mgr_base_addr = of_iomap(clkmgr_np, 0); | ||
105 | BUG_ON(!clk_mgr_base_addr); | ||
99 | pll_clk->hw.reg = clk_mgr_base_addr + reg; | 106 | pll_clk->hw.reg = clk_mgr_base_addr + reg; |
100 | 107 | ||
101 | of_property_read_string(node, "clock-output-names", &clk_name); | 108 | of_property_read_string(node, "clock-output-names", &clk_name); |