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path: root/drivers/clk/samsung/clk-s3c2410.c
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Diffstat (limited to 'drivers/clk/samsung/clk-s3c2410.c')
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c51
1 files changed, 28 insertions, 23 deletions
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index 7b4182186a30..ba0716801db2 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -344,21 +344,24 @@ struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
344 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0), 344 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
345}; 345};
346 346
347static void __init s3c2410_common_clk_register_fixed_ext(unsigned long xti_f) 347static void __init s3c2410_common_clk_register_fixed_ext(
348 struct samsung_clk_provider *ctx,
349 unsigned long xti_f)
348{ 350{
349 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal"); 351 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
350 352
351 s3c2410_common_frate_clks[0].fixed_rate = xti_f; 353 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
352 samsung_clk_register_fixed_rate(s3c2410_common_frate_clks, 354 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
353 ARRAY_SIZE(s3c2410_common_frate_clks)); 355 ARRAY_SIZE(s3c2410_common_frate_clks));
354 356
355 samsung_clk_register_alias(&xti_alias, 1); 357 samsung_clk_register_alias(ctx, &xti_alias, 1);
356} 358}
357 359
358void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, 360void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
359 int current_soc, 361 int current_soc,
360 void __iomem *base) 362 void __iomem *base)
361{ 363{
364 struct samsung_clk_provider *ctx;
362 reg_base = base; 365 reg_base = base;
363 366
364 if (np) { 367 if (np) {
@@ -367,11 +370,13 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
367 panic("%s: failed to map registers\n", __func__); 370 panic("%s: failed to map registers\n", __func__);
368 } 371 }
369 372
370 samsung_clk_init(np, reg_base, NR_CLKS); 373 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
374 if (!ctx)
375 panic("%s: unable to allocate context.\n", __func__);
371 376
372 /* Register external clocks only in non-dt cases */ 377 /* Register external clocks only in non-dt cases */
373 if (!np) 378 if (!np)
374 s3c2410_common_clk_register_fixed_ext(xti_f); 379 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
375 380
376 if (current_soc == 2410) { 381 if (current_soc == 2410) {
377 if (_get_rate("xti") == 12 * MHZ) { 382 if (_get_rate("xti") == 12 * MHZ) {
@@ -380,7 +385,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
380 } 385 }
381 386
382 /* Register PLLs. */ 387 /* Register PLLs. */
383 samsung_clk_register_pll(s3c2410_plls, 388 samsung_clk_register_pll(ctx, s3c2410_plls,
384 ARRAY_SIZE(s3c2410_plls), reg_base); 389 ARRAY_SIZE(s3c2410_plls), reg_base);
385 390
386 } else { /* S3C2440, S3C2442 */ 391 } else { /* S3C2440, S3C2442 */
@@ -396,49 +401,49 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
396 } 401 }
397 402
398 /* Register PLLs. */ 403 /* Register PLLs. */
399 samsung_clk_register_pll(s3c244x_common_plls, 404 samsung_clk_register_pll(ctx, s3c244x_common_plls,
400 ARRAY_SIZE(s3c244x_common_plls), reg_base); 405 ARRAY_SIZE(s3c244x_common_plls), reg_base);
401 } 406 }
402 407
403 /* Register common internal clocks. */ 408 /* Register common internal clocks. */
404 samsung_clk_register_mux(s3c2410_common_muxes, 409 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
405 ARRAY_SIZE(s3c2410_common_muxes)); 410 ARRAY_SIZE(s3c2410_common_muxes));
406 samsung_clk_register_div(s3c2410_common_dividers, 411 samsung_clk_register_div(ctx, s3c2410_common_dividers,
407 ARRAY_SIZE(s3c2410_common_dividers)); 412 ARRAY_SIZE(s3c2410_common_dividers));
408 samsung_clk_register_gate(s3c2410_common_gates, 413 samsung_clk_register_gate(ctx, s3c2410_common_gates,
409 ARRAY_SIZE(s3c2410_common_gates)); 414 ARRAY_SIZE(s3c2410_common_gates));
410 415
411 if (current_soc == S3C2440 || current_soc == S3C2442) { 416 if (current_soc == S3C2440 || current_soc == S3C2442) {
412 samsung_clk_register_div(s3c244x_common_dividers, 417 samsung_clk_register_div(ctx, s3c244x_common_dividers,
413 ARRAY_SIZE(s3c244x_common_dividers)); 418 ARRAY_SIZE(s3c244x_common_dividers));
414 samsung_clk_register_gate(s3c244x_common_gates, 419 samsung_clk_register_gate(ctx, s3c244x_common_gates,
415 ARRAY_SIZE(s3c244x_common_gates)); 420 ARRAY_SIZE(s3c244x_common_gates));
416 samsung_clk_register_mux(s3c244x_common_muxes, 421 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
417 ARRAY_SIZE(s3c244x_common_muxes)); 422 ARRAY_SIZE(s3c244x_common_muxes));
418 samsung_clk_register_fixed_factor(s3c244x_common_ffactor, 423 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
419 ARRAY_SIZE(s3c244x_common_ffactor)); 424 ARRAY_SIZE(s3c244x_common_ffactor));
420 } 425 }
421 426
422 /* Register SoC-specific clocks. */ 427 /* Register SoC-specific clocks. */
423 switch (current_soc) { 428 switch (current_soc) {
424 case S3C2410: 429 case S3C2410:
425 samsung_clk_register_div(s3c2410_dividers, 430 samsung_clk_register_div(ctx, s3c2410_dividers,
426 ARRAY_SIZE(s3c2410_dividers)); 431 ARRAY_SIZE(s3c2410_dividers));
427 samsung_clk_register_fixed_factor(s3c2410_ffactor, 432 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
428 ARRAY_SIZE(s3c2410_ffactor)); 433 ARRAY_SIZE(s3c2410_ffactor));
429 samsung_clk_register_alias(s3c2410_aliases, 434 samsung_clk_register_alias(ctx, s3c2410_aliases,
430 ARRAY_SIZE(s3c2410_common_aliases)); 435 ARRAY_SIZE(s3c2410_common_aliases));
431 break; 436 break;
432 case S3C2440: 437 case S3C2440:
433 samsung_clk_register_mux(s3c2440_muxes, 438 samsung_clk_register_mux(ctx, s3c2440_muxes,
434 ARRAY_SIZE(s3c2440_muxes)); 439 ARRAY_SIZE(s3c2440_muxes));
435 samsung_clk_register_gate(s3c2440_gates, 440 samsung_clk_register_gate(ctx, s3c2440_gates,
436 ARRAY_SIZE(s3c2440_gates)); 441 ARRAY_SIZE(s3c2440_gates));
437 break; 442 break;
438 case S3C2442: 443 case S3C2442:
439 samsung_clk_register_mux(s3c2442_muxes, 444 samsung_clk_register_mux(ctx, s3c2442_muxes,
440 ARRAY_SIZE(s3c2442_muxes)); 445 ARRAY_SIZE(s3c2442_muxes));
441 samsung_clk_register_fixed_factor(s3c2442_ffactor, 446 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
442 ARRAY_SIZE(s3c2442_ffactor)); 447 ARRAY_SIZE(s3c2442_ffactor));
443 break; 448 break;
444 } 449 }
@@ -447,11 +452,11 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
447 * Register common aliases at the end, as some of the aliased clocks 452 * Register common aliases at the end, as some of the aliased clocks
448 * are SoC specific. 453 * are SoC specific.
449 */ 454 */
450 samsung_clk_register_alias(s3c2410_common_aliases, 455 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
451 ARRAY_SIZE(s3c2410_common_aliases)); 456 ARRAY_SIZE(s3c2410_common_aliases));
452 457
453 if (current_soc == S3C2440 || current_soc == S3C2442) { 458 if (current_soc == S3C2440 || current_soc == S3C2442) {
454 samsung_clk_register_alias(s3c244x_common_aliases, 459 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
455 ARRAY_SIZE(s3c244x_common_aliases)); 460 ARRAY_SIZE(s3c244x_common_aliases));
456 } 461 }
457 462