aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/samsung/clk-exynos5420.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c1127
1 files changed, 780 insertions, 347 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 60b26819bed5..9d7d7eed03fd 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -27,18 +27,24 @@
27#define DIV_CPU1 0x504 27#define DIV_CPU1 0x504
28#define GATE_BUS_CPU 0x700 28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800 29#define GATE_SCLK_CPU 0x800
30#define CLKOUT_CMU_CPU 0xa00
31#define GATE_IP_G2D 0x8800
30#define CPLL_LOCK 0x10020 32#define CPLL_LOCK 0x10020
31#define DPLL_LOCK 0x10030 33#define DPLL_LOCK 0x10030
32#define EPLL_LOCK 0x10040 34#define EPLL_LOCK 0x10040
33#define RPLL_LOCK 0x10050 35#define RPLL_LOCK 0x10050
34#define IPLL_LOCK 0x10060 36#define IPLL_LOCK 0x10060
35#define SPLL_LOCK 0x10070 37#define SPLL_LOCK 0x10070
36#define VPLL_LOCK 0x10070 38#define VPLL_LOCK 0x10080
37#define MPLL_LOCK 0x10090 39#define MPLL_LOCK 0x10090
38#define CPLL_CON0 0x10120 40#define CPLL_CON0 0x10120
39#define DPLL_CON0 0x10128 41#define DPLL_CON0 0x10128
40#define EPLL_CON0 0x10130 42#define EPLL_CON0 0x10130
43#define EPLL_CON1 0x10134
44#define EPLL_CON2 0x10138
41#define RPLL_CON0 0x10140 45#define RPLL_CON0 0x10140
46#define RPLL_CON1 0x10144
47#define RPLL_CON2 0x10148
42#define IPLL_CON0 0x10150 48#define IPLL_CON0 0x10150
43#define SPLL_CON0 0x10160 49#define SPLL_CON0 0x10160
44#define VPLL_CON0 0x10170 50#define VPLL_CON0 0x10170
@@ -51,21 +57,31 @@
51#define SRC_TOP5 0x10214 57#define SRC_TOP5 0x10214
52#define SRC_TOP6 0x10218 58#define SRC_TOP6 0x10218
53#define SRC_TOP7 0x1021c 59#define SRC_TOP7 0x1021c
60#define SRC_TOP8 0x10220 /* 5800 specific */
61#define SRC_TOP9 0x10224 /* 5800 specific */
54#define SRC_DISP10 0x1022c 62#define SRC_DISP10 0x1022c
55#define SRC_MAU 0x10240 63#define SRC_MAU 0x10240
56#define SRC_FSYS 0x10244 64#define SRC_FSYS 0x10244
57#define SRC_PERIC0 0x10250 65#define SRC_PERIC0 0x10250
58#define SRC_PERIC1 0x10254 66#define SRC_PERIC1 0x10254
67#define SRC_ISP 0x10270
68#define SRC_CAM 0x10274 /* 5800 specific */
59#define SRC_TOP10 0x10280 69#define SRC_TOP10 0x10280
60#define SRC_TOP11 0x10284 70#define SRC_TOP11 0x10284
61#define SRC_TOP12 0x10288 71#define SRC_TOP12 0x10288
62#define SRC_MASK_DISP10 0x1032c 72#define SRC_TOP13 0x1028c /* 5800 specific */
73#define SRC_MASK_TOP2 0x10308
74#define SRC_MASK_TOP7 0x1031c
75#define SRC_MASK_DISP10 0x1032c
76#define SRC_MASK_MAU 0x10334
63#define SRC_MASK_FSYS 0x10340 77#define SRC_MASK_FSYS 0x10340
64#define SRC_MASK_PERIC0 0x10350 78#define SRC_MASK_PERIC0 0x10350
65#define SRC_MASK_PERIC1 0x10354 79#define SRC_MASK_PERIC1 0x10354
66#define DIV_TOP0 0x10500 80#define DIV_TOP0 0x10500
67#define DIV_TOP1 0x10504 81#define DIV_TOP1 0x10504
68#define DIV_TOP2 0x10508 82#define DIV_TOP2 0x10508
83#define DIV_TOP8 0x10520 /* 5800 specific */
84#define DIV_TOP9 0x10524 /* 5800 specific */
69#define DIV_DISP10 0x1052c 85#define DIV_DISP10 0x1052c
70#define DIV_MAU 0x10544 86#define DIV_MAU 0x10544
71#define DIV_FSYS0 0x10548 87#define DIV_FSYS0 0x10548
@@ -76,54 +92,82 @@
76#define DIV_PERIC2 0x10560 92#define DIV_PERIC2 0x10560
77#define DIV_PERIC3 0x10564 93#define DIV_PERIC3 0x10564
78#define DIV_PERIC4 0x10568 94#define DIV_PERIC4 0x10568
95#define DIV_CAM 0x10574 /* 5800 specific */
96#define SCLK_DIV_ISP0 0x10580
97#define SCLK_DIV_ISP1 0x10584
98#define DIV2_RATIO0 0x10590
99#define DIV4_RATIO 0x105a0
79#define GATE_BUS_TOP 0x10700 100#define GATE_BUS_TOP 0x10700
101#define GATE_BUS_GEN 0x1073c
80#define GATE_BUS_FSYS0 0x10740 102#define GATE_BUS_FSYS0 0x10740
103#define GATE_BUS_FSYS2 0x10748
81#define GATE_BUS_PERIC 0x10750 104#define GATE_BUS_PERIC 0x10750
82#define GATE_BUS_PERIC1 0x10754 105#define GATE_BUS_PERIC1 0x10754
83#define GATE_BUS_PERIS0 0x10760 106#define GATE_BUS_PERIS0 0x10760
84#define GATE_BUS_PERIS1 0x10764 107#define GATE_BUS_PERIS1 0x10764
108#define GATE_BUS_NOC 0x10770
109#define GATE_TOP_SCLK_ISP 0x10870
85#define GATE_IP_GSCL0 0x10910 110#define GATE_IP_GSCL0 0x10910
86#define GATE_IP_GSCL1 0x10920 111#define GATE_IP_GSCL1 0x10920
112#define GATE_IP_CAM 0x10924 /* 5800 specific */
87#define GATE_IP_MFC 0x1092c 113#define GATE_IP_MFC 0x1092c
88#define GATE_IP_DISP1 0x10928 114#define GATE_IP_DISP1 0x10928
89#define GATE_IP_G3D 0x10930 115#define GATE_IP_G3D 0x10930
90#define GATE_IP_GEN 0x10934 116#define GATE_IP_GEN 0x10934
117#define GATE_IP_FSYS 0x10944
118#define GATE_IP_PERIC 0x10950
119#define GATE_IP_PERIS 0x10960
91#define GATE_IP_MSCL 0x10970 120#define GATE_IP_MSCL 0x10970
92#define GATE_TOP_SCLK_GSCL 0x10820 121#define GATE_TOP_SCLK_GSCL 0x10820
93#define GATE_TOP_SCLK_DISP1 0x10828 122#define GATE_TOP_SCLK_DISP1 0x10828
94#define GATE_TOP_SCLK_MAU 0x1083c 123#define GATE_TOP_SCLK_MAU 0x1083c
95#define GATE_TOP_SCLK_FSYS 0x10840 124#define GATE_TOP_SCLK_FSYS 0x10840
96#define GATE_TOP_SCLK_PERIC 0x10850 125#define GATE_TOP_SCLK_PERIC 0x10850
126#define TOP_SPARE2 0x10b08
97#define BPLL_LOCK 0x20010 127#define BPLL_LOCK 0x20010
98#define BPLL_CON0 0x20110 128#define BPLL_CON0 0x20110
99#define SRC_CDREX 0x20200
100#define KPLL_LOCK 0x28000 129#define KPLL_LOCK 0x28000
101#define KPLL_CON0 0x28100 130#define KPLL_CON0 0x28100
102#define SRC_KFC 0x28200 131#define SRC_KFC 0x28200
103#define DIV_KFC0 0x28500 132#define DIV_KFC0 0x28500
104 133
134/* Exynos5x SoC type */
135enum exynos5x_soc {
136 EXYNOS5420,
137 EXYNOS5800,
138};
139
105/* list of PLLs */ 140/* list of PLLs */
106enum exynos5420_plls { 141enum exynos5x_plls {
107 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 142 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
108 bpll, kpll, 143 bpll, kpll,
109 nr_plls /* number of PLLs */ 144 nr_plls /* number of PLLs */
110}; 145};
111 146
112static void __iomem *reg_base; 147static void __iomem *reg_base;
148static enum exynos5x_soc exynos5x_soc;
113 149
114#ifdef CONFIG_PM_SLEEP 150#ifdef CONFIG_PM_SLEEP
115static struct samsung_clk_reg_dump *exynos5420_save; 151static struct samsung_clk_reg_dump *exynos5x_save;
152static struct samsung_clk_reg_dump *exynos5800_save;
116 153
117/* 154/*
118 * list of controller registers to be saved and restored during a 155 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle. 156 * suspend/resume cycle.
120 */ 157 */
121static unsigned long exynos5420_clk_regs[] __initdata = { 158static unsigned long exynos5x_clk_regs[] __initdata = {
122 SRC_CPU, 159 SRC_CPU,
123 DIV_CPU0, 160 DIV_CPU0,
124 DIV_CPU1, 161 DIV_CPU1,
125 GATE_BUS_CPU, 162 GATE_BUS_CPU,
126 GATE_SCLK_CPU, 163 GATE_SCLK_CPU,
164 CLKOUT_CMU_CPU,
165 EPLL_CON0,
166 EPLL_CON1,
167 EPLL_CON2,
168 RPLL_CON0,
169 RPLL_CON1,
170 RPLL_CON2,
127 SRC_TOP0, 171 SRC_TOP0,
128 SRC_TOP1, 172 SRC_TOP1,
129 SRC_TOP2, 173 SRC_TOP2,
@@ -140,10 +184,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
140 SRC_TOP10, 184 SRC_TOP10,
141 SRC_TOP11, 185 SRC_TOP11,
142 SRC_TOP12, 186 SRC_TOP12,
187 SRC_MASK_TOP2,
188 SRC_MASK_TOP7,
143 SRC_MASK_DISP10, 189 SRC_MASK_DISP10,
144 SRC_MASK_FSYS, 190 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0, 191 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1, 192 SRC_MASK_PERIC1,
193 SRC_ISP,
147 DIV_TOP0, 194 DIV_TOP0,
148 DIV_TOP1, 195 DIV_TOP1,
149 DIV_TOP2, 196 DIV_TOP2,
@@ -157,41 +204,71 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
157 DIV_PERIC2, 204 DIV_PERIC2,
158 DIV_PERIC3, 205 DIV_PERIC3,
159 DIV_PERIC4, 206 DIV_PERIC4,
207 SCLK_DIV_ISP0,
208 SCLK_DIV_ISP1,
209 DIV2_RATIO0,
210 DIV4_RATIO,
160 GATE_BUS_TOP, 211 GATE_BUS_TOP,
212 GATE_BUS_GEN,
161 GATE_BUS_FSYS0, 213 GATE_BUS_FSYS0,
214 GATE_BUS_FSYS2,
162 GATE_BUS_PERIC, 215 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1, 216 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0, 217 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1, 218 GATE_BUS_PERIS1,
219 GATE_BUS_NOC,
220 GATE_TOP_SCLK_ISP,
166 GATE_IP_GSCL0, 221 GATE_IP_GSCL0,
167 GATE_IP_GSCL1, 222 GATE_IP_GSCL1,
168 GATE_IP_MFC, 223 GATE_IP_MFC,
169 GATE_IP_DISP1, 224 GATE_IP_DISP1,
170 GATE_IP_G3D, 225 GATE_IP_G3D,
171 GATE_IP_GEN, 226 GATE_IP_GEN,
227 GATE_IP_FSYS,
228 GATE_IP_PERIC,
229 GATE_IP_PERIS,
172 GATE_IP_MSCL, 230 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL, 231 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1, 232 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU, 233 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS, 234 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC, 235 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX, 236 TOP_SPARE2,
179 SRC_KFC, 237 SRC_KFC,
180 DIV_KFC0, 238 DIV_KFC0,
181}; 239};
182 240
241static unsigned long exynos5800_clk_regs[] __initdata = {
242 SRC_TOP8,
243 SRC_TOP9,
244 SRC_CAM,
245 SRC_TOP1,
246 DIV_TOP8,
247 DIV_TOP9,
248 DIV_CAM,
249 GATE_IP_CAM,
250};
251
183static int exynos5420_clk_suspend(void) 252static int exynos5420_clk_suspend(void)
184{ 253{
185 samsung_clk_save(reg_base, exynos5420_save, 254 samsung_clk_save(reg_base, exynos5x_save,
186 ARRAY_SIZE(exynos5420_clk_regs)); 255 ARRAY_SIZE(exynos5x_clk_regs));
256
257 if (exynos5x_soc == EXYNOS5800)
258 samsung_clk_save(reg_base, exynos5800_save,
259 ARRAY_SIZE(exynos5800_clk_regs));
187 260
188 return 0; 261 return 0;
189} 262}
190 263
191static void exynos5420_clk_resume(void) 264static void exynos5420_clk_resume(void)
192{ 265{
193 samsung_clk_restore(reg_base, exynos5420_save, 266 samsung_clk_restore(reg_base, exynos5x_save,
194 ARRAY_SIZE(exynos5420_clk_regs)); 267 ARRAY_SIZE(exynos5x_clk_regs));
268
269 if (exynos5x_soc == EXYNOS5800)
270 samsung_clk_restore(reg_base, exynos5800_save,
271 ARRAY_SIZE(exynos5800_clk_regs));
195} 272}
196 273
197static struct syscore_ops exynos5420_clk_syscore_ops = { 274static struct syscore_ops exynos5420_clk_syscore_ops = {
@@ -201,108 +278,183 @@ static struct syscore_ops exynos5420_clk_syscore_ops = {
201 278
202static void exynos5420_clk_sleep_init(void) 279static void exynos5420_clk_sleep_init(void)
203{ 280{
204 exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 281 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
205 ARRAY_SIZE(exynos5420_clk_regs)); 282 ARRAY_SIZE(exynos5x_clk_regs));
206 if (!exynos5420_save) { 283 if (!exynos5x_save) {
207 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 284 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
208 __func__); 285 __func__);
209 return; 286 return;
210 } 287 }
211 288
289 if (exynos5x_soc == EXYNOS5800) {
290 exynos5800_save =
291 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
292 ARRAY_SIZE(exynos5800_clk_regs));
293 if (!exynos5800_save)
294 goto err_soc;
295 }
296
212 register_syscore_ops(&exynos5420_clk_syscore_ops); 297 register_syscore_ops(&exynos5420_clk_syscore_ops);
298 return;
299err_soc:
300 kfree(exynos5x_save);
301 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
302 __func__);
303 return;
213} 304}
214#else 305#else
215static void exynos5420_clk_sleep_init(void) {} 306static void exynos5420_clk_sleep_init(void) {}
216#endif 307#endif
217 308
218/* list of all parent clocks */ 309/* list of all parent clocks */
219PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 310PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
220 "sclk_mpll", "sclk_spll" }; 311 "mout_sclk_mpll", "mout_sclk_spll"};
221PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 312PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
222PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 313PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
223PNAME(apll_p) = { "fin_pll", "fout_apll", }; 314PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
224PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 315PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
225PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 316PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
226PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 317PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
227PNAME(epll_p) = { "fin_pll", "fout_epll", }; 318PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
228PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 319PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
229PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 320PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
230PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 321PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
231PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 322PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
232PNAME(spll_p) = { "fin_pll", "fout_spll", }; 323PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
233PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 324PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
234 325
235PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 326PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
236PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 327 "mout_sclk_mpll"};
237 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 328PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
238PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 329 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
239PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 330 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
240PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 331PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
241 332PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
242PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 333PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
243PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 334
244 335PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
245PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 336PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
246PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 337PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
247 338PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
248PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 339
249PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 340PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
250 341PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
251PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 342PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
252PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 343PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
253 344
254PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 345PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
255PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 346PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
256 347PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
257PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 348PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
258PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 349
259 350PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
260PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 351PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
261PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 352PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
262 353
263PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 354PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
264PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 355PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
265 356
266PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 357PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
267PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 358 "mout_sclk_spll"};
268 359PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
269PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 360
270PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 361PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
271 362PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
272PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 363
273PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 364PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
274 365PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
275PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 366
276PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 367PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
277 368PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
278PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 369
279PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 370PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
280 371PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
281PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 372
282PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 373PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
283 374PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
284PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 375
285PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 376PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
286 377PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
287PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 378PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
288 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 379
289PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 380PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
290 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 381PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
291PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 382
292 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 383PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
293PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 384PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
294 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 385
295PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; 386PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
296PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 387PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
297 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 388PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
389PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
390
391PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
392PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
393
394PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
395PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
396
397PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
398PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
399
400PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
401PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
402
403PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
404 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
405 "mout_sclk_epll", "mout_sclk_rpll"};
406PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
407 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
408 "mout_sclk_epll", "mout_sclk_rpll"};
409PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
410 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
411 "mout_sclk_epll", "mout_sclk_rpll"};
412PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
413 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
414 "mout_sclk_epll", "mout_sclk_rpll"};
415PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
416PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
417 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
418 "mout_sclk_epll", "mout_sclk_rpll"};
419PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
420 "mout_sclk_mpll", "mout_sclk_spll"};
421/* List of parents specific to exynos5800 */
422PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
423PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
424 "mout_sclk_mpll", "ff_dout_spll2" };
425PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
426 "mout_sclk_mpll", "ff_dout_spll2",
427 "mout_epll2", "mout_sclk_ipll" };
428PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
429 "mout_sclk_mpll", "ff_dout_spll2",
430 "mout_epll2" };
431PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
432 "mout_sclk_mpll", "mout_sclk_spll" };
433PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
434 "mout_sclk_mpll", "ff_dout_spll2" };
435PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
436 "mout_sclk_mpll", "mout_sclk_spll",
437 "mout_epll2", "mout_sclk_ipll" };
438PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
439 "mout_sclk_mpll",
440 "ff_dout_spll2" };
441PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
442PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
443PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
444PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
445PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
446PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
447PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
448PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
298 449
299/* fixed rate clocks generated outside the soc */ 450/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 451static struct samsung_fixed_rate_clock
452 exynos5x_fixed_rate_ext_clks[] __initdata = {
301 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 453 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302}; 454};
303 455
304/* fixed rate clocks generated inside the soc */ 456/* fixed rate clocks generated inside the soc */
305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 457static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
306 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 458 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 459 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 460 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
@@ -310,146 +462,309 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
310 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 462 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311}; 463};
312 464
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 465static struct samsung_fixed_factor_clock
314 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 466 exynos5x_fixed_factor_clks[] __initdata = {
467 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
468 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
315}; 469};
316 470
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 471static struct samsung_fixed_factor_clock
318 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 472 exynos5800_fixed_factor_clks[] __initdata = {
319 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 473 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
320 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 474 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
321 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 475};
322 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 476
323 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 477struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
324 478 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
325 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 479 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
326 480 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
327 MUX_A(0, "mout_aclk400_mscl", group1_p, 481 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 482
329 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 483 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
330 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 484 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
331 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 485 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
332 486 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
333 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 487 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
334 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 488
335 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 489 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
336 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 490 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
337 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 491 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
338 492 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
339 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 493 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
340 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 494 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
341 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 495
342 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 496 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
343 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 497 20, 2),
344 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 498 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
345 499 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
346 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 500
501 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
502 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
503 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
504 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
505
506 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
507 SRC_TOP9, 16, 1),
508 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
509 SRC_TOP9, 20, 1),
510 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
511 SRC_TOP9, 24, 1),
512 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
513 SRC_TOP9, 28, 1),
514
515 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
516 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
517 SRC_TOP13, 20, 1),
518 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
519 SRC_TOP13, 24, 1),
520 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
521 SRC_TOP13, 28, 1),
522
523 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
524};
525
526struct samsung_div_clock exynos5800_div_clks[] __initdata = {
527 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
528
529 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
530 DIV_TOP8, 16, 3),
531 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
532 DIV_TOP8, 20, 3),
533 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
534 DIV_TOP8, 24, 3),
535 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
536 DIV_TOP8, 28, 3),
537
538 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
539 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
540};
541
542struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
543 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
544 GATE_BUS_TOP, 24, 0, 0),
545 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
546 GATE_BUS_TOP, 27, 0, 0),
547};
548
549struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
550 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
551 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
552 TOP_SPARE2, 4, 1),
553
554 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
555 MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
556 SRC_TOP0, 4, 2, "aclk400_mscl"),
557 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
558 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
559
560 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
561 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
562 SRC_TOP1, 4, 2),
563 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
564 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
565 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
566
567 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
568 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
569 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
570 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
571 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
572 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
573
574 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
575
576 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
577};
578
579struct samsung_div_clock exynos5420_div_clks[] __initdata = {
580 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
581 DIV_TOP0, 16, 3),
582};
583
584static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
585 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
586 SRC_TOP7, 4, 1),
587 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
588 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
589
590 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
591 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
592 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
593 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
594
595 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
596 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
597 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
598 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
599
600 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
601 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
602
603 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
604
605 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
606 SRC_TOP3, 0, 1),
607 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 608 SRC_TOP3, 4, 1),
348 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p, 609 MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 610 SRC_TOP3, 8, 1),
350 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 611 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 612 SRC_TOP3, 12, 1),
352 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 613 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
614 SRC_TOP3, 16, 1),
615 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
616 SRC_TOP3, 20, 1),
617 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
618 SRC_TOP3, 24, 1),
619 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 620 SRC_TOP3, 28, 1),
354 621
355 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 622 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 623 SRC_TOP4, 0, 1),
357 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 624 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
358 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 625 SRC_TOP4, 4, 1),
359 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 626 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
360 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 627 SRC_TOP4, 8, 1),
361 628 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
362 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 629 SRC_TOP4, 12, 1),
363 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 630 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
364 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 631 SRC_TOP4, 16, 1),
365 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, 632 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
366 SRC_TOP5, 16, 1, "aclkg3d"), 633 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
367 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 634 MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
635
636 MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
637 SRC_TOP5, 0, 1),
638 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
639 SRC_TOP5, 4, 1),
640 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
641 SRC_TOP5, 8, 1),
642 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
643 SRC_TOP5, 12, 1),
644 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
645 SRC_TOP5, 16, 1),
646 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 647 SRC_TOP5, 20, 1),
369 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 648 MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 649 SRC_TOP5, 24, 1),
371 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 650 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 651 SRC_TOP5, 28, 1),
373 652
374 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 653 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
375 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 654 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
376 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 655 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
377 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 656 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
378 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 657 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
379 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 658 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
380 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 659 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
381 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 660 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
382 661
383 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 662 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
384 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 663 SRC_TOP10, 0, 1),
385 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 664 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
665 SRC_TOP10, 4, 1),
666 MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
667 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 668 SRC_TOP10, 12, 1),
387 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 669 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
388 670 SRC_TOP10, 16, 1),
389 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 671 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
672 SRC_TOP10, 20, 1),
673 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
674 SRC_TOP10, 24, 1),
675 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
676 SRC_TOP10, 28, 1),
677
678 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 679 SRC_TOP11, 0, 1),
391 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 680 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
392 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 681 SRC_TOP11, 4, 1),
393 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 682 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
394 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 683 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
395 684 SRC_TOP11, 12, 1),
396 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 685 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
397 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 686 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
398 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 687 MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
399 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 688
400 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 689 MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
690 SRC_TOP12, 4, 1),
691 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
692 SRC_TOP12, 8, 1),
693 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
694 SRC_TOP12, 12, 1),
695 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
696 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
697 SRC_TOP12, 20, 1),
698 MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 699 SRC_TOP12, 24, 1),
402 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 700 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
701 SRC_TOP12, 28, 1),
403 702
404 /* DISP1 Block */ 703 /* DISP1 Block */
405 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 704 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
406 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 705 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
407 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 706 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
408 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 707 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
409 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 708 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
709
710 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
410 711
411 /* MAU Block */ 712 /* MAU Block */
412 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 713 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
413 714
414 /* FSYS Block */ 715 /* FSYS Block */
415 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 716 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
416 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 717 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
417 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 718 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
418 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 719 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
419 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 720 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
420 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 721 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
722 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
421 723
422 /* PERIC Block */ 724 /* PERIC Block */
423 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 725 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
424 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 726 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
425 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 727 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
426 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 728 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
427 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 729 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
428 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 730 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
429 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 731 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
430 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 732 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
431 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 733 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
432 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 734 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
433 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 735 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
434 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 736 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
737
738 /* ISP Block */
739 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
740 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
741 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
742 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
743 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
435}; 744};
436 745
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 746static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
438 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 747 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 748 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 749 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 750 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
442 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 751 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 752
753 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
444 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 754 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 755 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 756 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
757 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
447 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 758 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 759 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 760
450 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 761 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 762 DIV_TOP1, 0, 3),
763 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
764 DIV_TOP1, 4, 3),
452 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 765 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
766 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
767 DIV_TOP1, 16, 3),
453 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 768 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 769 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 770 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
@@ -458,15 +773,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
458 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 773 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 774 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 775 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 776 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
462 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 777 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 778
465 /* DISP1 Block */ 779 /* DISP1 Block */
466 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 780 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
467 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 781 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 782 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 783 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
784 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
785 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
470 786
471 /* Audio Block */ 787 /* Audio Block */
472 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 788 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -484,6 +800,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
484 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 800 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 801
486 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 802 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
803 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
487 804
488 /* UART and PWM */ 805 /* UART and PWM */
489 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 806 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -497,6 +814,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
497 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 814 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 815 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 816
817 /* Mfc Block */
818 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
819
500 /* PCM */ 820 /* PCM */
501 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 821 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 822 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
@@ -509,15 +829,43 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
509 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 829 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 830
511 /* SPI Pre-Ratio */ 831 /* SPI Pre-Ratio */
512 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 832 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 833 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 834 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
835
836 /* GSCL Block */
837 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
838 DIV2_RATIO0, 4, 2),
839 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
840
841 /* MSCL Block */
842 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
843
844 /* PSGEN */
845 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
846 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
847
848 /* ISP Block */
849 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
850 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
851 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
852 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
853 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
854 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
855 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
856 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
857 CLK_SET_RATE_PARENT, 0),
858 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
859 CLK_SET_RATE_PARENT, 0),
515}; 860};
516 861
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 862static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 863 /* G2D */
519 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 864 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
520 "mct"), 865 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
866 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
867 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
868 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
521 869
522 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 870 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
523 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 871 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -530,20 +878,42 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
530 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 878 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
531 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 879 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
532 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 880 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
881 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
882 GATE_BUS_TOP, 5, 0, 0),
533 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 883 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
534 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 884 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
535 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 885 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
536 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 886 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
537 GATE(0, "pclk66_gpio", "mout_sw_aclk66", 887 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
888 GATE_BUS_TOP, 8, 0, 0),
889 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
538 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 890 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
539 GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 891 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
540 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 892 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
541 GATE(0, "aclk66_peric", "mout_aclk66_peric", 893 GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
542 GATE_BUS_TOP, 11, 0, 0), 894 GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
895 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
896 GATE_BUS_TOP, 13, 0, 0),
543 GATE(0, "aclk166", "mout_user_aclk166", 897 GATE(0, "aclk166", "mout_user_aclk166",
544 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 898 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
545 GATE(0, "aclk333", "mout_aclk333", 899 GATE(0, "aclk333", "mout_aclk333",
546 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 900 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
901 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
902 GATE_BUS_TOP, 16, 0, 0),
903 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
904 GATE_BUS_TOP, 17, 0, 0),
905 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
906 GATE_BUS_TOP, 18, 0, 0),
907 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
908 GATE_BUS_TOP, 28, 0, 0),
909 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
910 GATE_BUS_TOP, 29, 0, 0),
911
912 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
913 SRC_MASK_TOP2, 24, 0, 0),
914
915 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
916 SRC_MASK_TOP7, 20, 0, 0),
547 917
548 /* sclk */ 918 /* sclk */
549 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 919 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
@@ -554,11 +924,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
554 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 924 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
555 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 925 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
556 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 926 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
557 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 927 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
558 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 928 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 929 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
560 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 930 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 931 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
562 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 932 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 933 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
564 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 934 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
@@ -588,164 +958,191 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
588 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 958 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
589 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 959 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
590 960
591 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
592 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
593
594 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
595 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
596 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
597 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
598
599 /* Display */ 961 /* Display */
600 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 962 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
601 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 963 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
602 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 964 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
603 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 965 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
604 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 966 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
605 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 967 GATE_TOP_SCLK_DISP1, 9, 0, 0),
606 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 968 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
607 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 969 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
608 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 970 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
609 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 971 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
610 972
611 /* Maudio Block */ 973 /* Maudio Block */
612 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 974 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
613 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 975 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
614 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 976 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
615 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 977 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
616 /* FSYS */ 978
979 /* FSYS Block */
617 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 980 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
618 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 981 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
619 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 982 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
620 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 983 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
621 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 984 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
622 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 985 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
623 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 986 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
624 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 987 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
625 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 988 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
626 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 989 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
627 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 990 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
628 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 991 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
629 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 992 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
630 993 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
631 /* UART */ 994 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
632 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
633 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
634 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
635 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
636 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
637 /* I2C */
638 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
639 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
640 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
641 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
642 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
643 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
644 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
645 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
646 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
647 0),
648 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
649 /* SPI */
650 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
651 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
652 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
653 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
654 /* I2S */
655 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
656 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
657 /* PCM */
658 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
659 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
660 /* PWM */
661 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
662 /* SPDIF */
663 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
664 995
665 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 996 /* PERIC Block */
666 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 997 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
667 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 998 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),
999 GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),
1000 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),
1001 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),
1002 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),
1003 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),
1004 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),
1005 GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),
1006 GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),
1007 GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),
1008 GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),
1009 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),
1010 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),
1011 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),
1012 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),
1013 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),
1014 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),
1015 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),
1016 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),
1017 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),
1018 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),
1019 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),
1020 GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),
1021 GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),
1022 GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),
668 1023
1024 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
1025
1026 /* PERIS Block */
669 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1027 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
670 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 1028 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
671 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1029 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
672 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 1030 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
673 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 1031 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
674 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 1032 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
675 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 1033 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
676 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 1034 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
677 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 1035 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
678 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 1036 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
679 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 1037 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
680 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 1038 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
681 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 1039 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
682 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 1040 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
683 1041 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
684 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 1042 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
685 0), 1043 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1044 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1045 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1046 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1047
686 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1048 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
687 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 1049
688 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 1050 /* GEN Block */
689 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 1051 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
690 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 1052 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1053 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1054 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1055 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1056 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1057 GATE_IP_GEN, 6, 0, 0),
1058 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1059 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1060 GATE_IP_GEN, 9, 0, 0),
1061
1062 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1063 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1064 GATE_BUS_GEN, 28, 0, 0),
1065 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1066
1067 /* GSCL Block */
1068 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1069 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1070 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1071 GATE_TOP_SCLK_GSCL, 7, 0, 0),
691 1072
692 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1073 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
693 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1074 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
694 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 1075 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
695 1076 GATE_IP_GSCL0, 4, 0, 0),
696 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 1077 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
697 0), 1078 GATE_IP_GSCL0, 5, 0, 0),
698 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 1079 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1080 GATE_IP_GSCL0, 6, 0, 0),
1081
1082 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1083 GATE_IP_GSCL1, 2, 0, 0),
1084 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
699 GATE_IP_GSCL1, 3, 0, 0), 1085 GATE_IP_GSCL1, 3, 0, 0),
700 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 1086 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
701 GATE_IP_GSCL1, 4, 0, 0), 1087 GATE_IP_GSCL1, 4, 0, 0),
702 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 1088 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
703 0), 1089 GATE_IP_GSCL1, 6, 0, 0),
704 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 1090 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
705 0), 1091 GATE_IP_GSCL1, 7, 0, 0),
706 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 1092 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
707 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 1093 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
708 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 1094 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
709 GATE_IP_GSCL1, 16, 0, 0), 1095 GATE_IP_GSCL1, 16, 0, 0),
710 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1096 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
711 GATE_IP_GSCL1, 17, 0, 0), 1097 GATE_IP_GSCL1, 17, 0, 0),
712 1098
1099 /* MSCL Block */
1100 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1101 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1102 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1103 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1104 GATE_IP_MSCL, 8, 0, 0),
1105 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1106 GATE_IP_MSCL, 9, 0, 0),
1107 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1108 GATE_IP_MSCL, 10, 0, 0),
1109
713 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1110 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
714 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1111 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
715 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1112 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
716 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 1113 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
717 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1114 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
718 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 1115 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
719 0), 1116 GATE_IP_DISP1, 7, 0, 0),
1117 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1118 GATE_IP_DISP1, 8, 0, 0),
1119 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1120 GATE_IP_DISP1, 9, 0, 0),
1121
1122 /* ISP */
1123 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1124 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1125 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1126 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1127 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1128 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1129 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1130 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1131 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1132 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1133 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1134 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1135 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1136 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
720 1137
721 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1138 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
722 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 1139 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
723 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 1140 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
724
725 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
726 1141
727 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 1142 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
728 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
729 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
730 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
731 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
732 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
733 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
734
735 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
736 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
737 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
738 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
739 0),
740 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
741 0),
742 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
743 0),
744 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
745 0),
746}; 1143};
747 1144
748static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 1145static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
749 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1146 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
750 APLL_CON0, NULL), 1147 APLL_CON0, NULL),
751 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1148 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
@@ -776,8 +1173,11 @@ static struct of_device_id ext_clk_match[] __initdata = {
776}; 1173};
777 1174
778/* register exynos5420 clocks */ 1175/* register exynos5420 clocks */
779static void __init exynos5420_clk_init(struct device_node *np) 1176static void __init exynos5x_clk_init(struct device_node *np,
1177 enum exynos5x_soc soc)
780{ 1178{
1179 struct samsung_clk_provider *ctx;
1180
781 if (np) { 1181 if (np) {
782 reg_base = of_iomap(np, 0); 1182 reg_base = of_iomap(np, 0);
783 if (!reg_base) 1183 if (!reg_base)
@@ -786,23 +1186,56 @@ static void __init exynos5420_clk_init(struct device_node *np)
786 panic("%s: unable to determine soc\n", __func__); 1186 panic("%s: unable to determine soc\n", __func__);
787 } 1187 }
788 1188
789 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1189 exynos5x_soc = soc;
790 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 1190
791 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 1191 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1192 if (!ctx)
1193 panic("%s: unable to allocate context.\n", __func__);
1194
1195 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1196 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
792 ext_clk_match); 1197 ext_clk_match);
793 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), 1198 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
794 reg_base); 1199 reg_base);
795 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 1200 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
796 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 1201 ARRAY_SIZE(exynos5x_fixed_rate_clks));
797 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 1202 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
798 ARRAY_SIZE(exynos5420_fixed_factor_clks)); 1203 ARRAY_SIZE(exynos5x_fixed_factor_clks));
799 samsung_clk_register_mux(exynos5420_mux_clks, 1204 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
800 ARRAY_SIZE(exynos5420_mux_clks)); 1205 ARRAY_SIZE(exynos5x_mux_clks));
801 samsung_clk_register_div(exynos5420_div_clks, 1206 samsung_clk_register_div(ctx, exynos5x_div_clks,
802 ARRAY_SIZE(exynos5420_div_clks)); 1207 ARRAY_SIZE(exynos5x_div_clks));
803 samsung_clk_register_gate(exynos5420_gate_clks, 1208 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
804 ARRAY_SIZE(exynos5420_gate_clks)); 1209 ARRAY_SIZE(exynos5x_gate_clks));
1210
1211 if (soc == EXYNOS5420) {
1212 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1213 ARRAY_SIZE(exynos5420_mux_clks));
1214 samsung_clk_register_div(ctx, exynos5420_div_clks,
1215 ARRAY_SIZE(exynos5420_div_clks));
1216 } else {
1217 samsung_clk_register_fixed_factor(
1218 ctx, exynos5800_fixed_factor_clks,
1219 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1220 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1221 ARRAY_SIZE(exynos5800_mux_clks));
1222 samsung_clk_register_div(ctx, exynos5800_div_clks,
1223 ARRAY_SIZE(exynos5800_div_clks));
1224 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1225 ARRAY_SIZE(exynos5800_gate_clks));
1226 }
805 1227
806 exynos5420_clk_sleep_init(); 1228 exynos5420_clk_sleep_init();
807} 1229}
1230
1231static void __init exynos5420_clk_init(struct device_node *np)
1232{
1233 exynos5x_clk_init(np, EXYNOS5420);
1234}
808CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1235CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1236
1237static void __init exynos5800_clk_init(struct device_node *np)
1238{
1239 exynos5x_clk_init(np, EXYNOS5800);
1240}
1241CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 03:22:16 -0500