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path: root/drivers/clk/samsung/clk-exynos5420.c
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-rw-r--r--drivers/clk/samsung/clk-exynos5420.c650
1 files changed, 310 insertions, 340 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 48c4a9350b91..ab4f2f7d88ef 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5420 SoC. 10 * Common Clock Framework support for Exynos5420 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5420.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -107,48 +108,6 @@ enum exynos5420_plls {
107 nr_plls /* number of PLLs */ 108 nr_plls /* number of PLLs */
108}; 109};
109 110
110enum exynos5420_clks {
111 none,
112
113 /* core clocks */
114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
116
117 /* gate for special clocks (sclk) */
118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
119 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
124
125 /* gate clocks */
126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
127 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
128 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
129 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
130 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
131 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
132 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
133 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
134 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
135 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
136 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
137 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
142
143 /* mux clocks */
144 mout_hdmi = 640,
145
146 /* divider clocks */
147 dout_pixel = 768,
148
149 nr_clks,
150};
151
152/* 111/*
153 * list of controller registers to be saved and restored during a 112 * list of controller registers to be saved and restored during a
154 * suspend/resume cycle. 113 * suspend/resume cycle.
@@ -298,225 +257,226 @@ PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
298 257
299/* fixed rate clocks generated outside the soc */ 258/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 259static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
301 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 260 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302}; 261};
303 262
304/* fixed rate clocks generated inside the soc */ 263/* fixed rate clocks generated inside the soc */
305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 264static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
306 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 265 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 266 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 267 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
309 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 268 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
310 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 269 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311}; 270};
312 271
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 272static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
314 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 273 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
315}; 274};
316 275
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 276static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
318 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 277 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
319 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 278 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
320 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), 279 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
321 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 280 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
322 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 281 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
323 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 282 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
324 283
325 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 284 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
326 285
327 MUX_A(none, "mout_aclk400_mscl", group1_p, 286 MUX_A(0, "mout_aclk400_mscl", group1_p,
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 287 SRC_TOP0, 4, 2, "aclk400_mscl"),
329 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 288 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
330 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 289 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
331 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 290 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
332 291
333 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 292 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
334 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 293 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
335 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 294 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
336 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 295 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
337 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 296 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
338 297
339 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 298 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
340 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 299 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
341 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 300 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
342 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 301 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
343 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 302 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
344 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 303 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
345 304
346 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 305 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 306 SRC_TOP3, 4, 1),
348 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p, 307 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 308 SRC_TOP3, 8, 1, "aclk200_disp1"),
350 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 309 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 310 SRC_TOP3, 12, 1),
352 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 311 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 312 SRC_TOP3, 28, 1),
354 313
355 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 314 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 315 SRC_TOP4, 0, 1),
357 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 316 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
358 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 317 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
359 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 318 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
360 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 319 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
361 320
362 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 321 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
363 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 322 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
364 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 323 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
365 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p, 324 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
366 SRC_TOP5, 16, 1, "aclkg3d"), 325 SRC_TOP5, 16, 1, "aclkg3d"),
367 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 326 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 327 SRC_TOP5, 20, 1),
369 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 328 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 329 SRC_TOP5, 24, 1),
371 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 330 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 331 SRC_TOP5, 28, 1),
373 332
374 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 333 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
375 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 334 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
376 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 335 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
377 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 336 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
378 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 337 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
379 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 338 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
380 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 339 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
381 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 340 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
382 341
383 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 342 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
384 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 343 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
385 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 344 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 345 SRC_TOP10, 12, 1),
387 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 346 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
388 347
389 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 348 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 349 SRC_TOP11, 0, 1),
391 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 350 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
392 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 351 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
393 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 352 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
394 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 353 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
395 354
396 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 355 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
397 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 356 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
398 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 357 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
399 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 358 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
400 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 359 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 360 SRC_TOP12, 24, 1),
402 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 361 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
403 362
404 /* DISP1 Block */ 363 /* DISP1 Block */
405 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 364 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
406 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 365 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
407 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 366 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
408 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 367 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
409 MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 368 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
410 369
411 /* MAU Block */ 370 /* MAU Block */
412 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 371 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
413 372
414 /* FSYS Block */ 373 /* FSYS Block */
415 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 374 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
416 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 375 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
417 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 376 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
418 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 377 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
419 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 378 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
420 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 379 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
421 380
422 /* PERIC Block */ 381 /* PERIC Block */
423 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 382 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
424 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 383 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
425 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 384 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
426 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 385 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
427 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 386 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
428 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 387 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
429 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 388 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
430 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 389 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
431 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 390 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
432 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 391 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
433 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 392 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
434 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 393 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
435}; 394};
436 395
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 396static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
438 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 397 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 398 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), 399 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 400 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
442 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 401 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 402
444 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 403 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 404 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 405 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
447 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 406 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 407 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 408
450 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 409 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 410 DIV_TOP1, 0, 3),
452 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 411 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
453 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 412 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 413 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 414 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
456 415
457 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 416 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
458 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 417 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 418 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 419 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", 420 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
462 DIV_TOP2, 24, 3, "aclk300_disp1"), 421 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 422 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 423
465 /* DISP1 Block */ 424 /* DISP1 Block */
466 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 425 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
467 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 426 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 427 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 428 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
470 429
471 /* Audio Block */ 430 /* Audio Block */
472 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 431 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
473 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 432 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
474 433
475 /* USB3.0 */ 434 /* USB3.0 */
476 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 435 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
477 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 436 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
478 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 437 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
479 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 438 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
480 439
481 /* MMC */ 440 /* MMC */
482 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 441 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
483 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 442 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
484 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 443 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 444
486 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 445 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
487 446
488 /* UART and PWM */ 447 /* UART and PWM */
489 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 448 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
490 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 449 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
491 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 450 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
492 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 451 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
493 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 452 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
494 453
495 /* SPI */ 454 /* SPI */
496 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 455 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
497 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 456 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 457 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 458
500 /* PCM */ 459 /* PCM */
501 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 460 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 461 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
503 462
504 /* Audio - I2S */ 463 /* Audio - I2S */
505 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 464 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
506 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 465 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
507 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 466 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
508 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 467 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
509 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 468 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 469
511 /* SPI Pre-Ratio */ 470 /* SPI Pre-Ratio */
512 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 471 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 472 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 473 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
515}; 474};
516 475
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 476static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 477 /* TODO: Re-verify the CG bits for all the gate clocks */
519 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), 478 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
479 "mct"),
520 480
521 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 481 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
522 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 482 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -545,217 +505,227 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
545 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 505 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
546 506
547 /* sclk */ 507 /* sclk */
548 GATE(sclk_uart0, "sclk_uart0", "dout_uart0", 508 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
549 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 509 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_uart1, "sclk_uart1", "dout_uart1", 510 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
551 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 511 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_uart2, "sclk_uart2", "dout_uart2", 512 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
553 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 513 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
554 GATE(sclk_uart3, "sclk_uart3", "dout_uart3", 514 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
555 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 515 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
556 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0", 516 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
557 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 517 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
558 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1", 518 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
559 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 519 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2", 520 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
561 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 521 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
562 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 522 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
563 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 523 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
564 GATE(sclk_pwm, "sclk_pwm", "dout_pwm", 524 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
565 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 525 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1", 526 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
567 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 527 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2", 528 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
569 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 529 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1", 530 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
571 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 531 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2", 532 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
573 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 533 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
574 534
575 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0", 535 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
576 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 536 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
577 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1", 537 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
578 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 538 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
579 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2", 539 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
580 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 540 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
581 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301", 541 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
582 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 542 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
583 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300", 543 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
584 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 544 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
585 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300", 545 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
586 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 546 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
587 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301", 547 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
588 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 548 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
589 549
590 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro", 550 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
591 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 551 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
592 552
593 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl", 553 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
594 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 554 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
595 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl", 555 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
596 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 556 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
597 557
598 /* Display */ 558 /* Display */
599 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1", 559 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
600 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 560 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
601 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1", 561 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
602 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 562 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
603 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 563 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
604 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 564 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
605 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", 565 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
606 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 566 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
607 GATE(sclk_dp1, "sclk_dp1", "dout_dp1", 567 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
608 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 568 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
609 569
610 /* Maudio Block */ 570 /* Maudio Block */
611 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0", 571 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
612 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 572 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
613 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0", 573 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
614 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 574 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
615 /* FSYS */ 575 /* FSYS */
616 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 576 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
617 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 577 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
618 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 578 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
619 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 579 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
620 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 580 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
621 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 581 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
622 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 582 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
623 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 583 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
624 GATE(sromc, "sromc", "aclk200_fsys2", 584 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
625 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 585 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
626 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 586 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
627 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 587 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
628 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 588 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
629 589
630 /* UART */ 590 /* UART */
631 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 591 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
632 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 592 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
633 GATE_A(uart2, "uart2", "aclk66_peric", 593 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
634 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 594 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
635 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 595 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
636 /* I2C */ 596 /* I2C */
637 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 597 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
638 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 598 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
639 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 599 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
640 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 600 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
641 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 601 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
642 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 602 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
643 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 603 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
644 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 604 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
645 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0), 605 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
646 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 606 0),
607 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
647 /* SPI */ 608 /* SPI */
648 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 609 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
649 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 610 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
650 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 611 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
651 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 612 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
652 /* I2S */ 613 /* I2S */
653 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 614 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
654 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 615 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
655 /* PCM */ 616 /* PCM */
656 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 617 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
657 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 618 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
658 /* PWM */ 619 /* PWM */
659 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 620 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
660 /* SPDIF */ 621 /* SPDIF */
661 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 622 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
662 623
663 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 624 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
664 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 625 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
665 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 626 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
666 627
667 GATE(chipid, "chipid", "aclk66_psgen", 628 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
668 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 629 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
669 GATE(sysreg, "sysreg", "aclk66_psgen", 630 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
670 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 631 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
671 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 632 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
672 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 633 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
673 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 634 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
674 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 635 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
675 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 636 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
676 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 637 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
677 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 638 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
678 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 639 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
679 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 640 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
680 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 641 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
681 642
682 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0), 643 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
683 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 644 0),
684 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 645 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
685 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 646 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
686 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 647 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
687 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 648 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
688 649 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
689 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 650
690 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 651 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
691 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 652 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
692 653 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
693 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0), 654
694 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl", 655 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
656 0),
657 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
695 GATE_IP_GSCL1, 3, 0, 0), 658 GATE_IP_GSCL1, 3, 0, 0),
696 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl", 659 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
697 GATE_IP_GSCL1, 4, 0, 0), 660 GATE_IP_GSCL1, 4, 0, 0),
698 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0), 661 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
699 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0), 662 0),
700 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 663 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
701 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 664 0),
702 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl", 665 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
703 GATE_IP_GSCL1, 16, 0, 0), 668 GATE_IP_GSCL1, 16, 0, 0),
704 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl", 669 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
705 GATE_IP_GSCL1, 17, 0, 0), 670 GATE_IP_GSCL1, 17, 0, 0),
706 671
707 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 672 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
708 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 673 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
709 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 674 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
710 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 675 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
711 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 676 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
712 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), 677 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
713 678 0),
714 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 679
715 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 680 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
716 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 681 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
717 682 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
718 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 683
719 684 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
720 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 685
721 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 686 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
722 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 687 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
723 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 688 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
724 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 689 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
725 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 690 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
726 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 691 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
727 692 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
728 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 693
729 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 694 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
730 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 695 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
731 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), 696 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
732 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), 697 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
733 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), 698 0),
734 GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), 699 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
700 0),
701 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
702 0),
703 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
704 0),
735}; 705};
736 706
737static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 707static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
738 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 708 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
739 APLL_CON0, NULL), 709 APLL_CON0, NULL),
740 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 710 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
741 MPLL_CON0, NULL), 711 CPLL_CON0, NULL),
742 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, 712 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
743 DPLL_CON0, NULL), 713 DPLL_CON0, NULL),
744 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 714 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
745 EPLL_CON0, NULL), 715 EPLL_CON0, NULL),
746 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK, 716 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
747 RPLL_CON0, NULL), 717 RPLL_CON0, NULL),
748 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK, 718 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
749 IPLL_CON0, NULL), 719 IPLL_CON0, NULL),
750 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK, 720 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
751 SPLL_CON0, NULL), 721 SPLL_CON0, NULL),
752 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, 722 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
753 VPLL_CON0, NULL), 723 VPLL_CON0, NULL),
754 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 724 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
755 MPLL_CON0, NULL), 725 MPLL_CON0, NULL),
756 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 726 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
757 BPLL_CON0, NULL), 727 BPLL_CON0, NULL),
758 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK, 728 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
759 KPLL_CON0, NULL), 729 KPLL_CON0, NULL),
760}; 730};
761 731
@@ -777,7 +747,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
777 panic("%s: unable to determine soc\n", __func__); 747 panic("%s: unable to determine soc\n", __func__);
778 } 748 }
779 749
780 samsung_clk_init(np, reg_base, nr_clks, 750 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
781 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), 751 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
782 NULL, 0); 752 NULL, 0);
783 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 753 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 17:06:29 -0500