1 files changed, 42 insertions, 0 deletions

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 870e18b9a687..1fad4c5e3f5d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -24,6 +24,8 @@
 #define APLL_CON0               0x100
 #define SRC_CPU                 0x200
 #define DIV_CPU0                0x500
+#define PWR_CTRL1               0x1020
+#define PWR_CTRL2               0x1024
 #define MPLL_LOCK               0x4000
 #define MPLL_CON0               0x4100
 #define SRC_CORE1               0x4204
@@ -84,6 +86,23 @@
 #define SRC_CDREX               0x20200
 #define PLL_DIV2_SEL            0x20a24
 
+/*Below definitions are used for PWR_CTRL settings*/
+#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
+
 /* list of PLLs to be registered */
 enum exynos5250_plls {
         apll, mpll, cpll, epll, vpll, gpll, bpll,
@@ -102,6 +121,8 @@ static struct samsung_clk_reg_dump *exynos5250_save;
 static unsigned long exynos5250_clk_regs[] __initdata = {
         SRC_CPU,
         DIV_CPU0,
+        PWR_CTRL1,
+        PWR_CTRL2,
         SRC_CORE1,
         SRC_TOP0,
         SRC_TOP1,
@@ -736,6 +757,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
 static void __init exynos5250_clk_init(struct device_node *np)
 {
         struct samsung_clk_provider *ctx;
+        unsigned int tmp;
 
         if (np) {
                 reg_base = of_iomap(np, 0);
@@ -776,6 +798,26 @@ static void __init exynos5250_clk_init(struct device_node *np)
         samsung_clk_register_gate(ctx, exynos5250_gate_clks,
                         ARRAY_SIZE(exynos5250_gate_clks));
 
+        /*
+         * Enable arm clock down (in idle) and set arm divider
+         * ratios in WFI/WFE state.
+         */
+        tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
+                PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
+                PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
+                PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
+        __raw_writel(tmp, reg_base + PWR_CTRL1);
+
+        /*
+         * Enable arm clock up (on exiting idle). Set arm divider
+         * ratios when not in idle along with the standby duration
+         * ratios.
+         */
+        tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
+                PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
+                PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
+        __raw_writel(tmp, reg_base + PWR_CTRL2);
+
         exynos5250_clk_sleep_init();
 
         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",