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-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c2625
1 files changed, 2625 insertions, 0 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
new file mode 100644
index 000000000000..c95774514b81
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -0,0 +1,2625 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
26#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define P_XO 0
35#define P_MMPLL0 1
36#define P_EDPLINK 1
37#define P_MMPLL1 2
38#define P_HDMIPLL 2
39#define P_GPLL0 3
40#define P_EDPVCO 3
41#define P_GPLL1 4
42#define P_DSI0PLL 4
43#define P_MMPLL2 4
44#define P_MMPLL3 4
45#define P_DSI1PLL 5
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
112 [P_XO] = 0,
113 [P_MMPLL0] = 1,
114 [P_MMPLL1] = 2,
115 [P_GPLL0] = 5,
116 [P_GPLL1] = 4,
117};
118
119static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
120 "xo",
121 "mmpll0_vote",
122 "mmpll1_vote",
123 "mmss_gpll0_vote",
124 "gpll1_vote",
125};
126
127static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
128 [P_XO] = 0,
129 [P_EDPLINK] = 4,
130 [P_HDMIPLL] = 3,
131 [P_EDPVCO] = 5,
132 [P_DSI0PLL] = 1,
133 [P_DSI1PLL] = 2,
134};
135
136static const char *mmcc_xo_dsi_hdmi_edp[] = {
137 "xo",
138 "edp_link_clk",
139 "hdmipll",
140 "edp_vco_div",
141 "dsi0pll",
142 "dsi1pll",
143};
144
145static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
146 [P_XO] = 0,
147 [P_EDPLINK] = 4,
148 [P_HDMIPLL] = 3,
149 [P_GPLL0] = 5,
150 [P_DSI0PLL] = 1,
151 [P_DSI1PLL] = 2,
152};
153
154static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
155 "xo",
156 "edp_link_clk",
157 "hdmipll",
158 "gpll0_vote",
159 "dsi0pll",
160 "dsi1pll",
161};
162
163#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
164
165static struct clk_pll mmpll0 = {
166 .l_reg = 0x0004,
167 .m_reg = 0x0008,
168 .n_reg = 0x000c,
169 .config_reg = 0x0014,
170 .mode_reg = 0x0000,
171 .status_reg = 0x001c,
172 .clkr.hw.init = &(struct clk_init_data){
173 .name = "mmpll0",
174 .parent_names = (const char *[]){ "xo" },
175 .num_parents = 1,
176 .ops = &clk_pll_ops,
177 },
178};
179
180static struct clk_regmap mmpll0_vote = {
181 .enable_reg = 0x0100,
182 .enable_mask = BIT(0),
183 .hw.init = &(struct clk_init_data){
184 .name = "mmpll0_vote",
185 .parent_names = (const char *[]){ "mmpll0" },
186 .num_parents = 1,
187 .ops = &clk_pll_vote_ops,
188 },
189};
190
191static struct clk_pll mmpll1 = {
192 .l_reg = 0x0044,
193 .m_reg = 0x0048,
194 .n_reg = 0x004c,
195 .config_reg = 0x0054,
196 .mode_reg = 0x0040,
197 .status_reg = 0x005c,
198 .clkr.hw.init = &(struct clk_init_data){
199 .name = "mmpll1",
200 .parent_names = (const char *[]){ "xo" },
201 .num_parents = 1,
202 .ops = &clk_pll_ops,
203 },
204};
205
206static struct clk_regmap mmpll1_vote = {
207 .enable_reg = 0x0100,
208 .enable_mask = BIT(1),
209 .hw.init = &(struct clk_init_data){
210 .name = "mmpll1_vote",
211 .parent_names = (const char *[]){ "mmpll1" },
212 .num_parents = 1,
213 .ops = &clk_pll_vote_ops,
214 },
215};
216
217static struct clk_pll mmpll2 = {
218 .l_reg = 0x4104,
219 .m_reg = 0x4108,
220 .n_reg = 0x410c,
221 .config_reg = 0x4114,
222 .mode_reg = 0x4100,
223 .status_reg = 0x411c,
224 .clkr.hw.init = &(struct clk_init_data){
225 .name = "mmpll2",
226 .parent_names = (const char *[]){ "xo" },
227 .num_parents = 1,
228 .ops = &clk_pll_ops,
229 },
230};
231
232static struct clk_pll mmpll3 = {
233 .l_reg = 0x0084,
234 .m_reg = 0x0088,
235 .n_reg = 0x008c,
236 .config_reg = 0x0094,
237 .mode_reg = 0x0080,
238 .status_reg = 0x009c,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "mmpll3",
241 .parent_names = (const char *[]){ "xo" },
242 .num_parents = 1,
243 .ops = &clk_pll_ops,
244 },
245};
246
247static struct clk_rcg2 mmss_ahb_clk_src = {
248 .cmd_rcgr = 0x5000,
249 .hid_width = 5,
250 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "mmss_ahb_clk_src",
253 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
254 .num_parents = 4,
255 .ops = &clk_rcg2_ops,
256 },
257};
258
259static struct freq_tbl ftbl_mmss_axi_clk[] = {
260 F( 19200000, P_XO, 1, 0, 0),
261 F( 37500000, P_GPLL0, 16, 0, 0),
262 F( 50000000, P_GPLL0, 12, 0, 0),
263 F( 75000000, P_GPLL0, 8, 0, 0),
264 F(100000000, P_GPLL0, 6, 0, 0),
265 F(150000000, P_GPLL0, 4, 0, 0),
266 F(291750000, P_MMPLL1, 4, 0, 0),
267 F(400000000, P_MMPLL0, 2, 0, 0),
268 F(466800000, P_MMPLL1, 2.5, 0, 0),
269};
270
271static struct clk_rcg2 mmss_axi_clk_src = {
272 .cmd_rcgr = 0x5040,
273 .hid_width = 5,
274 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
275 .freq_tbl = ftbl_mmss_axi_clk,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "mmss_axi_clk_src",
278 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
279 .num_parents = 4,
280 .ops = &clk_rcg2_ops,
281 },
282};
283
284static struct freq_tbl ftbl_ocmemnoc_clk[] = {
285 F( 19200000, P_XO, 1, 0, 0),
286 F( 37500000, P_GPLL0, 16, 0, 0),
287 F( 50000000, P_GPLL0, 12, 0, 0),
288 F( 75000000, P_GPLL0, 8, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(291750000, P_MMPLL1, 4, 0, 0),
292 F(400000000, P_MMPLL0, 2, 0, 0),
293};
294
295static struct clk_rcg2 ocmemnoc_clk_src = {
296 .cmd_rcgr = 0x5090,
297 .hid_width = 5,
298 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
299 .freq_tbl = ftbl_ocmemnoc_clk,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "ocmemnoc_clk_src",
302 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
303 .num_parents = 4,
304 .ops = &clk_rcg2_ops,
305 },
306};
307
308static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
309 F(100000000, P_GPLL0, 6, 0, 0),
310 F(200000000, P_MMPLL0, 4, 0, 0),
311 { }
312};
313
314static struct clk_rcg2 csi0_clk_src = {
315 .cmd_rcgr = 0x3090,
316 .hid_width = 5,
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .freq_tbl = ftbl_camss_csi0_3_clk,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "csi0_clk_src",
321 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
322 .num_parents = 4,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static struct clk_rcg2 csi1_clk_src = {
328 .cmd_rcgr = 0x3100,
329 .hid_width = 5,
330 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
331 .freq_tbl = ftbl_camss_csi0_3_clk,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "csi1_clk_src",
334 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
335 .num_parents = 4,
336 .ops = &clk_rcg2_ops,
337 },
338};
339
340static struct clk_rcg2 csi2_clk_src = {
341 .cmd_rcgr = 0x3160,
342 .hid_width = 5,
343 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
344 .freq_tbl = ftbl_camss_csi0_3_clk,
345 .clkr.hw.init = &(struct clk_init_data){
346 .name = "csi2_clk_src",
347 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
348 .num_parents = 4,
349 .ops = &clk_rcg2_ops,
350 },
351};
352
353static struct clk_rcg2 csi3_clk_src = {
354 .cmd_rcgr = 0x31c0,
355 .hid_width = 5,
356 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
357 .freq_tbl = ftbl_camss_csi0_3_clk,
358 .clkr.hw.init = &(struct clk_init_data){
359 .name = "csi3_clk_src",
360 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
361 .num_parents = 4,
362 .ops = &clk_rcg2_ops,
363 },
364};
365
366static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
367 F(37500000, P_GPLL0, 16, 0, 0),
368 F(50000000, P_GPLL0, 12, 0, 0),
369 F(60000000, P_GPLL0, 10, 0, 0),
370 F(80000000, P_GPLL0, 7.5, 0, 0),
371 F(100000000, P_GPLL0, 6, 0, 0),
372 F(109090000, P_GPLL0, 5.5, 0, 0),
373 F(133330000, P_GPLL0, 4.5, 0, 0),
374 F(200000000, P_GPLL0, 3, 0, 0),
375 F(228570000, P_MMPLL0, 3.5, 0, 0),
376 F(266670000, P_MMPLL0, 3, 0, 0),
377 F(320000000, P_MMPLL0, 2.5, 0, 0),
378 F(400000000, P_MMPLL0, 2, 0, 0),
379 F(465000000, P_MMPLL3, 2, 0, 0),
380 { }
381};
382
383static struct clk_rcg2 vfe0_clk_src = {
384 .cmd_rcgr = 0x3600,
385 .hid_width = 5,
386 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
387 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
388 .clkr.hw.init = &(struct clk_init_data){
389 .name = "vfe0_clk_src",
390 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
391 .num_parents = 4,
392 .ops = &clk_rcg2_ops,
393 },
394};
395
396static struct clk_rcg2 vfe1_clk_src = {
397 .cmd_rcgr = 0x3620,
398 .hid_width = 5,
399 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
400 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
401 .clkr.hw.init = &(struct clk_init_data){
402 .name = "vfe1_clk_src",
403 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
404 .num_parents = 4,
405 .ops = &clk_rcg2_ops,
406 },
407};
408
409static struct freq_tbl ftbl_mdss_mdp_clk[] = {
410 F(37500000, P_GPLL0, 16, 0, 0),
411 F(60000000, P_GPLL0, 10, 0, 0),
412 F(75000000, P_GPLL0, 8, 0, 0),
413 F(85710000, P_GPLL0, 7, 0, 0),
414 F(100000000, P_GPLL0, 6, 0, 0),
415 F(133330000, P_MMPLL0, 6, 0, 0),
416 F(160000000, P_MMPLL0, 5, 0, 0),
417 F(200000000, P_MMPLL0, 4, 0, 0),
418 F(228570000, P_MMPLL0, 3.5, 0, 0),
419 F(240000000, P_GPLL0, 2.5, 0, 0),
420 F(266670000, P_MMPLL0, 3, 0, 0),
421 F(320000000, P_MMPLL0, 2.5, 0, 0),
422 { }
423};
424
425static struct clk_rcg2 mdp_clk_src = {
426 .cmd_rcgr = 0x2040,
427 .hid_width = 5,
428 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
429 .freq_tbl = ftbl_mdss_mdp_clk,
430 .clkr.hw.init = &(struct clk_init_data){
431 .name = "mdp_clk_src",
432 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
433 .num_parents = 6,
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 gfx3d_clk_src = {
439 .cmd_rcgr = 0x4000,
440 .hid_width = 5,
441 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
442 .clkr.hw.init = &(struct clk_init_data){
443 .name = "gfx3d_clk_src",
444 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
445 .num_parents = 5,
446 .ops = &clk_rcg2_ops,
447 },
448};
449
450static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
451 F(75000000, P_GPLL0, 8, 0, 0),
452 F(133330000, P_GPLL0, 4.5, 0, 0),
453 F(200000000, P_GPLL0, 3, 0, 0),
454 F(228570000, P_MMPLL0, 3.5, 0, 0),
455 F(266670000, P_MMPLL0, 3, 0, 0),
456 F(320000000, P_MMPLL0, 2.5, 0, 0),
457 { }
458};
459
460static struct clk_rcg2 jpeg0_clk_src = {
461 .cmd_rcgr = 0x3500,
462 .hid_width = 5,
463 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
464 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
465 .clkr.hw.init = &(struct clk_init_data){
466 .name = "jpeg0_clk_src",
467 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
468 .num_parents = 4,
469 .ops = &clk_rcg2_ops,
470 },
471};
472
473static struct clk_rcg2 jpeg1_clk_src = {
474 .cmd_rcgr = 0x3520,
475 .hid_width = 5,
476 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
477 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "jpeg1_clk_src",
480 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
481 .num_parents = 4,
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct clk_rcg2 jpeg2_clk_src = {
487 .cmd_rcgr = 0x3540,
488 .hid_width = 5,
489 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
490 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "jpeg2_clk_src",
493 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
494 .num_parents = 4,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
500 F(125000000, P_DSI0PLL, 2, 0, 0),
501 F(250000000, P_DSI0PLL, 1, 0, 0),
502 { }
503};
504
505static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
506 F(125000000, P_DSI1PLL, 2, 0, 0),
507 F(250000000, P_DSI1PLL, 1, 0, 0),
508 { }
509};
510
511static struct clk_rcg2 pclk0_clk_src = {
512 .cmd_rcgr = 0x2000,
513 .mnd_width = 8,
514 .hid_width = 5,
515 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
516 .freq_tbl = ftbl_mdss_pclk0_clk,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "pclk0_clk_src",
519 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
520 .num_parents = 6,
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct clk_rcg2 pclk1_clk_src = {
526 .cmd_rcgr = 0x2020,
527 .mnd_width = 8,
528 .hid_width = 5,
529 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
530 .freq_tbl = ftbl_mdss_pclk1_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "pclk1_clk_src",
533 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
534 .num_parents = 6,
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
540 F(50000000, P_GPLL0, 12, 0, 0),
541 F(100000000, P_GPLL0, 6, 0, 0),
542 F(133330000, P_MMPLL0, 6, 0, 0),
543 F(200000000, P_MMPLL0, 4, 0, 0),
544 F(266670000, P_MMPLL0, 3, 0, 0),
545 F(465000000, P_MMPLL3, 2, 0, 0),
546 { }
547};
548
549static struct clk_rcg2 vcodec0_clk_src = {
550 .cmd_rcgr = 0x1000,
551 .mnd_width = 8,
552 .hid_width = 5,
553 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
554 .freq_tbl = ftbl_venus0_vcodec0_clk,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "vcodec0_clk_src",
557 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
558 .num_parents = 5,
559 .ops = &clk_rcg2_ops,
560 },
561};
562
563static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
564 F(19200000, P_XO, 1, 0, 0),
565 { }
566};
567
568static struct clk_rcg2 cci_clk_src = {
569 .cmd_rcgr = 0x3300,
570 .hid_width = 5,
571 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
572 .freq_tbl = ftbl_camss_cci_cci_clk,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "cci_clk_src",
575 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
576 .num_parents = 4,
577 .ops = &clk_rcg2_ops,
578 },
579};
580
581static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
582 F(10000, P_XO, 16, 1, 120),
583 F(24000, P_XO, 16, 1, 50),
584 F(6000000, P_GPLL0, 10, 1, 10),
585 F(12000000, P_GPLL0, 10, 1, 5),
586 F(13000000, P_GPLL0, 4, 13, 150),
587 F(24000000, P_GPLL0, 5, 1, 5),
588 { }
589};
590
591static struct clk_rcg2 camss_gp0_clk_src = {
592 .cmd_rcgr = 0x3420,
593 .mnd_width = 8,
594 .hid_width = 5,
595 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
596 .freq_tbl = ftbl_camss_gp0_1_clk,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "camss_gp0_clk_src",
599 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
600 .num_parents = 5,
601 .ops = &clk_rcg2_ops,
602 },
603};
604
605static struct clk_rcg2 camss_gp1_clk_src = {
606 .cmd_rcgr = 0x3450,
607 .mnd_width = 8,
608 .hid_width = 5,
609 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
610 .freq_tbl = ftbl_camss_gp0_1_clk,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "camss_gp1_clk_src",
613 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
614 .num_parents = 5,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
620 F(4800000, P_XO, 4, 0, 0),
621 F(6000000, P_GPLL0, 10, 1, 10),
622 F(8000000, P_GPLL0, 15, 1, 5),
623 F(9600000, P_XO, 2, 0, 0),
624 F(16000000, P_GPLL0, 12.5, 1, 3),
625 F(19200000, P_XO, 1, 0, 0),
626 F(24000000, P_GPLL0, 5, 1, 5),
627 F(32000000, P_MMPLL0, 5, 1, 5),
628 F(48000000, P_GPLL0, 12.5, 0, 0),
629 F(64000000, P_MMPLL0, 12.5, 0, 0),
630 F(66670000, P_GPLL0, 9, 0, 0),
631 { }
632};
633
634static struct clk_rcg2 mclk0_clk_src = {
635 .cmd_rcgr = 0x3360,
636 .hid_width = 5,
637 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
638 .freq_tbl = ftbl_camss_mclk0_3_clk,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "mclk0_clk_src",
641 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
642 .num_parents = 4,
643 .ops = &clk_rcg2_ops,
644 },
645};
646
647static struct clk_rcg2 mclk1_clk_src = {
648 .cmd_rcgr = 0x3390,
649 .hid_width = 5,
650 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
651 .freq_tbl = ftbl_camss_mclk0_3_clk,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "mclk1_clk_src",
654 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
655 .num_parents = 4,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static struct clk_rcg2 mclk2_clk_src = {
661 .cmd_rcgr = 0x33c0,
662 .hid_width = 5,
663 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
664 .freq_tbl = ftbl_camss_mclk0_3_clk,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "mclk2_clk_src",
667 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
668 .num_parents = 4,
669 .ops = &clk_rcg2_ops,
670 },
671};
672
673static struct clk_rcg2 mclk3_clk_src = {
674 .cmd_rcgr = 0x33f0,
675 .hid_width = 5,
676 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
677 .freq_tbl = ftbl_camss_mclk0_3_clk,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "mclk3_clk_src",
680 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
681 .num_parents = 4,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
687 F(100000000, P_GPLL0, 6, 0, 0),
688 F(200000000, P_MMPLL0, 4, 0, 0),
689 { }
690};
691
692static struct clk_rcg2 csi0phytimer_clk_src = {
693 .cmd_rcgr = 0x3000,
694 .hid_width = 5,
695 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
696 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "csi0phytimer_clk_src",
699 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
700 .num_parents = 4,
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 csi1phytimer_clk_src = {
706 .cmd_rcgr = 0x3030,
707 .hid_width = 5,
708 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
709 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "csi1phytimer_clk_src",
712 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
713 .num_parents = 4,
714 .ops = &clk_rcg2_ops,
715 },
716};
717
718static struct clk_rcg2 csi2phytimer_clk_src = {
719 .cmd_rcgr = 0x3060,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
722 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "csi2phytimer_clk_src",
725 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
726 .num_parents = 4,
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
732 F(133330000, P_GPLL0, 4.5, 0, 0),
733 F(266670000, P_MMPLL0, 3, 0, 0),
734 F(320000000, P_MMPLL0, 2.5, 0, 0),
735 F(400000000, P_MMPLL0, 2, 0, 0),
736 F(465000000, P_MMPLL3, 2, 0, 0),
737 { }
738};
739
740static struct clk_rcg2 cpp_clk_src = {
741 .cmd_rcgr = 0x3640,
742 .hid_width = 5,
743 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
744 .freq_tbl = ftbl_camss_vfe_cpp_clk,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "cpp_clk_src",
747 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
748 .num_parents = 4,
749 .ops = &clk_rcg2_ops,
750 },
751};
752
753static struct freq_tbl ftbl_mdss_byte0_clk[] = {
754 F(93750000, P_DSI0PLL, 8, 0, 0),
755 F(187500000, P_DSI0PLL, 4, 0, 0),
756 { }
757};
758
759static struct freq_tbl ftbl_mdss_byte1_clk[] = {
760 F(93750000, P_DSI1PLL, 8, 0, 0),
761 F(187500000, P_DSI1PLL, 4, 0, 0),
762 { }
763};
764
765static struct clk_rcg2 byte0_clk_src = {
766 .cmd_rcgr = 0x2120,
767 .hid_width = 5,
768 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
769 .freq_tbl = ftbl_mdss_byte0_clk,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "byte0_clk_src",
772 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
773 .num_parents = 6,
774 .ops = &clk_rcg2_ops,
775 },
776};
777
778static struct clk_rcg2 byte1_clk_src = {
779 .cmd_rcgr = 0x2140,
780 .hid_width = 5,
781 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
782 .freq_tbl = ftbl_mdss_byte1_clk,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "byte1_clk_src",
785 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
786 .num_parents = 6,
787 .ops = &clk_rcg2_ops,
788 },
789};
790
791static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
792 F(19200000, P_XO, 1, 0, 0),
793 { }
794};
795
796static struct clk_rcg2 edpaux_clk_src = {
797 .cmd_rcgr = 0x20e0,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
800 .freq_tbl = ftbl_mdss_edpaux_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "edpaux_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct freq_tbl ftbl_mdss_edplink_clk[] = {
810 F(135000000, P_EDPLINK, 2, 0, 0),
811 F(270000000, P_EDPLINK, 11, 0, 0),
812 { }
813};
814
815static struct clk_rcg2 edplink_clk_src = {
816 .cmd_rcgr = 0x20c0,
817 .hid_width = 5,
818 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
819 .freq_tbl = ftbl_mdss_edplink_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "edplink_clk_src",
822 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
823 .num_parents = 6,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
829 F(175000000, P_EDPVCO, 2, 0, 0),
830 F(350000000, P_EDPVCO, 11, 0, 0),
831 { }
832};
833
834static struct clk_rcg2 edppixel_clk_src = {
835 .cmd_rcgr = 0x20a0,
836 .mnd_width = 8,
837 .hid_width = 5,
838 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
839 .freq_tbl = ftbl_mdss_edppixel_clk,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "edppixel_clk_src",
842 .parent_names = mmcc_xo_dsi_hdmi_edp,
843 .num_parents = 6,
844 .ops = &clk_rcg2_ops,
845 },
846};
847
848static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
849 F(19200000, P_XO, 1, 0, 0),
850 { }
851};
852
853static struct clk_rcg2 esc0_clk_src = {
854 .cmd_rcgr = 0x2160,
855 .hid_width = 5,
856 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
857 .freq_tbl = ftbl_mdss_esc0_1_clk,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "esc0_clk_src",
860 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
861 .num_parents = 6,
862 .ops = &clk_rcg2_ops,
863 },
864};
865
866static struct clk_rcg2 esc1_clk_src = {
867 .cmd_rcgr = 0x2180,
868 .hid_width = 5,
869 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
870 .freq_tbl = ftbl_mdss_esc0_1_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "esc1_clk_src",
873 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
874 .num_parents = 6,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
880 F(25200000, P_HDMIPLL, 1, 0, 0),
881 F(27000000, P_HDMIPLL, 1, 0, 0),
882 F(27030000, P_HDMIPLL, 1, 0, 0),
883 F(65000000, P_HDMIPLL, 1, 0, 0),
884 F(74250000, P_HDMIPLL, 1, 0, 0),
885 F(108000000, P_HDMIPLL, 1, 0, 0),
886 F(148500000, P_HDMIPLL, 1, 0, 0),
887 F(268500000, P_HDMIPLL, 1, 0, 0),
888 F(297000000, P_HDMIPLL, 1, 0, 0),
889 { }
890};
891
892static struct clk_rcg2 extpclk_clk_src = {
893 .cmd_rcgr = 0x2060,
894 .hid_width = 5,
895 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
896 .freq_tbl = ftbl_mdss_extpclk_clk,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "extpclk_clk_src",
899 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
900 .num_parents = 6,
901 .ops = &clk_rcg2_ops,
902 },
903};
904
905static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
906 F(19200000, P_XO, 1, 0, 0),
907 { }
908};
909
910static struct clk_rcg2 hdmi_clk_src = {
911 .cmd_rcgr = 0x2100,
912 .hid_width = 5,
913 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
914 .freq_tbl = ftbl_mdss_hdmi_clk,
915 .clkr.hw.init = &(struct clk_init_data){
916 .name = "hdmi_clk_src",
917 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
918 .num_parents = 4,
919 .ops = &clk_rcg2_ops,
920 },
921};
922
923static struct freq_tbl ftbl_mdss_vsync_clk[] = {
924 F(19200000, P_XO, 1, 0, 0),
925 { }
926};
927
928static struct clk_rcg2 vsync_clk_src = {
929 .cmd_rcgr = 0x2080,
930 .hid_width = 5,
931 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
932 .freq_tbl = ftbl_mdss_vsync_clk,
933 .clkr.hw.init = &(struct clk_init_data){
934 .name = "vsync_clk_src",
935 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
936 .num_parents = 4,
937 .ops = &clk_rcg2_ops,
938 },
939};
940
941static struct clk_branch camss_cci_cci_ahb_clk = {
942 .halt_reg = 0x3348,
943 .clkr = {
944 .enable_reg = 0x3348,
945 .enable_mask = BIT(0),
946 .hw.init = &(struct clk_init_data){
947 .name = "camss_cci_cci_ahb_clk",
948 .parent_names = (const char *[]){
949 "mmss_ahb_clk_src",
950 },
951 .num_parents = 1,
952 .ops = &clk_branch2_ops,
953 },
954 },
955};
956
957static struct clk_branch camss_cci_cci_clk = {
958 .halt_reg = 0x3344,
959 .clkr = {
960 .enable_reg = 0x3344,
961 .enable_mask = BIT(0),
962 .hw.init = &(struct clk_init_data){
963 .name = "camss_cci_cci_clk",
964 .parent_names = (const char *[]){
965 "cci_clk_src",
966 },
967 .num_parents = 1,
968 .flags = CLK_SET_RATE_PARENT,
969 .ops = &clk_branch2_ops,
970 },
971 },
972};
973
974static struct clk_branch camss_csi0_ahb_clk = {
975 .halt_reg = 0x30bc,
976 .clkr = {
977 .enable_reg = 0x30bc,
978 .enable_mask = BIT(0),
979 .hw.init = &(struct clk_init_data){
980 .name = "camss_csi0_ahb_clk",
981 .parent_names = (const char *[]){
982 "mmss_ahb_clk_src",
983 },
984 .num_parents = 1,
985 .ops = &clk_branch2_ops,
986 },
987 },
988};
989
990static struct clk_branch camss_csi0_clk = {
991 .halt_reg = 0x30b4,
992 .clkr = {
993 .enable_reg = 0x30b4,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "camss_csi0_clk",
997 .parent_names = (const char *[]){
998 "csi0_clk_src",
999 },
1000 .num_parents = 1,
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1003 },
1004 },
1005};
1006
1007static struct clk_branch camss_csi0phy_clk = {
1008 .halt_reg = 0x30c4,
1009 .clkr = {
1010 .enable_reg = 0x30c4,
1011 .enable_mask = BIT(0),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "camss_csi0phy_clk",
1014 .parent_names = (const char *[]){
1015 "csi0_clk_src",
1016 },
1017 .num_parents = 1,
1018 .flags = CLK_SET_RATE_PARENT,
1019 .ops = &clk_branch2_ops,
1020 },
1021 },
1022};
1023
1024static struct clk_branch camss_csi0pix_clk = {
1025 .halt_reg = 0x30e4,
1026 .clkr = {
1027 .enable_reg = 0x30e4,
1028 .enable_mask = BIT(0),
1029 .hw.init = &(struct clk_init_data){
1030 .name = "camss_csi0pix_clk",
1031 .parent_names = (const char *[]){
1032 "csi0_clk_src",
1033 },
1034 .num_parents = 1,
1035 .flags = CLK_SET_RATE_PARENT,
1036 .ops = &clk_branch2_ops,
1037 },
1038 },
1039};
1040
1041static struct clk_branch camss_csi0rdi_clk = {
1042 .halt_reg = 0x30d4,
1043 .clkr = {
1044 .enable_reg = 0x30d4,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "camss_csi0rdi_clk",
1048 .parent_names = (const char *[]){
1049 "csi0_clk_src",
1050 },
1051 .num_parents = 1,
1052 .flags = CLK_SET_RATE_PARENT,
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056};
1057
1058static struct clk_branch camss_csi1_ahb_clk = {
1059 .halt_reg = 0x3128,
1060 .clkr = {
1061 .enable_reg = 0x3128,
1062 .enable_mask = BIT(0),
1063 .hw.init = &(struct clk_init_data){
1064 .name = "camss_csi1_ahb_clk",
1065 .parent_names = (const char *[]){
1066 "mmss_ahb_clk_src",
1067 },
1068 .num_parents = 1,
1069 .ops = &clk_branch2_ops,
1070 },
1071 },
1072};
1073
1074static struct clk_branch camss_csi1_clk = {
1075 .halt_reg = 0x3124,
1076 .clkr = {
1077 .enable_reg = 0x3124,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(struct clk_init_data){
1080 .name = "camss_csi1_clk",
1081 .parent_names = (const char *[]){
1082 "csi1_clk_src",
1083 },
1084 .num_parents = 1,
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_branch2_ops,
1087 },
1088 },
1089};
1090
1091static struct clk_branch camss_csi1phy_clk = {
1092 .halt_reg = 0x3134,
1093 .clkr = {
1094 .enable_reg = 0x3134,
1095 .enable_mask = BIT(0),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "camss_csi1phy_clk",
1098 .parent_names = (const char *[]){
1099 "csi1_clk_src",
1100 },
1101 .num_parents = 1,
1102 .flags = CLK_SET_RATE_PARENT,
1103 .ops = &clk_branch2_ops,
1104 },
1105 },
1106};
1107
1108static struct clk_branch camss_csi1pix_clk = {
1109 .halt_reg = 0x3154,
1110 .clkr = {
1111 .enable_reg = 0x3154,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "camss_csi1pix_clk",
1115 .parent_names = (const char *[]){
1116 "csi1_clk_src",
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123};
1124
1125static struct clk_branch camss_csi1rdi_clk = {
1126 .halt_reg = 0x3144,
1127 .clkr = {
1128 .enable_reg = 0x3144,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "camss_csi1rdi_clk",
1132 .parent_names = (const char *[]){
1133 "csi1_clk_src",
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140};
1141
1142static struct clk_branch camss_csi2_ahb_clk = {
1143 .halt_reg = 0x3188,
1144 .clkr = {
1145 .enable_reg = 0x3188,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "camss_csi2_ahb_clk",
1149 .parent_names = (const char *[]){
1150 "mmss_ahb_clk_src",
1151 },
1152 .num_parents = 1,
1153 .ops = &clk_branch2_ops,
1154 },
1155 },
1156};
1157
1158static struct clk_branch camss_csi2_clk = {
1159 .halt_reg = 0x3184,
1160 .clkr = {
1161 .enable_reg = 0x3184,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "camss_csi2_clk",
1165 .parent_names = (const char *[]){
1166 "csi2_clk_src",
1167 },
1168 .num_parents = 1,
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1171 },
1172 },
1173};
1174
1175static struct clk_branch camss_csi2phy_clk = {
1176 .halt_reg = 0x3194,
1177 .clkr = {
1178 .enable_reg = 0x3194,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "camss_csi2phy_clk",
1182 .parent_names = (const char *[]){
1183 "csi2_clk_src",
1184 },
1185 .num_parents = 1,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1188 },
1189 },
1190};
1191
1192static struct clk_branch camss_csi2pix_clk = {
1193 .halt_reg = 0x31b4,
1194 .clkr = {
1195 .enable_reg = 0x31b4,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "camss_csi2pix_clk",
1199 .parent_names = (const char *[]){
1200 "csi2_clk_src",
1201 },
1202 .num_parents = 1,
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207};
1208
1209static struct clk_branch camss_csi2rdi_clk = {
1210 .halt_reg = 0x31a4,
1211 .clkr = {
1212 .enable_reg = 0x31a4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_csi2rdi_clk",
1216 .parent_names = (const char *[]){
1217 "csi2_clk_src",
1218 },
1219 .num_parents = 1,
1220 .flags = CLK_SET_RATE_PARENT,
1221 .ops = &clk_branch2_ops,
1222 },
1223 },
1224};
1225
1226static struct clk_branch camss_csi3_ahb_clk = {
1227 .halt_reg = 0x31e8,
1228 .clkr = {
1229 .enable_reg = 0x31e8,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "camss_csi3_ahb_clk",
1233 .parent_names = (const char *[]){
1234 "mmss_ahb_clk_src",
1235 },
1236 .num_parents = 1,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch camss_csi3_clk = {
1243 .halt_reg = 0x31e4,
1244 .clkr = {
1245 .enable_reg = 0x31e4,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "camss_csi3_clk",
1249 .parent_names = (const char *[]){
1250 "csi3_clk_src",
1251 },
1252 .num_parents = 1,
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1255 },
1256 },
1257};
1258
1259static struct clk_branch camss_csi3phy_clk = {
1260 .halt_reg = 0x31f4,
1261 .clkr = {
1262 .enable_reg = 0x31f4,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "camss_csi3phy_clk",
1266 .parent_names = (const char *[]){
1267 "csi3_clk_src",
1268 },
1269 .num_parents = 1,
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274};
1275
1276static struct clk_branch camss_csi3pix_clk = {
1277 .halt_reg = 0x3214,
1278 .clkr = {
1279 .enable_reg = 0x3214,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "camss_csi3pix_clk",
1283 .parent_names = (const char *[]){
1284 "csi3_clk_src",
1285 },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1289 },
1290 },
1291};
1292
1293static struct clk_branch camss_csi3rdi_clk = {
1294 .halt_reg = 0x3204,
1295 .clkr = {
1296 .enable_reg = 0x3204,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "camss_csi3rdi_clk",
1300 .parent_names = (const char *[]){
1301 "csi3_clk_src",
1302 },
1303 .num_parents = 1,
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_branch2_ops,
1306 },
1307 },
1308};
1309
1310static struct clk_branch camss_csi_vfe0_clk = {
1311 .halt_reg = 0x3704,
1312 .clkr = {
1313 .enable_reg = 0x3704,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi_vfe0_clk",
1317 .parent_names = (const char *[]){
1318 "vfe0_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch camss_csi_vfe1_clk = {
1328 .halt_reg = 0x3714,
1329 .clkr = {
1330 .enable_reg = 0x3714,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "camss_csi_vfe1_clk",
1334 .parent_names = (const char *[]){
1335 "vfe1_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch camss_gp0_clk = {
1345 .halt_reg = 0x3444,
1346 .clkr = {
1347 .enable_reg = 0x3444,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "camss_gp0_clk",
1351 .parent_names = (const char *[]){
1352 "camss_gp0_clk_src",
1353 },
1354 .num_parents = 1,
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_branch2_ops,
1357 },
1358 },
1359};
1360
1361static struct clk_branch camss_gp1_clk = {
1362 .halt_reg = 0x3474,
1363 .clkr = {
1364 .enable_reg = 0x3474,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_gp1_clk",
1368 .parent_names = (const char *[]){
1369 "camss_gp1_clk_src",
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376};
1377
1378static struct clk_branch camss_ispif_ahb_clk = {
1379 .halt_reg = 0x3224,
1380 .clkr = {
1381 .enable_reg = 0x3224,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "camss_ispif_ahb_clk",
1385 .parent_names = (const char *[]){
1386 "mmss_ahb_clk_src",
1387 },
1388 .num_parents = 1,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392};
1393
1394static struct clk_branch camss_jpeg_jpeg0_clk = {
1395 .halt_reg = 0x35a8,
1396 .clkr = {
1397 .enable_reg = 0x35a8,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "camss_jpeg_jpeg0_clk",
1401 .parent_names = (const char *[]){
1402 "jpeg0_clk_src",
1403 },
1404 .num_parents = 1,
1405 .flags = CLK_SET_RATE_PARENT,
1406 .ops = &clk_branch2_ops,
1407 },
1408 },
1409};
1410
1411static struct clk_branch camss_jpeg_jpeg1_clk = {
1412 .halt_reg = 0x35ac,
1413 .clkr = {
1414 .enable_reg = 0x35ac,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "camss_jpeg_jpeg1_clk",
1418 .parent_names = (const char *[]){
1419 "jpeg1_clk_src",
1420 },
1421 .num_parents = 1,
1422 .flags = CLK_SET_RATE_PARENT,
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428static struct clk_branch camss_jpeg_jpeg2_clk = {
1429 .halt_reg = 0x35b0,
1430 .clkr = {
1431 .enable_reg = 0x35b0,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data){
1434 .name = "camss_jpeg_jpeg2_clk",
1435 .parent_names = (const char *[]){
1436 "jpeg2_clk_src",
1437 },
1438 .num_parents = 1,
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_branch2_ops,
1441 },
1442 },
1443};
1444
1445static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1446 .halt_reg = 0x35b4,
1447 .clkr = {
1448 .enable_reg = 0x35b4,
1449 .enable_mask = BIT(0),
1450 .hw.init = &(struct clk_init_data){
1451 .name = "camss_jpeg_jpeg_ahb_clk",
1452 .parent_names = (const char *[]){
1453 "mmss_ahb_clk_src",
1454 },
1455 .num_parents = 1,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1462 .halt_reg = 0x35b8,
1463 .clkr = {
1464 .enable_reg = 0x35b8,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "camss_jpeg_jpeg_axi_clk",
1468 .parent_names = (const char *[]){
1469 "mmss_axi_clk_src",
1470 },
1471 .num_parents = 1,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475};
1476
1477static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1478 .halt_reg = 0x35bc,
1479 .clkr = {
1480 .enable_reg = 0x35bc,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1484 .parent_names = (const char *[]){
1485 "ocmemnoc_clk_src",
1486 },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch camss_mclk0_clk = {
1495 .halt_reg = 0x3384,
1496 .clkr = {
1497 .enable_reg = 0x3384,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_mclk0_clk",
1501 .parent_names = (const char *[]){
1502 "mclk0_clk_src",
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509};
1510
1511static struct clk_branch camss_mclk1_clk = {
1512 .halt_reg = 0x33b4,
1513 .clkr = {
1514 .enable_reg = 0x33b4,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "camss_mclk1_clk",
1518 .parent_names = (const char *[]){
1519 "mclk1_clk_src",
1520 },
1521 .num_parents = 1,
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1524 },
1525 },
1526};
1527
1528static struct clk_branch camss_mclk2_clk = {
1529 .halt_reg = 0x33e4,
1530 .clkr = {
1531 .enable_reg = 0x33e4,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "camss_mclk2_clk",
1535 .parent_names = (const char *[]){
1536 "mclk2_clk_src",
1537 },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1541 },
1542 },
1543};
1544
1545static struct clk_branch camss_mclk3_clk = {
1546 .halt_reg = 0x3414,
1547 .clkr = {
1548 .enable_reg = 0x3414,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_mclk3_clk",
1552 .parent_names = (const char *[]){
1553 "mclk3_clk_src",
1554 },
1555 .num_parents = 1,
1556 .flags = CLK_SET_RATE_PARENT,
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560};
1561
1562static struct clk_branch camss_micro_ahb_clk = {
1563 .halt_reg = 0x3494,
1564 .clkr = {
1565 .enable_reg = 0x3494,
1566 .enable_mask = BIT(0),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "camss_micro_ahb_clk",
1569 .parent_names = (const char *[]){
1570 "mmss_ahb_clk_src",
1571 },
1572 .num_parents = 1,
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576};
1577
1578static struct clk_branch camss_phy0_csi0phytimer_clk = {
1579 .halt_reg = 0x3024,
1580 .clkr = {
1581 .enable_reg = 0x3024,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "camss_phy0_csi0phytimer_clk",
1585 .parent_names = (const char *[]){
1586 "csi0phytimer_clk_src",
1587 },
1588 .num_parents = 1,
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch camss_phy1_csi1phytimer_clk = {
1596 .halt_reg = 0x3054,
1597 .clkr = {
1598 .enable_reg = 0x3054,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camss_phy1_csi1phytimer_clk",
1602 .parent_names = (const char *[]){
1603 "csi1phytimer_clk_src",
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch camss_phy2_csi2phytimer_clk = {
1613 .halt_reg = 0x3084,
1614 .clkr = {
1615 .enable_reg = 0x3084,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "camss_phy2_csi2phytimer_clk",
1619 .parent_names = (const char *[]){
1620 "csi2phytimer_clk_src",
1621 },
1622 .num_parents = 1,
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1625 },
1626 },
1627};
1628
1629static struct clk_branch camss_top_ahb_clk = {
1630 .halt_reg = 0x3484,
1631 .clkr = {
1632 .enable_reg = 0x3484,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "camss_top_ahb_clk",
1636 .parent_names = (const char *[]){
1637 "mmss_ahb_clk_src",
1638 },
1639 .num_parents = 1,
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch camss_vfe_cpp_ahb_clk = {
1646 .halt_reg = 0x36b4,
1647 .clkr = {
1648 .enable_reg = 0x36b4,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "camss_vfe_cpp_ahb_clk",
1652 .parent_names = (const char *[]){
1653 "mmss_ahb_clk_src",
1654 },
1655 .num_parents = 1,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch camss_vfe_cpp_clk = {
1662 .halt_reg = 0x36b0,
1663 .clkr = {
1664 .enable_reg = 0x36b0,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_vfe_cpp_clk",
1668 .parent_names = (const char *[]){
1669 "cpp_clk_src",
1670 },
1671 .num_parents = 1,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1674 },
1675 },
1676};
1677
1678static struct clk_branch camss_vfe_vfe0_clk = {
1679 .halt_reg = 0x36a8,
1680 .clkr = {
1681 .enable_reg = 0x36a8,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_vfe_vfe0_clk",
1685 .parent_names = (const char *[]){
1686 "vfe0_clk_src",
1687 },
1688 .num_parents = 1,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1691 },
1692 },
1693};
1694
1695static struct clk_branch camss_vfe_vfe1_clk = {
1696 .halt_reg = 0x36ac,
1697 .clkr = {
1698 .enable_reg = 0x36ac,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_vfe_vfe1_clk",
1702 .parent_names = (const char *[]){
1703 "vfe1_clk_src",
1704 },
1705 .num_parents = 1,
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_branch2_ops,
1708 },
1709 },
1710};
1711
1712static struct clk_branch camss_vfe_vfe_ahb_clk = {
1713 .halt_reg = 0x36b8,
1714 .clkr = {
1715 .enable_reg = 0x36b8,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "camss_vfe_vfe_ahb_clk",
1719 .parent_names = (const char *[]){
1720 "mmss_ahb_clk_src",
1721 },
1722 .num_parents = 1,
1723 .ops = &clk_branch2_ops,
1724 },
1725 },
1726};
1727
1728static struct clk_branch camss_vfe_vfe_axi_clk = {
1729 .halt_reg = 0x36bc,
1730 .clkr = {
1731 .enable_reg = 0x36bc,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "camss_vfe_vfe_axi_clk",
1735 .parent_names = (const char *[]){
1736 "mmss_axi_clk_src",
1737 },
1738 .num_parents = 1,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1745 .halt_reg = 0x36c0,
1746 .clkr = {
1747 .enable_reg = 0x36c0,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_vfe_vfe_ocmemnoc_clk",
1751 .parent_names = (const char *[]){
1752 "ocmemnoc_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch mdss_ahb_clk = {
1762 .halt_reg = 0x2308,
1763 .clkr = {
1764 .enable_reg = 0x2308,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "mdss_ahb_clk",
1768 .parent_names = (const char *[]){
1769 "mmss_ahb_clk_src",
1770 },
1771 .num_parents = 1,
1772 .ops = &clk_branch2_ops,
1773 },
1774 },
1775};
1776
1777static struct clk_branch mdss_axi_clk = {
1778 .halt_reg = 0x2310,
1779 .clkr = {
1780 .enable_reg = 0x2310,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "mdss_axi_clk",
1784 .parent_names = (const char *[]){
1785 "mmss_axi_clk_src",
1786 },
1787 .num_parents = 1,
1788 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch mdss_byte0_clk = {
1795 .halt_reg = 0x233c,
1796 .clkr = {
1797 .enable_reg = 0x233c,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "mdss_byte0_clk",
1801 .parent_names = (const char *[]){
1802 "byte0_clk_src",
1803 },
1804 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch mdss_byte1_clk = {
1812 .halt_reg = 0x2340,
1813 .clkr = {
1814 .enable_reg = 0x2340,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "mdss_byte1_clk",
1818 .parent_names = (const char *[]){
1819 "byte1_clk_src",
1820 },
1821 .num_parents = 1,
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826};
1827
1828static struct clk_branch mdss_edpaux_clk = {
1829 .halt_reg = 0x2334,
1830 .clkr = {
1831 .enable_reg = 0x2334,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "mdss_edpaux_clk",
1835 .parent_names = (const char *[]){
1836 "edpaux_clk_src",
1837 },
1838 .num_parents = 1,
1839 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops,
1841 },
1842 },
1843};
1844
1845static struct clk_branch mdss_edplink_clk = {
1846 .halt_reg = 0x2330,
1847 .clkr = {
1848 .enable_reg = 0x2330,
1849 .enable_mask = BIT(0),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "mdss_edplink_clk",
1852 .parent_names = (const char *[]){
1853 "edplink_clk_src",
1854 },
1855 .num_parents = 1,
1856 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops,
1858 },
1859 },
1860};
1861
1862static struct clk_branch mdss_edppixel_clk = {
1863 .halt_reg = 0x232c,
1864 .clkr = {
1865 .enable_reg = 0x232c,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "mdss_edppixel_clk",
1869 .parent_names = (const char *[]){
1870 "edppixel_clk_src",
1871 },
1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877};
1878
1879static struct clk_branch mdss_esc0_clk = {
1880 .halt_reg = 0x2344,
1881 .clkr = {
1882 .enable_reg = 0x2344,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data){
1885 .name = "mdss_esc0_clk",
1886 .parent_names = (const char *[]){
1887 "esc0_clk_src",
1888 },
1889 .num_parents = 1,
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1892 },
1893 },
1894};
1895
1896static struct clk_branch mdss_esc1_clk = {
1897 .halt_reg = 0x2348,
1898 .clkr = {
1899 .enable_reg = 0x2348,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_esc1_clk",
1903 .parent_names = (const char *[]){
1904 "esc1_clk_src",
1905 },
1906 .num_parents = 1,
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1909 },
1910 },
1911};
1912
1913static struct clk_branch mdss_extpclk_clk = {
1914 .halt_reg = 0x2324,
1915 .clkr = {
1916 .enable_reg = 0x2324,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "mdss_extpclk_clk",
1920 .parent_names = (const char *[]){
1921 "extpclk_clk_src",
1922 },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928};
1929
1930static struct clk_branch mdss_hdmi_ahb_clk = {
1931 .halt_reg = 0x230c,
1932 .clkr = {
1933 .enable_reg = 0x230c,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "mdss_hdmi_ahb_clk",
1937 .parent_names = (const char *[]){
1938 "mmss_ahb_clk_src",
1939 },
1940 .num_parents = 1,
1941 .ops = &clk_branch2_ops,
1942 },
1943 },
1944};
1945
1946static struct clk_branch mdss_hdmi_clk = {
1947 .halt_reg = 0x2338,
1948 .clkr = {
1949 .enable_reg = 0x2338,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "mdss_hdmi_clk",
1953 .parent_names = (const char *[]){
1954 "hdmi_clk_src",
1955 },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch mdss_mdp_clk = {
1964 .halt_reg = 0x231c,
1965 .clkr = {
1966 .enable_reg = 0x231c,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "mdss_mdp_clk",
1970 .parent_names = (const char *[]){
1971 "mdp_clk_src",
1972 },
1973 .num_parents = 1,
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978};
1979
1980static struct clk_branch mdss_mdp_lut_clk = {
1981 .halt_reg = 0x2320,
1982 .clkr = {
1983 .enable_reg = 0x2320,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "mdss_mdp_lut_clk",
1987 .parent_names = (const char *[]){
1988 "mdp_clk_src",
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch mdss_pclk0_clk = {
1998 .halt_reg = 0x2314,
1999 .clkr = {
2000 .enable_reg = 0x2314,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "mdss_pclk0_clk",
2004 .parent_names = (const char *[]){
2005 "pclk0_clk_src",
2006 },
2007 .num_parents = 1,
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2010 },
2011 },
2012};
2013
2014static struct clk_branch mdss_pclk1_clk = {
2015 .halt_reg = 0x2318,
2016 .clkr = {
2017 .enable_reg = 0x2318,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "mdss_pclk1_clk",
2021 .parent_names = (const char *[]){
2022 "pclk1_clk_src",
2023 },
2024 .num_parents = 1,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2027 },
2028 },
2029};
2030
2031static struct clk_branch mdss_vsync_clk = {
2032 .halt_reg = 0x2328,
2033 .clkr = {
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "mdss_vsync_clk",
2038 .parent_names = (const char *[]){
2039 "vsync_clk_src",
2040 },
2041 .num_parents = 1,
2042 .flags = CLK_SET_RATE_PARENT,
2043 .ops = &clk_branch2_ops,
2044 },
2045 },
2046};
2047
2048static struct clk_branch mmss_misc_ahb_clk = {
2049 .halt_reg = 0x502c,
2050 .clkr = {
2051 .enable_reg = 0x502c,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "mmss_misc_ahb_clk",
2055 .parent_names = (const char *[]){
2056 "mmss_ahb_clk_src",
2057 },
2058 .num_parents = 1,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mmss_mmssnoc_ahb_clk = {
2065 .halt_reg = 0x5024,
2066 .clkr = {
2067 .enable_reg = 0x5024,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mmss_mmssnoc_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .ops = &clk_branch2_ops,
2076 .flags = CLK_IGNORE_UNUSED,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2082 .halt_reg = 0x5028,
2083 .clkr = {
2084 .enable_reg = 0x5028,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mmss_mmssnoc_bto_ahb_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_ahb_clk_src",
2090 },
2091 .num_parents = 1,
2092 .ops = &clk_branch2_ops,
2093 .flags = CLK_IGNORE_UNUSED,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mmss_mmssnoc_axi_clk = {
2099 .halt_reg = 0x506c,
2100 .clkr = {
2101 .enable_reg = 0x506c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mmss_mmssnoc_axi_clk",
2105 .parent_names = (const char *[]){
2106 "mmss_axi_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mmss_s0_axi_clk = {
2116 .halt_reg = 0x5064,
2117 .clkr = {
2118 .enable_reg = 0x5064,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mmss_s0_axi_clk",
2122 .parent_names = (const char *[]){
2123 "mmss_axi_clk_src",
2124 },
2125 .num_parents = 1,
2126 .ops = &clk_branch2_ops,
2127 .flags = CLK_IGNORE_UNUSED,
2128 },
2129 },
2130};
2131
2132static struct clk_branch ocmemcx_ahb_clk = {
2133 .halt_reg = 0x405c,
2134 .clkr = {
2135 .enable_reg = 0x405c,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "ocmemcx_ahb_clk",
2139 .parent_names = (const char *[]){
2140 "mmss_ahb_clk_src",
2141 },
2142 .num_parents = 1,
2143 .ops = &clk_branch2_ops,
2144 },
2145 },
2146};
2147
2148static struct clk_branch ocmemcx_ocmemnoc_clk = {
2149 .halt_reg = 0x4058,
2150 .clkr = {
2151 .enable_reg = 0x4058,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "ocmemcx_ocmemnoc_clk",
2155 .parent_names = (const char *[]){
2156 "ocmemnoc_clk_src",
2157 },
2158 .num_parents = 1,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2161 },
2162 },
2163};
2164
2165static struct clk_branch oxili_ocmemgx_clk = {
2166 .halt_reg = 0x402c,
2167 .clkr = {
2168 .enable_reg = 0x402c,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "oxili_ocmemgx_clk",
2172 .parent_names = (const char *[]){
2173 "gfx3d_clk_src",
2174 },
2175 .num_parents = 1,
2176 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops,
2178 },
2179 },
2180};
2181
2182static struct clk_branch ocmemnoc_clk = {
2183 .halt_reg = 0x50b4,
2184 .clkr = {
2185 .enable_reg = 0x50b4,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "ocmemnoc_clk",
2189 .parent_names = (const char *[]){
2190 "ocmemnoc_clk_src",
2191 },
2192 .num_parents = 1,
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2195 },
2196 },
2197};
2198
2199static struct clk_branch oxili_gfx3d_clk = {
2200 .halt_reg = 0x4028,
2201 .clkr = {
2202 .enable_reg = 0x4028,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "oxili_gfx3d_clk",
2206 .parent_names = (const char *[]){
2207 "gfx3d_clk_src",
2208 },
2209 .num_parents = 1,
2210 .flags = CLK_SET_RATE_PARENT,
2211 .ops = &clk_branch2_ops,
2212 },
2213 },
2214};
2215
2216static struct clk_branch oxilicx_ahb_clk = {
2217 .halt_reg = 0x403c,
2218 .clkr = {
2219 .enable_reg = 0x403c,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "oxilicx_ahb_clk",
2223 .parent_names = (const char *[]){
2224 "mmss_ahb_clk_src",
2225 },
2226 .num_parents = 1,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch oxilicx_axi_clk = {
2233 .halt_reg = 0x4038,
2234 .clkr = {
2235 .enable_reg = 0x4038,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "oxilicx_axi_clk",
2239 .parent_names = (const char *[]){
2240 "mmss_axi_clk_src",
2241 },
2242 .num_parents = 1,
2243 .ops = &clk_branch2_ops,
2244 },
2245 },
2246};
2247
2248static struct clk_branch venus0_ahb_clk = {
2249 .halt_reg = 0x1030,
2250 .clkr = {
2251 .enable_reg = 0x1030,
2252 .enable_mask = BIT(0),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "venus0_ahb_clk",
2255 .parent_names = (const char *[]){
2256 "mmss_ahb_clk_src",
2257 },
2258 .num_parents = 1,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch venus0_axi_clk = {
2265 .halt_reg = 0x1034,
2266 .clkr = {
2267 .enable_reg = 0x1034,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "venus0_axi_clk",
2271 .parent_names = (const char *[]){
2272 "mmss_axi_clk_src",
2273 },
2274 .num_parents = 1,
2275 .ops = &clk_branch2_ops,
2276 },
2277 },
2278};
2279
2280static struct clk_branch venus0_ocmemnoc_clk = {
2281 .halt_reg = 0x1038,
2282 .clkr = {
2283 .enable_reg = 0x1038,
2284 .enable_mask = BIT(0),
2285 .hw.init = &(struct clk_init_data){
2286 .name = "venus0_ocmemnoc_clk",
2287 .parent_names = (const char *[]){
2288 "ocmemnoc_clk_src",
2289 },
2290 .num_parents = 1,
2291 .flags = CLK_SET_RATE_PARENT,
2292 .ops = &clk_branch2_ops,
2293 },
2294 },
2295};
2296
2297static struct clk_branch venus0_vcodec0_clk = {
2298 .halt_reg = 0x1028,
2299 .clkr = {
2300 .enable_reg = 0x1028,
2301 .enable_mask = BIT(0),
2302 .hw.init = &(struct clk_init_data){
2303 .name = "venus0_vcodec0_clk",
2304 .parent_names = (const char *[]){
2305 "vcodec0_clk_src",
2306 },
2307 .num_parents = 1,
2308 .flags = CLK_SET_RATE_PARENT,
2309 .ops = &clk_branch2_ops,
2310 },
2311 },
2312};
2313
2314static const struct pll_config mmpll1_config = {
2315 .l = 60,
2316 .m = 25,
2317 .n = 32,
2318 .vco_val = 0x0,
2319 .vco_mask = 0x3 << 20,
2320 .pre_div_val = 0x0,
2321 .pre_div_mask = 0x3 << 12,
2322 .post_div_val = 0x0,
2323 .post_div_mask = 0x3 << 8,
2324 .mn_ena_mask = BIT(24),
2325 .main_output_mask = BIT(0),
2326};
2327
2328static struct pll_config mmpll3_config = {
2329 .l = 48,
2330 .m = 7,
2331 .n = 16,
2332 .vco_val = 0x0,
2333 .vco_mask = 0x3 << 20,
2334 .pre_div_val = 0x0,
2335 .pre_div_mask = 0x3 << 12,
2336 .post_div_val = 0x0,
2337 .post_div_mask = 0x3 << 8,
2338 .mn_ena_mask = BIT(24),
2339 .main_output_mask = BIT(0),
2340 .aux_output_mask = BIT(1),
2341};
2342
2343static struct clk_regmap *mmcc_msm8974_clocks[] = {
2344 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2345 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2346 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2347 [MMPLL0] = &mmpll0.clkr,
2348 [MMPLL0_VOTE] = &mmpll0_vote,
2349 [MMPLL1] = &mmpll1.clkr,
2350 [MMPLL1_VOTE] = &mmpll1_vote,
2351 [MMPLL2] = &mmpll2.clkr,
2352 [MMPLL3] = &mmpll3.clkr,
2353 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2354 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2355 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2356 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2357 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2358 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2359 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2360 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2361 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2362 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2363 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2364 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2365 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2366 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2367 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2368 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2369 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2370 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2371 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2372 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2373 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2374 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2375 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2376 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2377 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2378 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2379 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2380 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2381 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2382 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2383 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2384 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2385 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2386 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2387 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2388 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2389 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2390 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2391 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2392 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2393 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2394 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2395 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2396 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2397 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2398 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2399 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2400 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2401 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2402 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2403 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2404 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2405 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2406 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2407 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2408 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2409 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2410 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2411 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2412 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2413 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2414 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2415 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2416 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2417 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2418 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2419 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2420 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2421 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2422 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2423 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2424 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2425 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2426 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2427 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2428 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2429 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2430 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2431 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2432 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2433 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2434 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2435 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2436 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2437 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2438 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2439 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2440 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2441 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2442 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2443 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2444 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2445 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2446 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2447 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2448 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2449 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2450 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2451 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2452 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2453 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2454 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2455 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2456 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2457 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2458 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2459 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2460 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2461 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2462 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2463 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2464 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2465 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2466 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2467 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2468 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2469 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2470};
2471
2472static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2473 [SPDM_RESET] = { 0x0200 },
2474 [SPDM_RM_RESET] = { 0x0300 },
2475 [VENUS0_RESET] = { 0x1020 },
2476 [MDSS_RESET] = { 0x2300 },
2477 [CAMSS_PHY0_RESET] = { 0x3020 },
2478 [CAMSS_PHY1_RESET] = { 0x3050 },
2479 [CAMSS_PHY2_RESET] = { 0x3080 },
2480 [CAMSS_CSI0_RESET] = { 0x30b0 },
2481 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2482 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2483 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2484 [CAMSS_CSI1_RESET] = { 0x3120 },
2485 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2486 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2487 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2488 [CAMSS_CSI2_RESET] = { 0x3180 },
2489 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2490 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2491 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2492 [CAMSS_CSI3_RESET] = { 0x31e0 },
2493 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2494 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2495 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2496 [CAMSS_ISPIF_RESET] = { 0x3220 },
2497 [CAMSS_CCI_RESET] = { 0x3340 },
2498 [CAMSS_MCLK0_RESET] = { 0x3380 },
2499 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2500 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2501 [CAMSS_MCLK3_RESET] = { 0x3410 },
2502 [CAMSS_GP0_RESET] = { 0x3440 },
2503 [CAMSS_GP1_RESET] = { 0x3470 },
2504 [CAMSS_TOP_RESET] = { 0x3480 },
2505 [CAMSS_MICRO_RESET] = { 0x3490 },
2506 [CAMSS_JPEG_RESET] = { 0x35a0 },
2507 [CAMSS_VFE_RESET] = { 0x36a0 },
2508 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2509 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2510 [OXILI_RESET] = { 0x4020 },
2511 [OXILICX_RESET] = { 0x4030 },
2512 [OCMEMCX_RESET] = { 0x4050 },
2513 [MMSS_RBCRP_RESET] = { 0x4080 },
2514 [MMSSNOCAHB_RESET] = { 0x5020 },
2515 [MMSSNOCAXI_RESET] = { 0x5060 },
2516 [OCMEMNOC_RESET] = { 0x50b0 },
2517};
2518
2519static const struct regmap_config mmcc_msm8974_regmap_config = {
2520 .reg_bits = 32,
2521 .reg_stride = 4,
2522 .val_bits = 32,
2523 .max_register = 0x5104,
2524 .fast_io = true,
2525};
2526
2527static const struct of_device_id mmcc_msm8974_match_table[] = {
2528 { .compatible = "qcom,mmcc-msm8974" },
2529 { }
2530};
2531MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2532
2533struct qcom_cc {
2534 struct qcom_reset_controller reset;
2535 struct clk_onecell_data data;
2536 struct clk *clks[];
2537};
2538
2539static int mmcc_msm8974_probe(struct platform_device *pdev)
2540{
2541 void __iomem *base;
2542 struct resource *res;
2543 int i, ret;
2544 struct device *dev = &pdev->dev;
2545 struct clk *clk;
2546 struct clk_onecell_data *data;
2547 struct clk **clks;
2548 struct regmap *regmap;
2549 size_t num_clks;
2550 struct qcom_reset_controller *reset;
2551 struct qcom_cc *cc;
2552
2553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2554 base = devm_ioremap_resource(dev, res);
2555 if (IS_ERR(base))
2556 return PTR_ERR(base);
2557
2558 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8974_regmap_config);
2559 if (IS_ERR(regmap))
2560 return PTR_ERR(regmap);
2561
2562 num_clks = ARRAY_SIZE(mmcc_msm8974_clocks);
2563 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2564 GFP_KERNEL);
2565 if (!cc)
2566 return -ENOMEM;
2567
2568 clks = cc->clks;
2569 data = &cc->data;
2570 data->clks = clks;
2571 data->clk_num = num_clks;
2572
2573 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2574 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2575
2576 for (i = 0; i < num_clks; i++) {
2577 if (!mmcc_msm8974_clocks[i])
2578 continue;
2579 clk = devm_clk_register_regmap(dev, mmcc_msm8974_clocks[i]);
2580 if (IS_ERR(clk))
2581 return PTR_ERR(clk);
2582 clks[i] = clk;
2583 }
2584
2585 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2586 if (ret)
2587 return ret;
2588
2589 reset = &cc->reset;
2590 reset->rcdev.of_node = dev->of_node;
2591 reset->rcdev.ops = &qcom_reset_ops,
2592 reset->rcdev.owner = THIS_MODULE,
2593 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2594 reset->regmap = regmap;
2595 reset->reset_map = mmcc_msm8974_resets,
2596 platform_set_drvdata(pdev, &reset->rcdev);
2597
2598 ret = reset_controller_register(&reset->rcdev);
2599 if (ret)
2600 of_clk_del_provider(dev->of_node);
2601
2602 return ret;
2603}
2604
2605static int mmcc_msm8974_remove(struct platform_device *pdev)
2606{
2607 of_clk_del_provider(pdev->dev.of_node);
2608 reset_controller_unregister(platform_get_drvdata(pdev));
2609 return 0;
2610}
2611
2612static struct platform_driver mmcc_msm8974_driver = {
2613 .probe = mmcc_msm8974_probe,
2614 .remove = mmcc_msm8974_remove,
2615 .driver = {
2616 .name = "mmcc-msm8974",
2617 .owner = THIS_MODULE,
2618 .of_match_table = mmcc_msm8974_match_table,
2619 },
2620};
2621module_platform_driver(mmcc_msm8974_driver);
2622
2623MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2624MODULE_LICENSE("GPL v2");
2625MODULE_ALIAS("platform:mmcc-msm8974");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 14:04:50 -0500