diff options
Diffstat (limited to 'drivers/clk/qcom/mmcc-msm8960.c')
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8960.c | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index e8b33bbc362f..9711bca9cc06 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c | |||
| @@ -33,18 +33,21 @@ | |||
| 33 | #include "clk-branch.h" | 33 | #include "clk-branch.h" |
| 34 | #include "reset.h" | 34 | #include "reset.h" |
| 35 | 35 | ||
| 36 | #define P_PXO 0 | 36 | enum { |
| 37 | #define P_PLL8 1 | 37 | P_PXO, |
| 38 | #define P_PLL2 2 | 38 | P_PLL8, |
| 39 | #define P_PLL3 3 | 39 | P_PLL2, |
| 40 | #define P_PLL15 3 | 40 | P_PLL3, |
| 41 | P_PLL15, | ||
| 42 | P_HDMI_PLL, | ||
| 43 | }; | ||
| 41 | 44 | ||
| 42 | #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } | 45 | #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } |
| 43 | 46 | ||
| 44 | static u8 mmcc_pxo_pll8_pll2_map[] = { | 47 | static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { |
| 45 | [P_PXO] = 0, | 48 | { P_PXO, 0 }, |
| 46 | [P_PLL8] = 2, | 49 | { P_PLL8, 2 }, |
| 47 | [P_PLL2] = 1, | 50 | { P_PLL2, 1 } |
| 48 | }; | 51 | }; |
| 49 | 52 | ||
| 50 | static const char *mmcc_pxo_pll8_pll2[] = { | 53 | static const char *mmcc_pxo_pll8_pll2[] = { |
| @@ -53,11 +56,11 @@ static const char *mmcc_pxo_pll8_pll2[] = { | |||
| 53 | "pll2", | 56 | "pll2", |
| 54 | }; | 57 | }; |
| 55 | 58 | ||
| 56 | static u8 mmcc_pxo_pll8_pll2_pll3_map[] = { | 59 | static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { |
| 57 | [P_PXO] = 0, | 60 | { P_PXO, 0 }, |
| 58 | [P_PLL8] = 2, | 61 | { P_PLL8, 2 }, |
| 59 | [P_PLL2] = 1, | 62 | { P_PLL2, 1 }, |
| 60 | [P_PLL3] = 3, | 63 | { P_PLL3, 3 } |
| 61 | }; | 64 | }; |
| 62 | 65 | ||
| 63 | static const char *mmcc_pxo_pll8_pll2_pll15[] = { | 66 | static const char *mmcc_pxo_pll8_pll2_pll15[] = { |
| @@ -67,11 +70,11 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = { | |||
| 67 | "pll15", | 70 | "pll15", |
| 68 | }; | 71 | }; |
| 69 | 72 | ||
| 70 | static u8 mmcc_pxo_pll8_pll2_pll15_map[] = { | 73 | static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { |
| 71 | [P_PXO] = 0, | 74 | { P_PXO, 0 }, |
| 72 | [P_PLL8] = 2, | 75 | { P_PLL8, 2 }, |
| 73 | [P_PLL2] = 1, | 76 | { P_PLL2, 1 }, |
| 74 | [P_PLL15] = 3, | 77 | { P_PLL15, 3 } |
| 75 | }; | 78 | }; |
| 76 | 79 | ||
| 77 | static const char *mmcc_pxo_pll8_pll2_pll3[] = { | 80 | static const char *mmcc_pxo_pll8_pll2_pll3[] = { |
| @@ -1377,11 +1380,9 @@ static struct clk_branch rot_clk = { | |||
| 1377 | }, | 1380 | }, |
| 1378 | }; | 1381 | }; |
| 1379 | 1382 | ||
| 1380 | #define P_HDMI_PLL 1 | 1383 | static const struct parent_map mmcc_pxo_hdmi_map[] = { |
| 1381 | 1384 | { P_PXO, 0 }, | |
| 1382 | static u8 mmcc_pxo_hdmi_map[] = { | 1385 | { P_HDMI_PLL, 3 } |
| 1383 | [P_PXO] = 0, | ||
| 1384 | [P_HDMI_PLL] = 3, | ||
| 1385 | }; | 1386 | }; |
| 1386 | 1387 | ||
| 1387 | static const char *mmcc_pxo_hdmi[] = { | 1388 | static const char *mmcc_pxo_hdmi[] = { |