1 files changed, 32 insertions, 30 deletions
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef90264214..54a756b90a37 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,20 @@
 #include "clk-branch.h"
 #include "reset.h"
-#define P_XO    0
+enum {
-#define P_GPLL0 1
+        P_XO,
-#define P_GPLL1 1
+        P_GPLL0,
-#define P_GPLL4 2
+        P_GPLL1,
-#define P_PCIE_0_1_PIPE_CLK 1
+        P_GPLL4,
-#define P_SATA_ASIC0_CLK 1
+        P_PCIE_0_1_PIPE_CLK,
-#define P_SATA_RX_CLK 1
+        P_SATA_ASIC0_CLK,
-#define P_SLEEP_CLK 1
+        P_SATA_RX_CLK,
+        P_SLEEP_CLK,
+};
-static const u8 gcc_xo_gpll0_map[] = {
+static const struct parent_map gcc_xo_gpll0_map[] = {
-        [P_XO]          = 0,
+        { P_XO, 0 },
-        [P_GPLL0]       = 1,
+        { P_GPLL0, 1 }
 };
 static const char *gcc_xo_gpll0[] = {
@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
        "gpll0_vote",
 };
-static const u8 gcc_xo_gpll0_gpll4_map[] = {
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-        [P_XO]          = 0,
+        { P_XO, 0 },
-        [P_GPLL0]       = 1,
+        { P_GPLL0, 1 },
-        [P_GPLL4]       = 5,
+        { P_GPLL4, 5 }
 };
 static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
        "gpll4_vote",
 };
-static const u8 gcc_xo_sata_asic0_map[] = {
+static const struct parent_map gcc_xo_sata_asic0_map[] = {
-        [P_XO]                  = 0,
+        { P_XO, 0 },
-        [P_SATA_ASIC0_CLK]      = 2,
+        { P_SATA_ASIC0_CLK, 2 }
 };
 static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
        "sata_asic0_clk",
 };
-static const u8 gcc_xo_sata_rx_map[] = {
+static const struct parent_map gcc_xo_sata_rx_map[] = {
-        [P_XO]                  = 0,
+        { P_XO, 0 },
-        [P_SATA_RX_CLK]         = 2,
+        { P_SATA_RX_CLK, 2}
 };
 static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
        "sata_rx_clk",
 };
-static const u8 gcc_xo_pcie_map[] = {
+static const struct parent_map gcc_xo_pcie_map[] = {
-        [P_XO]                  = 0,
+        { P_XO, 0 },
-        [P_PCIE_0_1_PIPE_CLK]   = 2,
+        { P_PCIE_0_1_PIPE_CLK, 2 }
 };
 static const char *gcc_xo_pcie[] = {
@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
        "pcie_pipe",
 };
-static const u8 gcc_xo_pcie_sleep_map[] = {
+static const struct parent_map gcc_xo_pcie_sleep_map[] = {
-        [P_XO]                  = 0,
+        { P_XO, 0 },
-        [P_SLEEP_CLK]           = 6,
+        { P_SLEEP_CLK, 6 }
 };
 static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
        { }
 };
-static u8 usb_hsic_clk_src_map[] = {
+static const struct parent_map usb_hsic_clk_src_map[] = {
-        [P_XO]          = 0,
+        { P_XO, 0 },
-        [P_GPLL1]       = 4,
+        { P_GPLL1, 4 }
 };
 static struct clk_rcg2 usb_hsic_clk_src = {

diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index e3ef90264214..54a756b90a37 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,20 @@
32	#include "clk-branch.h"	32	#include "clk-branch.h"
33	#include "reset.h"	33	#include "reset.h"
34		34
35	#define P_XO 0	35	enum {
36	#define P_GPLL0 1	36	P_XO,
37	#define P_GPLL1 1	37	P_GPLL0,
38	#define P_GPLL4 2	38	P_GPLL1,
39	#define P_PCIE_0_1_PIPE_CLK 1	39	P_GPLL4,
40	#define P_SATA_ASIC0_CLK 1	40	P_PCIE_0_1_PIPE_CLK,
41	#define P_SATA_RX_CLK 1	41	P_SATA_ASIC0_CLK,
42	#define P_SLEEP_CLK 1	42	P_SATA_RX_CLK,
		43	P_SLEEP_CLK,
		44	};
43		45
44	static const u8 gcc_xo_gpll0_map[] = {	46	static const struct parent_map gcc_xo_gpll0_map[] = {
45	[P_XO] = 0,	47	{ P_XO, 0 },
46	[P_GPLL0] = 1,	48	{ P_GPLL0, 1 }
47	};	49	};
48		50
49	static const char *gcc_xo_gpll0[] = {	51	static const char *gcc_xo_gpll0[] = {
@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
51	"gpll0_vote",	53	"gpll0_vote",
52	};	54	};
53		55
54	static const u8 gcc_xo_gpll0_gpll4_map[] = {	56	static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
55	[P_XO] = 0,	57	{ P_XO, 0 },
56	[P_GPLL0] = 1,	58	{ P_GPLL0, 1 },
57	[P_GPLL4] = 5,	59	{ P_GPLL4, 5 }
58	};	60	};
59		61
60	static const char *gcc_xo_gpll0_gpll4[] = {	62	static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
63	"gpll4_vote",	65	"gpll4_vote",
64	};	66	};
65		67
66	static const u8 gcc_xo_sata_asic0_map[] = {	68	static const struct parent_map gcc_xo_sata_asic0_map[] = {
67	[P_XO] = 0,	69	{ P_XO, 0 },
68	[P_SATA_ASIC0_CLK] = 2,	70	{ P_SATA_ASIC0_CLK, 2 }
69	};	71	};
70		72
71	static const char *gcc_xo_sata_asic0[] = {	73	static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
73	"sata_asic0_clk",	75	"sata_asic0_clk",
74	};	76	};
75		77
76	static const u8 gcc_xo_sata_rx_map[] = {	78	static const struct parent_map gcc_xo_sata_rx_map[] = {
77	[P_XO] = 0,	79	{ P_XO, 0 },
78	[P_SATA_RX_CLK] = 2,	80	{ P_SATA_RX_CLK, 2}
79	};	81	};
80		82
81	static const char *gcc_xo_sata_rx[] = {	83	static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
83	"sata_rx_clk",	85	"sata_rx_clk",
84	};	86	};
85		87
86	static const u8 gcc_xo_pcie_map[] = {	88	static const struct parent_map gcc_xo_pcie_map[] = {
87	[P_XO] = 0,	89	{ P_XO, 0 },
88	[P_PCIE_0_1_PIPE_CLK] = 2,	90	{ P_PCIE_0_1_PIPE_CLK, 2 }
89	};	91	};
90		92
91	static const char *gcc_xo_pcie[] = {	93	static const char *gcc_xo_pcie[] = {
@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
93	"pcie_pipe",	95	"pcie_pipe",
94	};	96	};
95		97
96	static const u8 gcc_xo_pcie_sleep_map[] = {	98	static const struct parent_map gcc_xo_pcie_sleep_map[] = {
97	[P_XO] = 0,	99	{ P_XO, 0 },
98	[P_SLEEP_CLK] = 6,	100	{ P_SLEEP_CLK, 6 }
99	};	101	};
100		102
101	static const char *gcc_xo_pcie_sleep[] = {	103	static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1263	{ }	1265	{ }
1264	};	1266	};
1265		1267
1266	static u8 usb_hsic_clk_src_map[] = {	1268	static const struct parent_map usb_hsic_clk_src_map[] = {
1267	[P_XO] = 0,	1269	{ P_XO, 0 },
1268	[P_GPLL1] = 4,	1270	{ P_GPLL1, 4 }
1269	};	1271	};
1270		1272
1271	static struct clk_rcg2 usb_hsic_clk_src = {	1273	static struct clk_rcg2 usb_hsic_clk_src = {