diff options
Diffstat (limited to 'drivers/clk/qcom/clk-pll.h')
-rw-r--r-- | drivers/clk/qcom/clk-pll.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h new file mode 100644 index 000000000000..0775a99ca768 --- /dev/null +++ b/drivers/clk/qcom/clk-pll.h | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __QCOM_CLK_PLL_H__ | ||
15 | #define __QCOM_CLK_PLL_H__ | ||
16 | |||
17 | #include <linux/clk-provider.h> | ||
18 | #include "clk-regmap.h" | ||
19 | |||
20 | /** | ||
21 | * struct clk_pll - phase locked loop (PLL) | ||
22 | * @l_reg: L register | ||
23 | * @m_reg: M register | ||
24 | * @n_reg: N register | ||
25 | * @config_reg: config register | ||
26 | * @mode_reg: mode register | ||
27 | * @status_reg: status register | ||
28 | * @status_bit: ANDed with @status_reg to determine if PLL is enabled | ||
29 | * @hw: handle between common and hardware-specific interfaces | ||
30 | */ | ||
31 | struct clk_pll { | ||
32 | u32 l_reg; | ||
33 | u32 m_reg; | ||
34 | u32 n_reg; | ||
35 | u32 config_reg; | ||
36 | u32 mode_reg; | ||
37 | u32 status_reg; | ||
38 | u8 status_bit; | ||
39 | |||
40 | struct clk_regmap clkr; | ||
41 | }; | ||
42 | |||
43 | extern const struct clk_ops clk_pll_ops; | ||
44 | extern const struct clk_ops clk_pll_vote_ops; | ||
45 | |||
46 | #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) | ||
47 | |||
48 | struct pll_config { | ||
49 | u16 l; | ||
50 | u32 m; | ||
51 | u32 n; | ||
52 | u32 vco_val; | ||
53 | u32 vco_mask; | ||
54 | u32 pre_div_val; | ||
55 | u32 pre_div_mask; | ||
56 | u32 post_div_val; | ||
57 | u32 post_div_mask; | ||
58 | u32 mn_ena_mask; | ||
59 | u32 main_output_mask; | ||
60 | u32 aux_output_mask; | ||
61 | }; | ||
62 | |||
63 | void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, | ||
64 | const struct pll_config *config, bool fsm_mode); | ||
65 | |||
66 | #endif | ||