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-rw-r--r--drivers/char/agp/Makefile1
-rw-r--r--drivers/char/agp/intel-agp.c200
-rw-r--r--drivers/char/agp/intel-agp.h43
-rw-r--r--drivers/char/agp/intel-gtt.c1088
4 files changed, 615 insertions, 717 deletions
diff --git a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile
index 627f542827c7..8eb56e273e75 100644
--- a/drivers/char/agp/Makefile
+++ b/drivers/char/agp/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o 13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
14obj-$(CONFIG_AGP_I460) += i460-agp.o 14obj-$(CONFIG_AGP_I460) += i460-agp.o
15obj-$(CONFIG_AGP_INTEL) += intel-agp.o 15obj-$(CONFIG_AGP_INTEL) += intel-agp.o
16obj-$(CONFIG_AGP_INTEL) += intel-gtt.o
16obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o 17obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
17obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o 18obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
18obj-$(CONFIG_AGP_SIS) += sis-agp.o 19obj-$(CONFIG_AGP_SIS) += sis-agp.o
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index cd18493c9527..5cd2221ab472 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -12,9 +12,6 @@
12#include <asm/smp.h> 12#include <asm/smp.h>
13#include "agp.h" 13#include "agp.h"
14#include "intel-agp.h" 14#include "intel-agp.h"
15#include <linux/intel-gtt.h>
16
17#include "intel-gtt.c"
18 15
19int intel_agp_enabled; 16int intel_agp_enabled;
20EXPORT_SYMBOL(intel_agp_enabled); 17EXPORT_SYMBOL(intel_agp_enabled);
@@ -703,179 +700,37 @@ static const struct agp_bridge_driver intel_7505_driver = {
703 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 700 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
704}; 701};
705 702
706static int find_gmch(u16 device)
707{
708 struct pci_dev *gmch_device;
709
710 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
711 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
712 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
713 device, gmch_device);
714 }
715
716 if (!gmch_device)
717 return 0;
718
719 intel_private.pcidev = gmch_device;
720 return 1;
721}
722
723/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 703/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
724 * driver and gmch_driver must be non-null, and find_gmch will determine 704 * driver and gmch_driver must be non-null, and find_gmch will determine
725 * which one should be used if a gmch_chip_id is present. 705 * which one should be used if a gmch_chip_id is present.
726 */ 706 */
727static const struct intel_driver_description { 707static const struct intel_agp_driver_description {
728 unsigned int chip_id; 708 unsigned int chip_id;
729 unsigned int gmch_chip_id;
730 char *name; 709 char *name;
731 const struct agp_bridge_driver *driver; 710 const struct agp_bridge_driver *driver;
732 const struct agp_bridge_driver *gmch_driver;
733} intel_agp_chipsets[] = { 711} intel_agp_chipsets[] = {
734 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL }, 712 { PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
735 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL }, 713 { PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
736 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL }, 714 { PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
737 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 715 { PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
738 NULL, &intel_810_driver }, 716 { PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
739 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 717 { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
740 NULL, &intel_810_driver }, 718 { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
741 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 719 { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
742 NULL, &intel_810_driver }, 720 { PCI_DEVICE_ID_INTEL_82845_HB, "845G", &intel_845_driver },
743 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 721 { PCI_DEVICE_ID_INTEL_82845G_HB, "830M", &intel_845_driver },
744 &intel_815_driver, &intel_810_driver }, 722 { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
745 { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL }, 723 { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
746 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL }, 724 { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
747 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 725 { PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
748 &intel_830mp_driver, &intel_830_driver }, 726 { PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
749 { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL }, 727 { PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
750 { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL }, 728 { PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
751 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 729 { PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
752 &intel_845_driver, &intel_830_driver }, 730 { PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
753 { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL }, 731 { 0, NULL, NULL }
754 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854",
755 &intel_845_driver, &intel_830_driver },
756 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
757 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
758 &intel_845_driver, &intel_830_driver },
759 { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
760 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
761 &intel_845_driver, &intel_830_driver },
762 { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
763 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
764 NULL, &intel_915_driver },
765 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
766 NULL, &intel_915_driver },
767 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
768 NULL, &intel_915_driver },
769 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
770 NULL, &intel_915_driver },
771 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
772 NULL, &intel_915_driver },
773 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
774 NULL, &intel_915_driver },
775 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
776 NULL, &intel_i965_driver },
777 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
778 NULL, &intel_i965_driver },
779 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
780 NULL, &intel_i965_driver },
781 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
782 NULL, &intel_i965_driver },
783 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
784 NULL, &intel_i965_driver },
785 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
786 NULL, &intel_i965_driver },
787 { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
788 { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
789 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33",
790 NULL, &intel_g33_driver },
791 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
792 NULL, &intel_g33_driver },
793 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
794 NULL, &intel_g33_driver },
795 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
796 NULL, &intel_g33_driver },
797 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
798 NULL, &intel_g33_driver },
799 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG,
800 "GM45", NULL, &intel_i965_driver },
801 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG,
802 "Eaglelake", NULL, &intel_i965_driver },
803 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG,
804 "Q45/Q43", NULL, &intel_i965_driver },
805 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG,
806 "G45/G43", NULL, &intel_i965_driver },
807 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG,
808 "B43", NULL, &intel_i965_driver },
809 { PCI_DEVICE_ID_INTEL_B43_1_HB, PCI_DEVICE_ID_INTEL_B43_1_IG,
810 "B43", NULL, &intel_i965_driver },
811 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG,
812 "G41", NULL, &intel_i965_driver },
813 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
814 "HD Graphics", NULL, &intel_i965_driver },
815 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
816 "HD Graphics", NULL, &intel_i965_driver },
817 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
818 "HD Graphics", NULL, &intel_i965_driver },
819 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
820 "HD Graphics", NULL, &intel_i965_driver },
821 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
822 "Sandybridge", NULL, &intel_gen6_driver },
823 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
824 "Sandybridge", NULL, &intel_gen6_driver },
825 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
826 "Sandybridge", NULL, &intel_gen6_driver },
827 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
828 "Sandybridge", NULL, &intel_gen6_driver },
829 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
830 "Sandybridge", NULL, &intel_gen6_driver },
831 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
832 "Sandybridge", NULL, &intel_gen6_driver },
833 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
834 "Sandybridge", NULL, &intel_gen6_driver },
835 { 0, 0, NULL, NULL, NULL }
836}; 732};
837 733
838static int __devinit intel_gmch_probe(struct pci_dev *pdev,
839 struct agp_bridge_data *bridge)
840{
841 int i, mask;
842
843 bridge->driver = NULL;
844
845 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
846 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
847 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
848 bridge->driver =
849 intel_agp_chipsets[i].gmch_driver;
850 break;
851 }
852 }
853
854 if (!bridge->driver)
855 return 0;
856
857 bridge->dev_private_data = &intel_private;
858 bridge->dev = pdev;
859
860 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
861
862 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
863 mask = 40;
864 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
865 mask = 36;
866 else
867 mask = 32;
868
869 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
870 dev_err(&intel_private.pcidev->dev,
871 "set gfx device dma mask %d-bit failed!\n", mask);
872 else
873 pci_set_consistent_dma_mask(intel_private.pcidev,
874 DMA_BIT_MASK(mask));
875
876 return 1;
877}
878
879static int __devinit agp_intel_probe(struct pci_dev *pdev, 734static int __devinit agp_intel_probe(struct pci_dev *pdev,
880 const struct pci_device_id *ent) 735 const struct pci_device_id *ent)
881{ 736{
@@ -905,7 +760,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
905 } 760 }
906 } 761 }
907 762
908 if (intel_agp_chipsets[i].name == NULL) { 763 if (!bridge->driver) {
909 if (cap_ptr) 764 if (cap_ptr)
910 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 765 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
911 pdev->vendor, pdev->device); 766 pdev->vendor, pdev->device);
@@ -913,14 +768,6 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
913 return -ENODEV; 768 return -ENODEV;
914 } 769 }
915 770
916 if (!bridge->driver) {
917 if (cap_ptr)
918 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
919 intel_agp_chipsets[i].gmch_chip_id);
920 agp_put_bridge(bridge);
921 return -ENODEV;
922 }
923
924 bridge->dev = pdev; 771 bridge->dev = pdev;
925 bridge->dev_private_data = NULL; 772 bridge->dev_private_data = NULL;
926 773
@@ -972,8 +819,7 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
972 819
973 agp_remove_bridge(bridge); 820 agp_remove_bridge(bridge);
974 821
975 if (intel_private.pcidev) 822 intel_gmch_remove(pdev);
976 pci_dev_put(intel_private.pcidev);
977 823
978 agp_put_bridge(bridge); 824 agp_put_bridge(bridge);
979} 825}
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index d09b1ab7e8ab..90539df02504 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -215,44 +215,7 @@
215#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ 215#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
216#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A 216#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
217 217
218/* cover 915 and 945 variants */ 218int intel_gmch_probe(struct pci_dev *pdev,
219#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 219 struct agp_bridge_data *bridge);
220 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 220void intel_gmch_remove(struct pci_dev *pdev);
221 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
222 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
223 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
224 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
225
226#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
227 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
228 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
229 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
230 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
231 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
232
233#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
234 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
235 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
236 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
237 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
238
239#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
240 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
241
242#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
243 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
244 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)
245
246#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
247 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
248 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
249 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
250 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
251 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
252 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
253 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
254 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
255 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
256 IS_SNB)
257
258#endif 221#endif
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 75e0a3497888..248ac5f8708e 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -15,6 +15,18 @@
15 * /fairy-tale-mode off 15 * /fairy-tale-mode off
16 */ 16 */
17 17
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/pagemap.h>
23#include <linux/agp_backend.h>
24#include <asm/smp.h>
25#include "agp.h"
26#include "intel-agp.h"
27#include <linux/intel-gtt.h>
28#include <drm/intel-gtt.h>
29
18/* 30/*
19 * If we have Intel graphics, we're not going to have anything other than 31 * If we have Intel graphics, we're not going to have anything other than
20 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
@@ -69,18 +81,26 @@ static struct gatt_mask intel_gen6_masks[] =
69 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, 81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
70}; 82};
71 83
84struct intel_gtt_driver {
85 unsigned int gen : 8;
86 unsigned int is_g33 : 1;
87 unsigned int is_pineview : 1;
88 unsigned int is_ironlake : 1;
89 /* Chipset specific GTT setup */
90 int (*setup)(void);
91};
92
72static struct _intel_private { 93static struct _intel_private {
94 struct intel_gtt base;
95 const struct intel_gtt_driver *driver;
73 struct pci_dev *pcidev; /* device one */ 96 struct pci_dev *pcidev; /* device one */
97 struct pci_dev *bridge_dev;
74 u8 __iomem *registers; 98 u8 __iomem *registers;
99 phys_addr_t gtt_bus_addr;
100 phys_addr_t gma_bus_addr;
101 phys_addr_t pte_bus_addr;
75 u32 __iomem *gtt; /* I915G */ 102 u32 __iomem *gtt; /* I915G */
76 int num_dcache_entries; 103 int num_dcache_entries;
77 /* gtt_entries is the number of gtt entries that are already mapped
78 * to stolen memory. Stolen memory is larger than the memory mapped
79 * through gtt_entries, as it includes some reserved space for the BIOS
80 * popup and for the GTT.
81 */
82 int gtt_entries; /* i830+ */
83 int gtt_total_size;
84 union { 104 union {
85 void __iomem *i9xx_flush_page; 105 void __iomem *i9xx_flush_page;
86 void *i8xx_flush_page; 106 void *i8xx_flush_page;
@@ -90,6 +110,11 @@ static struct _intel_private {
90 int resource_valid; 110 int resource_valid;
91} intel_private; 111} intel_private;
92 112
113#define INTEL_GTT_GEN intel_private.driver->gen
114#define IS_G33 intel_private.driver->is_g33
115#define IS_PINEVIEW intel_private.driver->is_pineview
116#define IS_IRONLAKE intel_private.driver->is_ironlake
117
93#ifdef USE_PCI_DMA_API 118#ifdef USE_PCI_DMA_API
94static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 119static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
95{ 120{
@@ -215,11 +240,12 @@ static int intel_i810_fetch_size(void)
215 u32 smram_miscc; 240 u32 smram_miscc;
216 struct aper_size_info_fixed *values; 241 struct aper_size_info_fixed *values;
217 242
218 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 243 pci_read_config_dword(intel_private.bridge_dev,
244 I810_SMRAM_MISCC, &smram_miscc);
219 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 245 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
220 246
221 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 247 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
222 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); 248 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
223 return 0; 249 return 0;
224 } 250 }
225 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 251 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
@@ -284,7 +310,7 @@ static void intel_i810_cleanup(void)
284 iounmap(intel_private.registers); 310 iounmap(intel_private.registers);
285} 311}
286 312
287static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 313static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
288{ 314{
289 return; 315 return;
290} 316}
@@ -514,8 +540,7 @@ static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
514 return addr | bridge->driver->masks[type].mask; 540 return addr | bridge->driver->masks[type].mask;
515} 541}
516 542
517static struct aper_size_info_fixed intel_i830_sizes[] = 543static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
518{
519 {128, 32768, 5}, 544 {128, 32768, 5},
520 /* The 64M mode still requires a 128k gatt */ 545 /* The 64M mode still requires a 128k gatt */
521 {64, 16384, 5}, 546 {64, 16384, 5},
@@ -523,102 +548,49 @@ static struct aper_size_info_fixed intel_i830_sizes[] =
523 {512, 131072, 7}, 548 {512, 131072, 7},
524}; 549};
525 550
526static void intel_i830_init_gtt_entries(void) 551static unsigned int intel_gtt_stolen_entries(void)
527{ 552{
528 u16 gmch_ctrl; 553 u16 gmch_ctrl;
529 int gtt_entries = 0;
530 u8 rdct; 554 u8 rdct;
531 int local = 0; 555 int local = 0;
532 static const int ddt[4] = { 0, 16, 32, 64 }; 556 static const int ddt[4] = { 0, 16, 32, 64 };
533 int size; /* reserved space (in kb) at the top of stolen memory */ 557 unsigned int overhead_entries, stolen_entries;
558 unsigned int stolen_size = 0;
534 559
535 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 560 pci_read_config_word(intel_private.bridge_dev,
561 I830_GMCH_CTRL, &gmch_ctrl);
536 562
537 if (IS_I965) { 563 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
538 u32 pgetbl_ctl; 564 overhead_entries = 0;
539 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 565 else
566 overhead_entries = intel_private.base.gtt_mappable_entries
567 / 1024;
540 568
541 /* The 965 has a field telling us the size of the GTT, 569 overhead_entries += 1; /* BIOS popup */
542 * which may be larger than what is necessary to map the
543 * aperture.
544 */
545 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
546 case I965_PGETBL_SIZE_128KB:
547 size = 128;
548 break;
549 case I965_PGETBL_SIZE_256KB:
550 size = 256;
551 break;
552 case I965_PGETBL_SIZE_512KB:
553 size = 512;
554 break;
555 case I965_PGETBL_SIZE_1MB:
556 size = 1024;
557 break;
558 case I965_PGETBL_SIZE_2MB:
559 size = 2048;
560 break;
561 case I965_PGETBL_SIZE_1_5MB:
562 size = 1024 + 512;
563 break;
564 default:
565 dev_info(&intel_private.pcidev->dev,
566 "unknown page table size, assuming 512KB\n");
567 size = 512;
568 }
569 size += 4; /* add in BIOS popup space */
570 } else if (IS_G33 && !IS_PINEVIEW) {
571 /* G33's GTT size defined in gmch_ctrl */
572 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
573 case G33_PGETBL_SIZE_1M:
574 size = 1024;
575 break;
576 case G33_PGETBL_SIZE_2M:
577 size = 2048;
578 break;
579 default:
580 dev_info(&agp_bridge->dev->dev,
581 "unknown page table size 0x%x, assuming 512KB\n",
582 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
583 size = 512;
584 }
585 size += 4;
586 } else if (IS_G4X || IS_PINEVIEW) {
587 /* On 4 series hardware, GTT stolen is separate from graphics
588 * stolen, ignore it in stolen gtt entries counting. However,
589 * 4KB of the stolen memory doesn't get mapped to the GTT.
590 */
591 size = 4;
592 } else {
593 /* On previous hardware, the GTT size was just what was
594 * required to map the aperture.
595 */
596 size = agp_bridge->driver->fetch_size() + 4;
597 }
598 570
599 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 571 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
600 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 572 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
601 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 573 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
602 case I830_GMCH_GMS_STOLEN_512: 574 case I830_GMCH_GMS_STOLEN_512:
603 gtt_entries = KB(512) - KB(size); 575 stolen_size = KB(512);
604 break; 576 break;
605 case I830_GMCH_GMS_STOLEN_1024: 577 case I830_GMCH_GMS_STOLEN_1024:
606 gtt_entries = MB(1) - KB(size); 578 stolen_size = MB(1);
607 break; 579 break;
608 case I830_GMCH_GMS_STOLEN_8192: 580 case I830_GMCH_GMS_STOLEN_8192:
609 gtt_entries = MB(8) - KB(size); 581 stolen_size = MB(8);
610 break; 582 break;
611 case I830_GMCH_GMS_LOCAL: 583 case I830_GMCH_GMS_LOCAL:
612 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 584 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
613 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 585 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
614 MB(ddt[I830_RDRAM_DDT(rdct)]); 586 MB(ddt[I830_RDRAM_DDT(rdct)]);
615 local = 1; 587 local = 1;
616 break; 588 break;
617 default: 589 default:
618 gtt_entries = 0; 590 stolen_size = 0;
619 break; 591 break;
620 } 592 }
621 } else if (IS_SNB) { 593 } else if (INTEL_GTT_GEN == 6) {
622 /* 594 /*
623 * SandyBridge has new memory control reg at 0x50.w 595 * SandyBridge has new memory control reg at 0x50.w
624 */ 596 */
@@ -626,142 +598,254 @@ static void intel_i830_init_gtt_entries(void)
626 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 598 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
627 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 599 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
628 case SNB_GMCH_GMS_STOLEN_32M: 600 case SNB_GMCH_GMS_STOLEN_32M:
629 gtt_entries = MB(32) - KB(size); 601 stolen_size = MB(32);
630 break; 602 break;
631 case SNB_GMCH_GMS_STOLEN_64M: 603 case SNB_GMCH_GMS_STOLEN_64M:
632 gtt_entries = MB(64) - KB(size); 604 stolen_size = MB(64);
633 break; 605 break;
634 case SNB_GMCH_GMS_STOLEN_96M: 606 case SNB_GMCH_GMS_STOLEN_96M:
635 gtt_entries = MB(96) - KB(size); 607 stolen_size = MB(96);
636 break; 608 break;
637 case SNB_GMCH_GMS_STOLEN_128M: 609 case SNB_GMCH_GMS_STOLEN_128M:
638 gtt_entries = MB(128) - KB(size); 610 stolen_size = MB(128);
639 break; 611 break;
640 case SNB_GMCH_GMS_STOLEN_160M: 612 case SNB_GMCH_GMS_STOLEN_160M:
641 gtt_entries = MB(160) - KB(size); 613 stolen_size = MB(160);
642 break; 614 break;
643 case SNB_GMCH_GMS_STOLEN_192M: 615 case SNB_GMCH_GMS_STOLEN_192M:
644 gtt_entries = MB(192) - KB(size); 616 stolen_size = MB(192);
645 break; 617 break;
646 case SNB_GMCH_GMS_STOLEN_224M: 618 case SNB_GMCH_GMS_STOLEN_224M:
647 gtt_entries = MB(224) - KB(size); 619 stolen_size = MB(224);
648 break; 620 break;
649 case SNB_GMCH_GMS_STOLEN_256M: 621 case SNB_GMCH_GMS_STOLEN_256M:
650 gtt_entries = MB(256) - KB(size); 622 stolen_size = MB(256);
651 break; 623 break;
652 case SNB_GMCH_GMS_STOLEN_288M: 624 case SNB_GMCH_GMS_STOLEN_288M:
653 gtt_entries = MB(288) - KB(size); 625 stolen_size = MB(288);
654 break; 626 break;
655 case SNB_GMCH_GMS_STOLEN_320M: 627 case SNB_GMCH_GMS_STOLEN_320M:
656 gtt_entries = MB(320) - KB(size); 628 stolen_size = MB(320);
657 break; 629 break;
658 case SNB_GMCH_GMS_STOLEN_352M: 630 case SNB_GMCH_GMS_STOLEN_352M:
659 gtt_entries = MB(352) - KB(size); 631 stolen_size = MB(352);
660 break; 632 break;
661 case SNB_GMCH_GMS_STOLEN_384M: 633 case SNB_GMCH_GMS_STOLEN_384M:
662 gtt_entries = MB(384) - KB(size); 634 stolen_size = MB(384);
663 break; 635 break;
664 case SNB_GMCH_GMS_STOLEN_416M: 636 case SNB_GMCH_GMS_STOLEN_416M:
665 gtt_entries = MB(416) - KB(size); 637 stolen_size = MB(416);
666 break; 638 break;
667 case SNB_GMCH_GMS_STOLEN_448M: 639 case SNB_GMCH_GMS_STOLEN_448M:
668 gtt_entries = MB(448) - KB(size); 640 stolen_size = MB(448);
669 break; 641 break;
670 case SNB_GMCH_GMS_STOLEN_480M: 642 case SNB_GMCH_GMS_STOLEN_480M:
671 gtt_entries = MB(480) - KB(size); 643 stolen_size = MB(480);
672 break; 644 break;
673 case SNB_GMCH_GMS_STOLEN_512M: 645 case SNB_GMCH_GMS_STOLEN_512M:
674 gtt_entries = MB(512) - KB(size); 646 stolen_size = MB(512);
675 break; 647 break;
676 } 648 }
677 } else { 649 } else {
678 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 650 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
679 case I855_GMCH_GMS_STOLEN_1M: 651 case I855_GMCH_GMS_STOLEN_1M:
680 gtt_entries = MB(1) - KB(size); 652 stolen_size = MB(1);
681 break; 653 break;
682 case I855_GMCH_GMS_STOLEN_4M: 654 case I855_GMCH_GMS_STOLEN_4M:
683 gtt_entries = MB(4) - KB(size); 655 stolen_size = MB(4);
684 break; 656 break;
685 case I855_GMCH_GMS_STOLEN_8M: 657 case I855_GMCH_GMS_STOLEN_8M:
686 gtt_entries = MB(8) - KB(size); 658 stolen_size = MB(8);
687 break; 659 break;
688 case I855_GMCH_GMS_STOLEN_16M: 660 case I855_GMCH_GMS_STOLEN_16M:
689 gtt_entries = MB(16) - KB(size); 661 stolen_size = MB(16);
690 break; 662 break;
691 case I855_GMCH_GMS_STOLEN_32M: 663 case I855_GMCH_GMS_STOLEN_32M:
692 gtt_entries = MB(32) - KB(size); 664 stolen_size = MB(32);
693 break; 665 break;
694 case I915_GMCH_GMS_STOLEN_48M: 666 case I915_GMCH_GMS_STOLEN_48M:
695 /* Check it's really I915G */ 667 stolen_size = MB(48);
696 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
697 gtt_entries = MB(48) - KB(size);
698 else
699 gtt_entries = 0;
700 break; 668 break;
701 case I915_GMCH_GMS_STOLEN_64M: 669 case I915_GMCH_GMS_STOLEN_64M:
702 /* Check it's really I915G */ 670 stolen_size = MB(64);
703 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
704 gtt_entries = MB(64) - KB(size);
705 else
706 gtt_entries = 0;
707 break; 671 break;
708 case G33_GMCH_GMS_STOLEN_128M: 672 case G33_GMCH_GMS_STOLEN_128M:
709 if (IS_G33 || IS_I965 || IS_G4X) 673 stolen_size = MB(128);
710 gtt_entries = MB(128) - KB(size);
711 else
712 gtt_entries = 0;
713 break; 674 break;
714 case G33_GMCH_GMS_STOLEN_256M: 675 case G33_GMCH_GMS_STOLEN_256M:
715 if (IS_G33 || IS_I965 || IS_G4X) 676 stolen_size = MB(256);
716 gtt_entries = MB(256) - KB(size);
717 else
718 gtt_entries = 0;
719 break; 677 break;
720 case INTEL_GMCH_GMS_STOLEN_96M: 678 case INTEL_GMCH_GMS_STOLEN_96M:
721 if (IS_I965 || IS_G4X) 679 stolen_size = MB(96);
722 gtt_entries = MB(96) - KB(size);
723 else
724 gtt_entries = 0;
725 break; 680 break;
726 case INTEL_GMCH_GMS_STOLEN_160M: 681 case INTEL_GMCH_GMS_STOLEN_160M:
727 if (IS_I965 || IS_G4X) 682 stolen_size = MB(160);
728 gtt_entries = MB(160) - KB(size);
729 else
730 gtt_entries = 0;
731 break; 683 break;
732 case INTEL_GMCH_GMS_STOLEN_224M: 684 case INTEL_GMCH_GMS_STOLEN_224M:
733 if (IS_I965 || IS_G4X) 685 stolen_size = MB(224);
734 gtt_entries = MB(224) - KB(size);
735 else
736 gtt_entries = 0;
737 break; 686 break;
738 case INTEL_GMCH_GMS_STOLEN_352M: 687 case INTEL_GMCH_GMS_STOLEN_352M:
739 if (IS_I965 || IS_G4X) 688 stolen_size = MB(352);
740 gtt_entries = MB(352) - KB(size);
741 else
742 gtt_entries = 0;
743 break; 689 break;
744 default: 690 default:
745 gtt_entries = 0; 691 stolen_size = 0;
746 break; 692 break;
747 } 693 }
748 } 694 }
749 if (!local && gtt_entries > intel_max_stolen) { 695
750 dev_info(&agp_bridge->dev->dev, 696 if (!local && stolen_size > intel_max_stolen) {
697 dev_info(&intel_private.bridge_dev->dev,
751 "detected %dK stolen memory, trimming to %dK\n", 698 "detected %dK stolen memory, trimming to %dK\n",
752 gtt_entries / KB(1), intel_max_stolen / KB(1)); 699 stolen_size / KB(1), intel_max_stolen / KB(1));
753 gtt_entries = intel_max_stolen / KB(4); 700 stolen_size = intel_max_stolen;
754 } else if (gtt_entries > 0) { 701 } else if (stolen_size > 0) {
755 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", 702 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
756 gtt_entries / KB(1), local ? "local" : "stolen"); 703 stolen_size / KB(1), local ? "local" : "stolen");
757 gtt_entries /= KB(4);
758 } else { 704 } else {
759 dev_info(&agp_bridge->dev->dev, 705 dev_info(&intel_private.bridge_dev->dev,
760 "no pre-allocated video memory detected\n"); 706 "no pre-allocated video memory detected\n");
761 gtt_entries = 0; 707 stolen_size = 0;
708 }
709
710 stolen_entries = stolen_size/KB(4) - overhead_entries;
711
712 return stolen_entries;
713}
714
715static unsigned int intel_gtt_total_entries(void)
716{
717 int size;
718
719 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
720 u32 pgetbl_ctl;
721 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
722
723 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
724 case I965_PGETBL_SIZE_128KB:
725 size = KB(128);
726 break;
727 case I965_PGETBL_SIZE_256KB:
728 size = KB(256);
729 break;
730 case I965_PGETBL_SIZE_512KB:
731 size = KB(512);
732 break;
733 case I965_PGETBL_SIZE_1MB:
734 size = KB(1024);
735 break;
736 case I965_PGETBL_SIZE_2MB:
737 size = KB(2048);
738 break;
739 case I965_PGETBL_SIZE_1_5MB:
740 size = KB(1024 + 512);
741 break;
742 default:
743 dev_info(&intel_private.pcidev->dev,
744 "unknown page table size, assuming 512KB\n");
745 size = KB(512);
746 }
747
748 return size/4;
749 } else if (INTEL_GTT_GEN == 6) {
750 u16 snb_gmch_ctl;
751
752 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
753 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
754 default:
755 case SNB_GTT_SIZE_0M:
756 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
757 size = MB(0);
758 break;
759 case SNB_GTT_SIZE_1M:
760 size = MB(1);
761 break;
762 case SNB_GTT_SIZE_2M:
763 size = MB(2);
764 break;
765 }
766 return size/4;
767 } else {
768 /* On previous hardware, the GTT size was just what was
769 * required to map the aperture.
770 */
771 return intel_private.base.gtt_mappable_entries;
772 }
773}
774
775static unsigned int intel_gtt_mappable_entries(void)
776{
777 unsigned int aperture_size;
778
779 if (INTEL_GTT_GEN == 2) {
780 u16 gmch_ctrl;
781
782 pci_read_config_word(intel_private.bridge_dev,
783 I830_GMCH_CTRL, &gmch_ctrl);
784
785 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
786 aperture_size = MB(64);
787 else
788 aperture_size = MB(128);
789 } else {
790 /* 9xx supports large sizes, just look at the length */
791 aperture_size = pci_resource_len(intel_private.pcidev, 2);
762 } 792 }
763 793
764 intel_private.gtt_entries = gtt_entries; 794 return aperture_size >> PAGE_SHIFT;
795}
796
797static int intel_gtt_init(void)
798{
799 u32 gtt_map_size;
800 int ret;
801
802 ret = intel_private.driver->setup();
803 if (ret != 0)
804 return ret;
805
806 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
807 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
808
809 gtt_map_size = intel_private.base.gtt_total_entries * 4;
810
811 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
812 gtt_map_size);
813 if (!intel_private.gtt) {
814 iounmap(intel_private.registers);
815 return -ENOMEM;
816 }
817
818 global_cache_flush(); /* FIXME: ? */
819
820 /* we have to call this as early as possible after the MMIO base address is known */
821 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
822 if (intel_private.base.gtt_stolen_entries == 0) {
823 iounmap(intel_private.registers);
824 iounmap(intel_private.gtt);
825 return -ENOMEM;
826 }
827
828 return 0;
829}
830
831static int intel_fake_agp_fetch_size(void)
832{
833 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
834 unsigned int aper_size;
835 int i;
836
837 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
838 / MB(1);
839
840 for (i = 0; i < num_sizes; i++) {
841 if (aper_size == intel_fake_agp_sizes[i].size) {
842 agp_bridge->current_size =
843 (void *) (intel_fake_agp_sizes + i);
844 return aper_size;
845 }
846 }
847
848 return 0;
765} 849}
766 850
767static void intel_i830_fini_flush(void) 851static void intel_i830_fini_flush(void)
@@ -811,120 +895,84 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
811 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 895 printk(KERN_ERR "Timed out waiting for cache flush.\n");
812} 896}
813 897
814/* The intel i830 automatically initializes the agp aperture during POST. 898static void intel_enable_gtt(void)
815 * Use the memory already set aside for in the GTT.
816 */
817static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
818{ 899{
819 int page_order; 900 u32 gma_addr;
820 struct aper_size_info_fixed *size; 901 u16 gmch_ctrl;
821 int num_entries;
822 u32 temp;
823 902
824 size = agp_bridge->current_size; 903 if (INTEL_GTT_GEN == 2)
825 page_order = size->page_order; 904 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
826 num_entries = size->num_entries; 905 &gma_addr);
827 agp_bridge->gatt_table_real = NULL; 906 else
907 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
908 &gma_addr);
828 909
829 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 910 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
830 temp &= 0xfff80000;
831 911
832 intel_private.registers = ioremap(temp, 128 * 4096); 912 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
833 if (!intel_private.registers) 913 gmch_ctrl |= I830_GMCH_ENABLED;
834 return -ENOMEM; 914 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
835 915
836 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 916 writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED,
837 global_cache_flush(); /* FIXME: ?? */ 917 intel_private.registers+I810_PGETBL_CTL);
918 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
919}
838 920
839 /* we have to call this as early as possible after the MMIO base address is known */ 921static int i830_setup(void)
840 intel_i830_init_gtt_entries(); 922{
841 if (intel_private.gtt_entries == 0) { 923 u32 reg_addr;
842 iounmap(intel_private.registers); 924
925 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
926 reg_addr &= 0xfff80000;
927
928 intel_private.registers = ioremap(reg_addr, KB(64));
929 if (!intel_private.registers)
843 return -ENOMEM; 930 return -ENOMEM;
844 }
845 931
846 agp_bridge->gatt_table = NULL; 932 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
933 intel_private.pte_bus_addr =
934 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
847 935
848 agp_bridge->gatt_bus_addr = temp; 936 intel_i830_setup_flush();
849 937
850 return 0; 938 return 0;
851} 939}
852 940
853/* Return the gatt table to a sane state. Use the top of stolen 941static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
854 * memory for the GTT.
855 */
856static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
857{ 942{
943 agp_bridge->gatt_table_real = NULL;
944 agp_bridge->gatt_table = NULL;
945 agp_bridge->gatt_bus_addr = 0;
946
858 return 0; 947 return 0;
859} 948}
860 949
861static int intel_i830_fetch_size(void) 950static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
862{ 951{
863 u16 gmch_ctrl;
864 struct aper_size_info_fixed *values;
865
866 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
867
868 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
869 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
870 /* 855GM/852GM/865G has 128MB aperture size */
871 agp_bridge->current_size = (void *) values;
872 agp_bridge->aperture_size_idx = 0;
873 return values[0].size;
874 }
875
876 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
877
878 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
879 agp_bridge->current_size = (void *) values;
880 agp_bridge->aperture_size_idx = 0;
881 return values[0].size;
882 } else {
883 agp_bridge->current_size = (void *) (values + 1);
884 agp_bridge->aperture_size_idx = 1;
885 return values[1].size;
886 }
887
888 return 0; 952 return 0;
889} 953}
890 954
891static int intel_i830_configure(void) 955static int intel_i830_configure(void)
892{ 956{
893 struct aper_size_info_fixed *current_size;
894 u32 temp;
895 u16 gmch_ctrl;
896 int i; 957 int i;
897 958
898 current_size = A_SIZE_FIX(agp_bridge->current_size); 959 intel_enable_gtt();
899 960
900 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 961 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
901 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
902
903 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
904 gmch_ctrl |= I830_GMCH_ENABLED;
905 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
906
907 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
908 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
909 962
910 if (agp_bridge->driver->needs_scratch_page) { 963 if (agp_bridge->driver->needs_scratch_page) {
911 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 964 for (i = intel_private.base.gtt_stolen_entries;
912 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 965 i < intel_private.base.gtt_total_entries; i++) {
966 writel(agp_bridge->scratch_page, intel_private.gtt+i);
913 } 967 }
914 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ 968 readl(intel_private.gtt+i-1); /* PCI Posting. */
915 } 969 }
916 970
917 global_cache_flush(); 971 global_cache_flush();
918 972
919 intel_i830_setup_flush();
920 return 0; 973 return 0;
921} 974}
922 975
923static void intel_i830_cleanup(void)
924{
925 iounmap(intel_private.registers);
926}
927
928static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 976static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
929 int type) 977 int type)
930{ 978{
@@ -939,10 +987,10 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
939 temp = agp_bridge->current_size; 987 temp = agp_bridge->current_size;
940 num_entries = A_SIZE_FIX(temp)->num_entries; 988 num_entries = A_SIZE_FIX(temp)->num_entries;
941 989
942 if (pg_start < intel_private.gtt_entries) { 990 if (pg_start < intel_private.base.gtt_stolen_entries) {
943 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 991 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
944 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 992 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
945 pg_start, intel_private.gtt_entries); 993 pg_start, intel_private.base.gtt_stolen_entries);
946 994
947 dev_info(&intel_private.pcidev->dev, 995 dev_info(&intel_private.pcidev->dev,
948 "trying to insert into local/stolen memory\n"); 996 "trying to insert into local/stolen memory\n");
@@ -971,9 +1019,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
971 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1019 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
972 writel(agp_bridge->driver->mask_memory(agp_bridge, 1020 writel(agp_bridge->driver->mask_memory(agp_bridge,
973 page_to_phys(mem->pages[i]), mask_type), 1021 page_to_phys(mem->pages[i]), mask_type),
974 intel_private.registers+I810_PTE_BASE+(j*4)); 1022 intel_private.gtt+j);
975 } 1023 }
976 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 1024 readl(intel_private.gtt+j-1);
977 1025
978out: 1026out:
979 ret = 0; 1027 ret = 0;
@@ -990,21 +1038,22 @@ static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
990 if (mem->page_count == 0) 1038 if (mem->page_count == 0)
991 return 0; 1039 return 0;
992 1040
993 if (pg_start < intel_private.gtt_entries) { 1041 if (pg_start < intel_private.base.gtt_stolen_entries) {
994 dev_info(&intel_private.pcidev->dev, 1042 dev_info(&intel_private.pcidev->dev,
995 "trying to disable local/stolen memory\n"); 1043 "trying to disable local/stolen memory\n");
996 return -EINVAL; 1044 return -EINVAL;
997 } 1045 }
998 1046
999 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1047 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1000 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 1048 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1001 } 1049 }
1002 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 1050 readl(intel_private.gtt+i-1);
1003 1051
1004 return 0; 1052 return 0;
1005} 1053}
1006 1054
1007static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 1055static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1056 int type)
1008{ 1057{
1009 if (type == AGP_PHYS_MEMORY) 1058 if (type == AGP_PHYS_MEMORY)
1010 return alloc_agpphysmem_i8xx(pg_count, type); 1059 return alloc_agpphysmem_i8xx(pg_count, type);
@@ -1015,9 +1064,9 @@ static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1015static int intel_alloc_chipset_flush_resource(void) 1064static int intel_alloc_chipset_flush_resource(void)
1016{ 1065{
1017 int ret; 1066 int ret;
1018 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1067 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1019 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1068 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1020 pcibios_align_resource, agp_bridge->dev); 1069 pcibios_align_resource, intel_private.bridge_dev);
1021 1070
1022 return ret; 1071 return ret;
1023} 1072}
@@ -1027,11 +1076,11 @@ static void intel_i915_setup_chipset_flush(void)
1027 int ret; 1076 int ret;
1028 u32 temp; 1077 u32 temp;
1029 1078
1030 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 1079 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1031 if (!(temp & 0x1)) { 1080 if (!(temp & 0x1)) {
1032 intel_alloc_chipset_flush_resource(); 1081 intel_alloc_chipset_flush_resource();
1033 intel_private.resource_valid = 1; 1082 intel_private.resource_valid = 1;
1034 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1083 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1035 } else { 1084 } else {
1036 temp &= ~1; 1085 temp &= ~1;
1037 1086
@@ -1050,17 +1099,17 @@ static void intel_i965_g33_setup_chipset_flush(void)
1050 u32 temp_hi, temp_lo; 1099 u32 temp_hi, temp_lo;
1051 int ret; 1100 int ret;
1052 1101
1053 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1102 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1054 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1103 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1055 1104
1056 if (!(temp_lo & 0x1)) { 1105 if (!(temp_lo & 0x1)) {
1057 1106
1058 intel_alloc_chipset_flush_resource(); 1107 intel_alloc_chipset_flush_resource();
1059 1108
1060 intel_private.resource_valid = 1; 1109 intel_private.resource_valid = 1;
1061 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1110 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1062 upper_32_bits(intel_private.ifp_resource.start)); 1111 upper_32_bits(intel_private.ifp_resource.start));
1063 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1112 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1064 } else { 1113 } else {
1065 u64 l64; 1114 u64 l64;
1066 1115
@@ -1083,7 +1132,7 @@ static void intel_i9xx_setup_flush(void)
1083 if (intel_private.ifp_resource.start) 1132 if (intel_private.ifp_resource.start)
1084 return; 1133 return;
1085 1134
1086 if (IS_SNB) 1135 if (INTEL_GTT_GEN == 6)
1087 return; 1136 return;
1088 1137
1089 /* setup a resource for this object */ 1138 /* setup a resource for this object */
@@ -1091,7 +1140,7 @@ static void intel_i9xx_setup_flush(void)
1091 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1140 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1092 1141
1093 /* Setup chipset flush for 915 */ 1142 /* Setup chipset flush for 915 */
1094 if (IS_I965 || IS_G33 || IS_G4X) { 1143 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1095 intel_i965_g33_setup_chipset_flush(); 1144 intel_i965_g33_setup_chipset_flush();
1096 } else { 1145 } else {
1097 intel_i915_setup_chipset_flush(); 1146 intel_i915_setup_chipset_flush();
@@ -1106,26 +1155,15 @@ static void intel_i9xx_setup_flush(void)
1106 1155
1107static int intel_i9xx_configure(void) 1156static int intel_i9xx_configure(void)
1108{ 1157{
1109 struct aper_size_info_fixed *current_size;
1110 u32 temp;
1111 u16 gmch_ctrl;
1112 int i; 1158 int i;
1113 1159
1114 current_size = A_SIZE_FIX(agp_bridge->current_size); 1160 intel_enable_gtt();
1115 1161
1116 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); 1162 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1117
1118 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1119
1120 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1121 gmch_ctrl |= I830_GMCH_ENABLED;
1122 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1123
1124 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1125 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1126 1163
1127 if (agp_bridge->driver->needs_scratch_page) { 1164 if (agp_bridge->driver->needs_scratch_page) {
1128 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { 1165 for (i = intel_private.base.gtt_stolen_entries; i <
1166 intel_private.base.gtt_total_entries; i++) {
1129 writel(agp_bridge->scratch_page, intel_private.gtt+i); 1167 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1130 } 1168 }
1131 readl(intel_private.gtt+i-1); /* PCI Posting. */ 1169 readl(intel_private.gtt+i-1); /* PCI Posting. */
@@ -1133,12 +1171,10 @@ static int intel_i9xx_configure(void)
1133 1171
1134 global_cache_flush(); 1172 global_cache_flush();
1135 1173
1136 intel_i9xx_setup_flush();
1137
1138 return 0; 1174 return 0;
1139} 1175}
1140 1176
1141static void intel_i915_cleanup(void) 1177static void intel_gtt_cleanup(void)
1142{ 1178{
1143 if (intel_private.i9xx_flush_page) 1179 if (intel_private.i9xx_flush_page)
1144 iounmap(intel_private.i9xx_flush_page); 1180 iounmap(intel_private.i9xx_flush_page);
@@ -1170,10 +1206,10 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1170 temp = agp_bridge->current_size; 1206 temp = agp_bridge->current_size;
1171 num_entries = A_SIZE_FIX(temp)->num_entries; 1207 num_entries = A_SIZE_FIX(temp)->num_entries;
1172 1208
1173 if (pg_start < intel_private.gtt_entries) { 1209 if (pg_start < intel_private.base.gtt_stolen_entries) {
1174 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 1210 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1175 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", 1211 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1176 pg_start, intel_private.gtt_entries); 1212 pg_start, intel_private.base.gtt_stolen_entries);
1177 1213
1178 dev_info(&intel_private.pcidev->dev, 1214 dev_info(&intel_private.pcidev->dev,
1179 "trying to insert into local/stolen memory\n"); 1215 "trying to insert into local/stolen memory\n");
@@ -1192,7 +1228,8 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1192 1228
1193 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1229 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1194 1230
1195 if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1231 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1232 mask_type != AGP_PHYS_MEMORY &&
1196 mask_type != INTEL_AGP_CACHED_MEMORY) 1233 mask_type != INTEL_AGP_CACHED_MEMORY)
1197 goto out_err; 1234 goto out_err;
1198 1235
@@ -1216,7 +1253,7 @@ static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1216 if (mem->page_count == 0) 1253 if (mem->page_count == 0)
1217 return 0; 1254 return 0;
1218 1255
1219 if (pg_start < intel_private.gtt_entries) { 1256 if (pg_start < intel_private.base.gtt_stolen_entries) {
1220 dev_info(&intel_private.pcidev->dev, 1257 dev_info(&intel_private.pcidev->dev,
1221 "trying to disable local/stolen memory\n"); 1258 "trying to disable local/stolen memory\n");
1222 return -EINVAL; 1259 return -EINVAL;
@@ -1230,112 +1267,44 @@ static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1230 return 0; 1267 return 0;
1231} 1268}
1232 1269
1233/* Return the aperture size by just checking the resource length. The effect 1270static int i9xx_setup(void)
1234 * described in the spec of the MSAC registers is just changing of the
1235 * resource size.
1236 */
1237static int intel_i9xx_fetch_size(void)
1238{ 1271{
1239 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1272 u32 reg_addr;
1240 int aper_size; /* size in megabytes */
1241 int i;
1242 1273
1243 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1274 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1244 1275
1245 for (i = 0; i < num_sizes; i++) { 1276 reg_addr &= 0xfff80000;
1246 if (aper_size == intel_i830_sizes[i].size) {
1247 agp_bridge->current_size = intel_i830_sizes + i;
1248 return aper_size;
1249 }
1250 }
1251 1277
1252 return 0; 1278 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1253} 1279 if (!intel_private.registers)
1280 return -ENOMEM;
1254 1281
1255static int intel_i915_get_gtt_size(void) 1282 if (INTEL_GTT_GEN == 3) {
1256{ 1283 u32 gtt_addr;
1257 int size;
1258 1284
1259 if (IS_G33) { 1285 pci_read_config_dword(intel_private.pcidev,
1260 u16 gmch_ctrl; 1286 I915_PTEADDR, &gtt_addr);
1287 intel_private.gtt_bus_addr = gtt_addr;
1288 } else {
1289 u32 gtt_offset;
1261 1290
1262 /* G33's GTT size defined in gmch_ctrl */ 1291 switch (INTEL_GTT_GEN) {
1263 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 1292 case 5:
1264 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 1293 case 6:
1265 case I830_GMCH_GMS_STOLEN_512: 1294 gtt_offset = MB(2);
1266 size = 512;
1267 break;
1268 case I830_GMCH_GMS_STOLEN_1024:
1269 size = 1024;
1270 break;
1271 case I830_GMCH_GMS_STOLEN_8192:
1272 size = 8*1024;
1273 break; 1295 break;
1296 case 4:
1274 default: 1297 default:
1275 dev_info(&agp_bridge->dev->dev, 1298 gtt_offset = KB(512);
1276 "unknown page table size 0x%x, assuming 512KB\n", 1299 break;
1277 (gmch_ctrl & I830_GMCH_GMS_MASK));
1278 size = 512;
1279 } 1300 }
1280 } else { 1301 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1281 /* On previous hardware, the GTT size was just what was
1282 * required to map the aperture.
1283 */
1284 size = agp_bridge->driver->fetch_size();
1285 }
1286
1287 return KB(size);
1288}
1289
1290/* The intel i915 automatically initializes the agp aperture during POST.
1291 * Use the memory already set aside for in the GTT.
1292 */
1293static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1294{
1295 int page_order;
1296 struct aper_size_info_fixed *size;
1297 int num_entries;
1298 u32 temp, temp2;
1299 int gtt_map_size;
1300
1301 size = agp_bridge->current_size;
1302 page_order = size->page_order;
1303 num_entries = size->num_entries;
1304 agp_bridge->gatt_table_real = NULL;
1305
1306 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1307 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1308
1309 gtt_map_size = intel_i915_get_gtt_size();
1310
1311 intel_private.gtt = ioremap(temp2, gtt_map_size);
1312 if (!intel_private.gtt)
1313 return -ENOMEM;
1314
1315 intel_private.gtt_total_size = gtt_map_size / 4;
1316
1317 temp &= 0xfff80000;
1318
1319 intel_private.registers = ioremap(temp, 128 * 4096);
1320 if (!intel_private.registers) {
1321 iounmap(intel_private.gtt);
1322 return -ENOMEM;
1323 } 1302 }
1324 1303
1325 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1304 intel_private.pte_bus_addr =
1326 global_cache_flush(); /* FIXME: ? */ 1305 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1327
1328 /* we have to call this as early as possible after the MMIO base address is known */
1329 intel_i830_init_gtt_entries();
1330 if (intel_private.gtt_entries == 0) {
1331 iounmap(intel_private.gtt);
1332 iounmap(intel_private.registers);
1333 return -ENOMEM;
1334 }
1335
1336 agp_bridge->gatt_table = NULL;
1337 1306
1338 agp_bridge->gatt_bus_addr = temp; 1307 intel_i9xx_setup_flush();
1339 1308
1340 return 0; 1309 return 0;
1341} 1310}
@@ -1369,101 +1338,6 @@ static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1369 return addr | bridge->driver->masks[type].mask; 1338 return addr | bridge->driver->masks[type].mask;
1370} 1339}
1371 1340
1372static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1373{
1374 u16 snb_gmch_ctl;
1375
1376 switch (agp_bridge->dev->device) {
1377 case PCI_DEVICE_ID_INTEL_GM45_HB:
1378 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1379 case PCI_DEVICE_ID_INTEL_Q45_HB:
1380 case PCI_DEVICE_ID_INTEL_G45_HB:
1381 case PCI_DEVICE_ID_INTEL_G41_HB:
1382 case PCI_DEVICE_ID_INTEL_B43_HB:
1383 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1384 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1385 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1386 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1387 *gtt_offset = *gtt_size = MB(2);
1388 break;
1389 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1390 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1391 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
1392 *gtt_offset = MB(2);
1393
1394 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1395 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1396 default:
1397 case SNB_GTT_SIZE_0M:
1398 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1399 *gtt_size = MB(0);
1400 break;
1401 case SNB_GTT_SIZE_1M:
1402 *gtt_size = MB(1);
1403 break;
1404 case SNB_GTT_SIZE_2M:
1405 *gtt_size = MB(2);
1406 break;
1407 }
1408 break;
1409 default:
1410 *gtt_offset = *gtt_size = KB(512);
1411 }
1412}
1413
1414/* The intel i965 automatically initializes the agp aperture during POST.
1415 * Use the memory already set aside for in the GTT.
1416 */
1417static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1418{
1419 int page_order;
1420 struct aper_size_info_fixed *size;
1421 int num_entries;
1422 u32 temp;
1423 int gtt_offset, gtt_size;
1424
1425 size = agp_bridge->current_size;
1426 page_order = size->page_order;
1427 num_entries = size->num_entries;
1428 agp_bridge->gatt_table_real = NULL;
1429
1430 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1431
1432 temp &= 0xfff00000;
1433
1434 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1435
1436 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1437
1438 if (!intel_private.gtt)
1439 return -ENOMEM;
1440
1441 intel_private.gtt_total_size = gtt_size / 4;
1442
1443 intel_private.registers = ioremap(temp, 128 * 4096);
1444 if (!intel_private.registers) {
1445 iounmap(intel_private.gtt);
1446 return -ENOMEM;
1447 }
1448
1449 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1450 global_cache_flush(); /* FIXME: ? */
1451
1452 /* we have to call this as early as possible after the MMIO base address is known */
1453 intel_i830_init_gtt_entries();
1454 if (intel_private.gtt_entries == 0) {
1455 iounmap(intel_private.gtt);
1456 iounmap(intel_private.registers);
1457 return -ENOMEM;
1458 }
1459
1460 agp_bridge->gatt_table = NULL;
1461
1462 agp_bridge->gatt_bus_addr = temp;
1463
1464 return 0;
1465}
1466
1467static const struct agp_bridge_driver intel_810_driver = { 1341static const struct agp_bridge_driver intel_810_driver = {
1468 .owner = THIS_MODULE, 1342 .owner = THIS_MODULE,
1469 .aperture_sizes = intel_i810_sizes, 1343 .aperture_sizes = intel_i810_sizes,
@@ -1475,7 +1349,7 @@ static const struct agp_bridge_driver intel_810_driver = {
1475 .cleanup = intel_i810_cleanup, 1349 .cleanup = intel_i810_cleanup,
1476 .mask_memory = intel_i810_mask_memory, 1350 .mask_memory = intel_i810_mask_memory,
1477 .masks = intel_i810_masks, 1351 .masks = intel_i810_masks,
1478 .agp_enable = intel_i810_agp_enable, 1352 .agp_enable = intel_fake_agp_enable,
1479 .cache_flush = global_cache_flush, 1353 .cache_flush = global_cache_flush,
1480 .create_gatt_table = agp_generic_create_gatt_table, 1354 .create_gatt_table = agp_generic_create_gatt_table,
1481 .free_gatt_table = agp_generic_free_gatt_table, 1355 .free_gatt_table = agp_generic_free_gatt_table,
@@ -1492,22 +1366,22 @@ static const struct agp_bridge_driver intel_810_driver = {
1492 1366
1493static const struct agp_bridge_driver intel_830_driver = { 1367static const struct agp_bridge_driver intel_830_driver = {
1494 .owner = THIS_MODULE, 1368 .owner = THIS_MODULE,
1495 .aperture_sizes = intel_i830_sizes,
1496 .size_type = FIXED_APER_SIZE, 1369 .size_type = FIXED_APER_SIZE,
1497 .num_aperture_sizes = 4, 1370 .aperture_sizes = intel_fake_agp_sizes,
1371 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1498 .needs_scratch_page = true, 1372 .needs_scratch_page = true,
1499 .configure = intel_i830_configure, 1373 .configure = intel_i830_configure,
1500 .fetch_size = intel_i830_fetch_size, 1374 .fetch_size = intel_fake_agp_fetch_size,
1501 .cleanup = intel_i830_cleanup, 1375 .cleanup = intel_gtt_cleanup,
1502 .mask_memory = intel_i810_mask_memory, 1376 .mask_memory = intel_i810_mask_memory,
1503 .masks = intel_i810_masks, 1377 .masks = intel_i810_masks,
1504 .agp_enable = intel_i810_agp_enable, 1378 .agp_enable = intel_fake_agp_enable,
1505 .cache_flush = global_cache_flush, 1379 .cache_flush = global_cache_flush,
1506 .create_gatt_table = intel_i830_create_gatt_table, 1380 .create_gatt_table = intel_fake_agp_create_gatt_table,
1507 .free_gatt_table = intel_i830_free_gatt_table, 1381 .free_gatt_table = intel_fake_agp_free_gatt_table,
1508 .insert_memory = intel_i830_insert_entries, 1382 .insert_memory = intel_i830_insert_entries,
1509 .remove_memory = intel_i830_remove_entries, 1383 .remove_memory = intel_i830_remove_entries,
1510 .alloc_by_type = intel_i830_alloc_by_type, 1384 .alloc_by_type = intel_fake_agp_alloc_by_type,
1511 .free_by_type = intel_i810_free_by_type, 1385 .free_by_type = intel_i810_free_by_type,
1512 .agp_alloc_page = agp_generic_alloc_page, 1386 .agp_alloc_page = agp_generic_alloc_page,
1513 .agp_alloc_pages = agp_generic_alloc_pages, 1387 .agp_alloc_pages = agp_generic_alloc_pages,
@@ -1519,22 +1393,22 @@ static const struct agp_bridge_driver intel_830_driver = {
1519 1393
1520static const struct agp_bridge_driver intel_915_driver = { 1394static const struct agp_bridge_driver intel_915_driver = {
1521 .owner = THIS_MODULE, 1395 .owner = THIS_MODULE,
1522 .aperture_sizes = intel_i830_sizes,
1523 .size_type = FIXED_APER_SIZE, 1396 .size_type = FIXED_APER_SIZE,
1524 .num_aperture_sizes = 4, 1397 .aperture_sizes = intel_fake_agp_sizes,
1398 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1525 .needs_scratch_page = true, 1399 .needs_scratch_page = true,
1526 .configure = intel_i9xx_configure, 1400 .configure = intel_i9xx_configure,
1527 .fetch_size = intel_i9xx_fetch_size, 1401 .fetch_size = intel_fake_agp_fetch_size,
1528 .cleanup = intel_i915_cleanup, 1402 .cleanup = intel_gtt_cleanup,
1529 .mask_memory = intel_i810_mask_memory, 1403 .mask_memory = intel_i810_mask_memory,
1530 .masks = intel_i810_masks, 1404 .masks = intel_i810_masks,
1531 .agp_enable = intel_i810_agp_enable, 1405 .agp_enable = intel_fake_agp_enable,
1532 .cache_flush = global_cache_flush, 1406 .cache_flush = global_cache_flush,
1533 .create_gatt_table = intel_i915_create_gatt_table, 1407 .create_gatt_table = intel_fake_agp_create_gatt_table,
1534 .free_gatt_table = intel_i830_free_gatt_table, 1408 .free_gatt_table = intel_fake_agp_free_gatt_table,
1535 .insert_memory = intel_i915_insert_entries, 1409 .insert_memory = intel_i915_insert_entries,
1536 .remove_memory = intel_i915_remove_entries, 1410 .remove_memory = intel_i915_remove_entries,
1537 .alloc_by_type = intel_i830_alloc_by_type, 1411 .alloc_by_type = intel_fake_agp_alloc_by_type,
1538 .free_by_type = intel_i810_free_by_type, 1412 .free_by_type = intel_i810_free_by_type,
1539 .agp_alloc_page = agp_generic_alloc_page, 1413 .agp_alloc_page = agp_generic_alloc_page,
1540 .agp_alloc_pages = agp_generic_alloc_pages, 1414 .agp_alloc_pages = agp_generic_alloc_pages,
@@ -1552,22 +1426,22 @@ static const struct agp_bridge_driver intel_915_driver = {
1552 1426
1553static const struct agp_bridge_driver intel_i965_driver = { 1427static const struct agp_bridge_driver intel_i965_driver = {
1554 .owner = THIS_MODULE, 1428 .owner = THIS_MODULE,
1555 .aperture_sizes = intel_i830_sizes,
1556 .size_type = FIXED_APER_SIZE, 1429 .size_type = FIXED_APER_SIZE,
1557 .num_aperture_sizes = 4, 1430 .aperture_sizes = intel_fake_agp_sizes,
1431 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1558 .needs_scratch_page = true, 1432 .needs_scratch_page = true,
1559 .configure = intel_i9xx_configure, 1433 .configure = intel_i9xx_configure,
1560 .fetch_size = intel_i9xx_fetch_size, 1434 .fetch_size = intel_fake_agp_fetch_size,
1561 .cleanup = intel_i915_cleanup, 1435 .cleanup = intel_gtt_cleanup,
1562 .mask_memory = intel_i965_mask_memory, 1436 .mask_memory = intel_i965_mask_memory,
1563 .masks = intel_i810_masks, 1437 .masks = intel_i810_masks,
1564 .agp_enable = intel_i810_agp_enable, 1438 .agp_enable = intel_fake_agp_enable,
1565 .cache_flush = global_cache_flush, 1439 .cache_flush = global_cache_flush,
1566 .create_gatt_table = intel_i965_create_gatt_table, 1440 .create_gatt_table = intel_fake_agp_create_gatt_table,
1567 .free_gatt_table = intel_i830_free_gatt_table, 1441 .free_gatt_table = intel_fake_agp_free_gatt_table,
1568 .insert_memory = intel_i915_insert_entries, 1442 .insert_memory = intel_i915_insert_entries,
1569 .remove_memory = intel_i915_remove_entries, 1443 .remove_memory = intel_i915_remove_entries,
1570 .alloc_by_type = intel_i830_alloc_by_type, 1444 .alloc_by_type = intel_fake_agp_alloc_by_type,
1571 .free_by_type = intel_i810_free_by_type, 1445 .free_by_type = intel_i810_free_by_type,
1572 .agp_alloc_page = agp_generic_alloc_page, 1446 .agp_alloc_page = agp_generic_alloc_page,
1573 .agp_alloc_pages = agp_generic_alloc_pages, 1447 .agp_alloc_pages = agp_generic_alloc_pages,
@@ -1585,22 +1459,22 @@ static const struct agp_bridge_driver intel_i965_driver = {
1585 1459
1586static const struct agp_bridge_driver intel_gen6_driver = { 1460static const struct agp_bridge_driver intel_gen6_driver = {
1587 .owner = THIS_MODULE, 1461 .owner = THIS_MODULE,
1588 .aperture_sizes = intel_i830_sizes,
1589 .size_type = FIXED_APER_SIZE, 1462 .size_type = FIXED_APER_SIZE,
1590 .num_aperture_sizes = 4, 1463 .aperture_sizes = intel_fake_agp_sizes,
1464 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1591 .needs_scratch_page = true, 1465 .needs_scratch_page = true,
1592 .configure = intel_i9xx_configure, 1466 .configure = intel_i9xx_configure,
1593 .fetch_size = intel_i9xx_fetch_size, 1467 .fetch_size = intel_fake_agp_fetch_size,
1594 .cleanup = intel_i915_cleanup, 1468 .cleanup = intel_gtt_cleanup,
1595 .mask_memory = intel_gen6_mask_memory, 1469 .mask_memory = intel_gen6_mask_memory,
1596 .masks = intel_gen6_masks, 1470 .masks = intel_gen6_masks,
1597 .agp_enable = intel_i810_agp_enable, 1471 .agp_enable = intel_fake_agp_enable,
1598 .cache_flush = global_cache_flush, 1472 .cache_flush = global_cache_flush,
1599 .create_gatt_table = intel_i965_create_gatt_table, 1473 .create_gatt_table = intel_fake_agp_create_gatt_table,
1600 .free_gatt_table = intel_i830_free_gatt_table, 1474 .free_gatt_table = intel_fake_agp_free_gatt_table,
1601 .insert_memory = intel_i915_insert_entries, 1475 .insert_memory = intel_i915_insert_entries,
1602 .remove_memory = intel_i915_remove_entries, 1476 .remove_memory = intel_i915_remove_entries,
1603 .alloc_by_type = intel_i830_alloc_by_type, 1477 .alloc_by_type = intel_fake_agp_alloc_by_type,
1604 .free_by_type = intel_i810_free_by_type, 1478 .free_by_type = intel_i810_free_by_type,
1605 .agp_alloc_page = agp_generic_alloc_page, 1479 .agp_alloc_page = agp_generic_alloc_page,
1606 .agp_alloc_pages = agp_generic_alloc_pages, 1480 .agp_alloc_pages = agp_generic_alloc_pages,
@@ -1618,22 +1492,22 @@ static const struct agp_bridge_driver intel_gen6_driver = {
1618 1492
1619static const struct agp_bridge_driver intel_g33_driver = { 1493static const struct agp_bridge_driver intel_g33_driver = {
1620 .owner = THIS_MODULE, 1494 .owner = THIS_MODULE,
1621 .aperture_sizes = intel_i830_sizes,
1622 .size_type = FIXED_APER_SIZE, 1495 .size_type = FIXED_APER_SIZE,
1623 .num_aperture_sizes = 4, 1496 .aperture_sizes = intel_fake_agp_sizes,
1497 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1624 .needs_scratch_page = true, 1498 .needs_scratch_page = true,
1625 .configure = intel_i9xx_configure, 1499 .configure = intel_i9xx_configure,
1626 .fetch_size = intel_i9xx_fetch_size, 1500 .fetch_size = intel_fake_agp_fetch_size,
1627 .cleanup = intel_i915_cleanup, 1501 .cleanup = intel_gtt_cleanup,
1628 .mask_memory = intel_i965_mask_memory, 1502 .mask_memory = intel_i965_mask_memory,
1629 .masks = intel_i810_masks, 1503 .masks = intel_i810_masks,
1630 .agp_enable = intel_i810_agp_enable, 1504 .agp_enable = intel_fake_agp_enable,
1631 .cache_flush = global_cache_flush, 1505 .cache_flush = global_cache_flush,
1632 .create_gatt_table = intel_i915_create_gatt_table, 1506 .create_gatt_table = intel_fake_agp_create_gatt_table,
1633 .free_gatt_table = intel_i830_free_gatt_table, 1507 .free_gatt_table = intel_fake_agp_free_gatt_table,
1634 .insert_memory = intel_i915_insert_entries, 1508 .insert_memory = intel_i915_insert_entries,
1635 .remove_memory = intel_i915_remove_entries, 1509 .remove_memory = intel_i915_remove_entries,
1636 .alloc_by_type = intel_i830_alloc_by_type, 1510 .alloc_by_type = intel_fake_agp_alloc_by_type,
1637 .free_by_type = intel_i810_free_by_type, 1511 .free_by_type = intel_i810_free_by_type,
1638 .agp_alloc_page = agp_generic_alloc_page, 1512 .agp_alloc_page = agp_generic_alloc_page,
1639 .agp_alloc_pages = agp_generic_alloc_pages, 1513 .agp_alloc_pages = agp_generic_alloc_pages,
@@ -1648,3 +1522,217 @@ static const struct agp_bridge_driver intel_g33_driver = {
1648 .agp_unmap_memory = intel_agp_unmap_memory, 1522 .agp_unmap_memory = intel_agp_unmap_memory,
1649#endif 1523#endif
1650}; 1524};
1525
1526static const struct intel_gtt_driver i8xx_gtt_driver = {
1527 .gen = 2,
1528 .setup = i830_setup,
1529};
1530static const struct intel_gtt_driver i915_gtt_driver = {
1531 .gen = 3,
1532 .setup = i9xx_setup,
1533};
1534static const struct intel_gtt_driver g33_gtt_driver = {
1535 .gen = 3,
1536 .is_g33 = 1,
1537 .setup = i9xx_setup,
1538};
1539static const struct intel_gtt_driver pineview_gtt_driver = {
1540 .gen = 3,
1541 .is_pineview = 1, .is_g33 = 1,
1542 .setup = i9xx_setup,
1543};
1544static const struct intel_gtt_driver i965_gtt_driver = {
1545 .gen = 4,
1546 .setup = i9xx_setup,
1547};
1548static const struct intel_gtt_driver g4x_gtt_driver = {
1549 .gen = 5,
1550 .setup = i9xx_setup,
1551};
1552static const struct intel_gtt_driver ironlake_gtt_driver = {
1553 .gen = 5,
1554 .is_ironlake = 1,
1555 .setup = i9xx_setup,
1556};
1557static const struct intel_gtt_driver sandybridge_gtt_driver = {
1558 .gen = 6,
1559 .setup = i9xx_setup,
1560};
1561
1562/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1563 * driver and gmch_driver must be non-null, and find_gmch will determine
1564 * which one should be used if a gmch_chip_id is present.
1565 */
1566static const struct intel_gtt_driver_description {
1567 unsigned int gmch_chip_id;
1568 char *name;
1569 const struct agp_bridge_driver *gmch_driver;
1570 const struct intel_gtt_driver *gtt_driver;
1571} intel_gtt_chipsets[] = {
1572 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1573 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1574 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1575 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1576 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1577 &intel_830_driver , &i8xx_gtt_driver},
1578 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1579 &intel_830_driver , &i8xx_gtt_driver},
1580 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1581 &intel_830_driver , &i8xx_gtt_driver},
1582 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1583 &intel_830_driver , &i8xx_gtt_driver},
1584 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1585 &intel_830_driver , &i8xx_gtt_driver},
1586 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1587 &intel_915_driver , &i915_gtt_driver },
1588 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1589 &intel_915_driver , &i915_gtt_driver },
1590 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1591 &intel_915_driver , &i915_gtt_driver },
1592 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1593 &intel_915_driver , &i915_gtt_driver },
1594 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1595 &intel_915_driver , &i915_gtt_driver },
1596 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1597 &intel_915_driver , &i915_gtt_driver },
1598 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1599 &intel_i965_driver , &i965_gtt_driver },
1600 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1601 &intel_i965_driver , &i965_gtt_driver },
1602 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1603 &intel_i965_driver , &i965_gtt_driver },
1604 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1605 &intel_i965_driver , &i965_gtt_driver },
1606 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1607 &intel_i965_driver , &i965_gtt_driver },
1608 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1609 &intel_i965_driver , &i965_gtt_driver },
1610 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1611 &intel_g33_driver , &g33_gtt_driver },
1612 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1613 &intel_g33_driver , &g33_gtt_driver },
1614 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1615 &intel_g33_driver , &g33_gtt_driver },
1616 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1617 &intel_g33_driver , &pineview_gtt_driver },
1618 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1619 &intel_g33_driver , &pineview_gtt_driver },
1620 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1621 &intel_i965_driver , &g4x_gtt_driver },
1622 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1623 &intel_i965_driver , &g4x_gtt_driver },
1624 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1625 &intel_i965_driver , &g4x_gtt_driver },
1626 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1627 &intel_i965_driver , &g4x_gtt_driver },
1628 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1629 &intel_i965_driver , &g4x_gtt_driver },
1630 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1631 &intel_i965_driver , &g4x_gtt_driver },
1632 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1633 &intel_i965_driver , &g4x_gtt_driver },
1634 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1635 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1636 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1637 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1638 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1639 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1640 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1641 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1642 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1643 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1644 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1645 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1646 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1647 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1648 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1649 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1650 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1651 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1652 { 0, NULL, NULL }
1653};
1654
1655static int find_gmch(u16 device)
1656{
1657 struct pci_dev *gmch_device;
1658
1659 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1660 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1661 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1662 device, gmch_device);
1663 }
1664
1665 if (!gmch_device)
1666 return 0;
1667
1668 intel_private.pcidev = gmch_device;
1669 return 1;
1670}
1671
1672int intel_gmch_probe(struct pci_dev *pdev,
1673 struct agp_bridge_data *bridge)
1674{
1675 int i, mask;
1676 bridge->driver = NULL;
1677
1678 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1679 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1680 bridge->driver =
1681 intel_gtt_chipsets[i].gmch_driver;
1682 intel_private.driver =
1683 intel_gtt_chipsets[i].gtt_driver;
1684 break;
1685 }
1686 }
1687
1688 if (!bridge->driver)
1689 return 0;
1690
1691 bridge->dev_private_data = &intel_private;
1692 bridge->dev = pdev;
1693
1694 intel_private.bridge_dev = pci_dev_get(pdev);
1695
1696 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1697
1698 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1699 mask = 40;
1700 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1701 mask = 36;
1702 else
1703 mask = 32;
1704
1705 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1706 dev_err(&intel_private.pcidev->dev,
1707 "set gfx device dma mask %d-bit failed!\n", mask);
1708 else
1709 pci_set_consistent_dma_mask(intel_private.pcidev,
1710 DMA_BIT_MASK(mask));
1711
1712 if (bridge->driver == &intel_810_driver)
1713 return 1;
1714
1715 if (intel_gtt_init() != 0)
1716 return 0;
1717
1718 return 1;
1719}
1720EXPORT_SYMBOL(intel_gmch_probe);
1721
1722struct intel_gtt *intel_gtt_get(void)
1723{
1724 return &intel_private.base;
1725}
1726EXPORT_SYMBOL(intel_gtt_get);
1727
1728void intel_gmch_remove(struct pci_dev *pdev)
1729{
1730 if (intel_private.pcidev)
1731 pci_dev_put(intel_private.pcidev);
1732 if (intel_private.bridge_dev)
1733 pci_dev_put(intel_private.bridge_dev);
1734}
1735EXPORT_SYMBOL(intel_gmch_remove);
1736
1737MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1738MODULE_LICENSE("GPL and additional rights");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 09:15:29 -0500