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-rw-r--r--drivers/char/agp/intel-agp.c34
1 files changed, 31 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a3e10dc7cc25..b78d5c381efe 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled);
97#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 97#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
99 99
100#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
102
100#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ 103#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 104 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
@@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled);
107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ 110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ 111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ 112 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ 113 IS_SNB)
111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
112 114
113extern int agp_memory_reserved; 115extern int agp_memory_reserved;
114 116
@@ -175,6 +177,10 @@ extern int agp_memory_reserved;
175#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 177#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
176#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 178#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
177#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 179#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
180#define SNB_GTT_SIZE_0M (0 << 8)
181#define SNB_GTT_SIZE_1M (1 << 8)
182#define SNB_GTT_SIZE_2M (2 << 8)
183#define SNB_GTT_SIZE_MASK (3 << 8)
178 184
179static const struct aper_size_info_fixed intel_i810_sizes[] = 185static const struct aper_size_info_fixed intel_i810_sizes[] =
180{ 186{
@@ -1200,6 +1206,9 @@ static void intel_i9xx_setup_flush(void)
1200 if (intel_private.ifp_resource.start) 1206 if (intel_private.ifp_resource.start)
1201 return; 1207 return;
1202 1208
1209 if (IS_SNB)
1210 return;
1211
1203 /* setup a resource for this object */ 1212 /* setup a resource for this object */
1204 intel_private.ifp_resource.name = "Intel Flush Page"; 1213 intel_private.ifp_resource.name = "Intel Flush Page";
1205 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1214 intel_private.ifp_resource.flags = IORESOURCE_MEM;
@@ -1438,6 +1447,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1438 1447
1439static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1448static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1440{ 1449{
1450 u16 snb_gmch_ctl;
1451
1441 switch (agp_bridge->dev->device) { 1452 switch (agp_bridge->dev->device) {
1442 case PCI_DEVICE_ID_INTEL_GM45_HB: 1453 case PCI_DEVICE_ID_INTEL_GM45_HB:
1443 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: 1454 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
@@ -1449,9 +1460,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1449 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: 1460 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1450 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: 1461 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1451 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: 1462 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1463 *gtt_offset = *gtt_size = MB(2);
1464 break;
1452 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: 1465 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1453 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: 1466 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1454 *gtt_offset = *gtt_size = MB(2); 1467 *gtt_offset = MB(2);
1468
1469 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1470 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1471 default:
1472 case SNB_GTT_SIZE_0M:
1473 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1474 *gtt_size = MB(0);
1475 break;
1476 case SNB_GTT_SIZE_1M:
1477 *gtt_size = MB(1);
1478 break;
1479 case SNB_GTT_SIZE_2M:
1480 *gtt_size = MB(2);
1481 break;
1482 }
1455 break; 1483 break;
1456 default: 1484 default:
1457 *gtt_offset = *gtt_size = KB(512); 1485 *gtt_offset = *gtt_size = KB(512);