diff options
Diffstat (limited to 'drivers/char')
-rw-r--r-- | drivers/char/drm/r300_cmdbuf.c | 50 | ||||
-rw-r--r-- | drivers/char/drm/r300_reg.h | 3 | ||||
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 3 |
3 files changed, 55 insertions, 1 deletions
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c index 291dbf4c8186..6dd21754ba67 100644 --- a/drivers/char/drm/r300_cmdbuf.c +++ b/drivers/char/drm/r300_cmdbuf.c | |||
@@ -161,6 +161,7 @@ void r300_init_reg_flags(void) | |||
161 | ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); | 161 | ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); |
162 | ADD_RANGE(R300_GB_ENABLE, 1); | 162 | ADD_RANGE(R300_GB_ENABLE, 1); |
163 | ADD_RANGE(R300_GB_MSPOS0, 5); | 163 | ADD_RANGE(R300_GB_MSPOS0, 5); |
164 | ADD_RANGE(R300_TX_CNTL, 1); | ||
164 | ADD_RANGE(R300_TX_ENABLE, 1); | 165 | ADD_RANGE(R300_TX_ENABLE, 1); |
165 | ADD_RANGE(0x4200, 4); | 166 | ADD_RANGE(0x4200, 4); |
166 | ADD_RANGE(0x4214, 1); | 167 | ADD_RANGE(0x4214, 1); |
@@ -489,6 +490,52 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, | |||
489 | 490 | ||
490 | return 0; | 491 | return 0; |
491 | } | 492 | } |
493 | static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, | ||
494 | drm_radeon_kcmd_buffer_t *cmdbuf) | ||
495 | { | ||
496 | u32 *cmd = (u32 *) cmdbuf->buf; | ||
497 | int count, ret; | ||
498 | RING_LOCALS; | ||
499 | |||
500 | count=(cmd[0]>>16) & 0x3fff; | ||
501 | |||
502 | if (cmd[0] & 0x8000) { | ||
503 | u32 offset; | ||
504 | |||
505 | if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | ||
506 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | ||
507 | offset = cmd[2] << 10; | ||
508 | ret = r300_check_offset(dev_priv, offset); | ||
509 | if (ret) | ||
510 | { | ||
511 | DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); | ||
512 | return DRM_ERR(EINVAL); | ||
513 | } | ||
514 | } | ||
515 | |||
516 | if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && | ||
517 | (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | ||
518 | offset = cmd[3] << 10; | ||
519 | ret = r300_check_offset(dev_priv, offset); | ||
520 | if (ret) | ||
521 | { | ||
522 | DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); | ||
523 | return DRM_ERR(EINVAL); | ||
524 | } | ||
525 | |||
526 | } | ||
527 | } | ||
528 | |||
529 | BEGIN_RING(count+2); | ||
530 | OUT_RING(cmd[0]); | ||
531 | OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); | ||
532 | ADVANCE_RING(); | ||
533 | |||
534 | cmdbuf->buf += (count+2)*4; | ||
535 | cmdbuf->bufsz -= (count+2)*4; | ||
536 | |||
537 | return 0; | ||
538 | } | ||
492 | 539 | ||
493 | static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, | 540 | static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, |
494 | drm_radeon_kcmd_buffer_t *cmdbuf) | 541 | drm_radeon_kcmd_buffer_t *cmdbuf) |
@@ -527,6 +574,9 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, | |||
527 | case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ | 574 | case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ |
528 | return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); | 575 | return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); |
529 | 576 | ||
577 | case RADEON_CNTL_BITBLT_MULTI: | ||
578 | return r300_emit_bitblt_multi(dev_priv, cmdbuf); | ||
579 | |||
530 | case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ | 580 | case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ |
531 | case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ | 581 | case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ |
532 | case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ | 582 | case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ |
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h index a0ed20e25221..d1e19954406b 100644 --- a/drivers/char/drm/r300_reg.h +++ b/drivers/char/drm/r300_reg.h | |||
@@ -451,6 +451,9 @@ I am fairly certain that they are correct unless stated otherwise in comments. | |||
451 | /* END */ | 451 | /* END */ |
452 | 452 | ||
453 | /* gap */ | 453 | /* gap */ |
454 | /* Zero to flush caches. */ | ||
455 | #define R300_TX_CNTL 0x4100 | ||
456 | |||
454 | /* The upper enable bits are guessed, based on fglrx reported limits. */ | 457 | /* The upper enable bits are guessed, based on fglrx reported limits. */ |
455 | #define R300_TX_ENABLE 0x4104 | 458 | #define R300_TX_ENABLE 0x4104 |
456 | # define R300_TX_ENABLE_0 (1 << 0) | 459 | # define R300_TX_ENABLE_0 (1 << 0) |
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 498b19b1d641..1f7d2ab8c4fc 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -90,9 +90,10 @@ | |||
90 | * 1.19- Add support for gart table in FB memory and PCIE r300 | 90 | * 1.19- Add support for gart table in FB memory and PCIE r300 |
91 | * 1.20- Add support for r300 texrect | 91 | * 1.20- Add support for r300 texrect |
92 | * 1.21- Add support for card type getparam | 92 | * 1.21- Add support for card type getparam |
93 | * 1.22- Add support for texture cache flushes (R300_TX_CNTL) | ||
93 | */ | 94 | */ |
94 | #define DRIVER_MAJOR 1 | 95 | #define DRIVER_MAJOR 1 |
95 | #define DRIVER_MINOR 21 | 96 | #define DRIVER_MINOR 22 |
96 | #define DRIVER_PATCHLEVEL 0 | 97 | #define DRIVER_PATCHLEVEL 0 |
97 | 98 | ||
98 | /* | 99 | /* |