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-rw-r--r--drivers/char/drm/radeon_cp.c26
-rw-r--r--drivers/char/drm/radeon_drv.h4
2 files changed, 27 insertions, 3 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 599187558abb..f5e22bfcc3cb 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -113,6 +113,27 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
114} 114}
115 115
116static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
117{
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
120
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
133 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
134 }
135}
136
116static int RADEON_READ_PLL(struct drm_device * dev, int addr) 137static int RADEON_READ_PLL(struct drm_device * dev, int addr)
117{ 138{
118 drm_radeon_private_t *dev_priv = dev->dev_private; 139 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -542,9 +563,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
542 563
543#if __OS_HAS_AGP 564#if __OS_HAS_AGP
544 if (dev_priv->flags & RADEON_IS_AGP) { 565 if (dev_priv->flags & RADEON_IS_AGP) {
545 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 566 radeon_write_agp_base(dev_priv, dev->agp->base);
546 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 567
547 RADEON_WRITE(RADEON_AGP_BASE_2, 0);
548 radeon_write_agp_location(dev_priv, 568 radeon_write_agp_location(dev_priv,
549 (((dev_priv->gart_vm_start - 1 + 569 (((dev_priv->gart_vm_start - 1 +
550 dev_priv->gart_size) & 0xffff0000) | 570 dev_priv->gart_size) & 0xffff0000) |
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index d0dc47cee6c9..f43e1f9b9550 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -522,9 +522,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
522 522
523#define RV515_MC_FB_LOCATION 0x01 523#define RV515_MC_FB_LOCATION 0x01
524#define RV515_MC_AGP_LOCATION 0x02 524#define RV515_MC_AGP_LOCATION 0x02
525#define RV515_MC_AGP_BASE 0x03
526#define RV515_MC_AGP_BASE_2 0x04
525 527
526#define R520_MC_FB_LOCATION 0x04 528#define R520_MC_FB_LOCATION 0x04
527#define R520_MC_AGP_LOCATION 0x05 529#define R520_MC_AGP_LOCATION 0x05
530#define R520_MC_AGP_BASE 0x06
531#define R520_MC_AGP_BASE_2 0x07
528 532
529#define RADEON_MPP_TB_CONFIG 0x01c0 533#define RADEON_MPP_TB_CONFIG 0x01c0
530#define RADEON_MEM_CNTL 0x0140 534#define RADEON_MEM_CNTL 0x0140